1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define i128 @v_shl_i128_vv(i128 %lhs, i128 %rhs) {
5; GCN-LABEL: v_shl_i128_vv:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
9; GCN-NEXT:    v_lshl_b64 v[5:6], v[2:3], v4
10; GCN-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
11; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
12; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
13; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
14; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
15; GCN-NEXT:    v_lshl_b64 v[5:6], v[0:1], v5
16; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
17; GCN-NEXT:    v_lshl_b64 v[0:1], v[0:1], v4
18; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
19; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[4:5]
20; GCN-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc
21; GCN-NEXT:    v_cndmask_b32_e64 v3, v5, v3, s[4:5]
22; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
23; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
24; GCN-NEXT:    s_setpc_b64 s[30:31]
25  %shl = shl i128 %lhs, %rhs
26  ret i128 %shl
27}
28
29define i128 @v_lshr_i128_vv(i128 %lhs, i128 %rhs) {
30; GCN-LABEL: v_lshr_i128_vv:
31; GCN:       ; %bb.0:
32; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
34; GCN-NEXT:    v_lshr_b64 v[5:6], v[0:1], v4
35; GCN-NEXT:    v_lshl_b64 v[7:8], v[2:3], v7
36; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
37; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
38; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
39; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
40; GCN-NEXT:    v_lshr_b64 v[5:6], v[2:3], v5
41; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
42; GCN-NEXT:    v_lshr_b64 v[2:3], v[2:3], v4
43; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
44; GCN-NEXT:    v_cndmask_b32_e64 v0, v5, v0, s[4:5]
45; GCN-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc
46; GCN-NEXT:    v_cndmask_b32_e64 v1, v5, v1, s[4:5]
47; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
48; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
49; GCN-NEXT:    s_setpc_b64 s[30:31]
50
51  %shl = lshr i128 %lhs, %rhs
52  ret i128 %shl
53}
54
55define i128 @v_ashr_i128_vv(i128 %lhs, i128 %rhs) {
56; GCN-LABEL: v_ashr_i128_vv:
57; GCN:       ; %bb.0:
58; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
59; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
60; GCN-NEXT:    v_lshr_b64 v[5:6], v[0:1], v4
61; GCN-NEXT:    v_lshl_b64 v[7:8], v[2:3], v7
62; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
63; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
64; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
65; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
66; GCN-NEXT:    v_ashr_i64 v[5:6], v[2:3], v5
67; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
68; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
69; GCN-NEXT:    v_cndmask_b32_e64 v0, v5, v0, s[4:5]
70; GCN-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc
71; GCN-NEXT:    v_cndmask_b32_e64 v1, v5, v1, s[4:5]
72; GCN-NEXT:    v_ashr_i64 v[4:5], v[2:3], v4
73; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
74; GCN-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
75; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
76; GCN-NEXT:    s_setpc_b64 s[30:31]
77  %shl = ashr i128 %lhs, %rhs
78  ret i128 %shl
79}
80
81
82define i128 @v_shl_i128_vk(i128 %lhs) {
83; GCN-LABEL: v_shl_i128_vk:
84; GCN:       ; %bb.0:
85; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
86; GCN-NEXT:    v_alignbit_b32 v4, v2, v1, 15
87; GCN-NEXT:    v_alignbit_b32 v1, v1, v0, 15
88; GCN-NEXT:    v_alignbit_b32 v3, v3, v2, 15
89; GCN-NEXT:    v_lshlrev_b32_e32 v0, 17, v0
90; GCN-NEXT:    v_mov_b32_e32 v2, v4
91; GCN-NEXT:    s_setpc_b64 s[30:31]
92  %shl = shl i128 %lhs, 17
93  ret i128 %shl
94}
95
96define i128 @v_lshr_i128_vk(i128 %lhs) {
97; GCN-LABEL: v_lshr_i128_vk:
98; GCN:       ; %bb.0:
99; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
100; GCN-NEXT:    v_alignbit_b32 v0, v3, v2, 1
101; GCN-NEXT:    v_lshrrev_b32_e32 v1, 1, v3
102; GCN-NEXT:    v_mov_b32_e32 v2, 0
103; GCN-NEXT:    v_mov_b32_e32 v3, 0
104; GCN-NEXT:    s_setpc_b64 s[30:31]
105  %shl = lshr i128 %lhs, 65
106  ret i128 %shl
107}
108
109define i128 @v_ashr_i128_vk(i128 %lhs) {
110; GCN-LABEL: v_ashr_i128_vk:
111; GCN:       ; %bb.0:
112; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113; GCN-NEXT:    v_ashr_i64 v[4:5], v[2:3], 33
114; GCN-NEXT:    v_alignbit_b32 v0, v2, v1, 1
115; GCN-NEXT:    v_alignbit_b32 v1, v3, v2, 1
116; GCN-NEXT:    v_mov_b32_e32 v2, v4
117; GCN-NEXT:    v_mov_b32_e32 v3, v5
118; GCN-NEXT:    s_setpc_b64 s[30:31]
119  %shl = ashr i128 %lhs, 33
120  ret i128 %shl
121}
122
123define i128 @v_shl_i128_kv(i128 %rhs) {
124; GCN-LABEL: v_shl_i128_kv:
125; GCN:       ; %bb.0:
126; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
127; GCN-NEXT:    v_sub_i32_e32 v1, vcc, 64, v0
128; GCN-NEXT:    v_lshr_b64 v[2:3], 17, v1
129; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, 64, v0
130; GCN-NEXT:    v_lshl_b64 v[4:5], 17, v1
131; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
132; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc
133; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
134; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, v1, s[4:5]
135; GCN-NEXT:    v_lshl_b64 v[0:1], 17, v0
136; GCN-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
137; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[4:5]
138; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
139; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
140; GCN-NEXT:    s_setpc_b64 s[30:31]
141  %shl = shl i128 17, %rhs
142  ret i128 %shl
143}
144
145define i128 @v_lshr_i128_kv(i128 %rhs) {
146; GCN-LABEL: v_lshr_i128_kv:
147; GCN:       ; %bb.0:
148; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
149; GCN-NEXT:    s_mov_b64 s[4:5], 0x41
150; GCN-NEXT:    v_lshr_b64 v[1:2], s[4:5], v0
151; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
152; GCN-NEXT:    v_mov_b32_e32 v3, s4
153; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
154; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
155; GCN-NEXT:    s_and_b64 vcc, s[4:5], vcc
156; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v1, s[4:5]
157; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
158; GCN-NEXT:    v_mov_b32_e32 v2, 0
159; GCN-NEXT:    v_mov_b32_e32 v3, 0
160; GCN-NEXT:    s_setpc_b64 s[30:31]
161  %shl = lshr i128 65, %rhs
162  ret i128 %shl
163}
164
165define i128 @v_ashr_i128_kv(i128 %rhs) {
166; GCN-LABEL: v_ashr_i128_kv:
167; GCN:       ; %bb.0:
168; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
169; GCN-NEXT:    v_lshr_b64 v[1:2], 33, v0
170; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
171; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
172; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
173; GCN-NEXT:    s_and_b64 vcc, s[4:5], vcc
174; GCN-NEXT:    v_cndmask_b32_e64 v0, 33, v1, s[4:5]
175; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
176; GCN-NEXT:    v_mov_b32_e32 v2, 0
177; GCN-NEXT:    v_mov_b32_e32 v3, 0
178; GCN-NEXT:    s_setpc_b64 s[30:31]
179  %shl = ashr i128 33, %rhs
180  ret i128 %shl
181}
182
183define amdgpu_kernel void @s_shl_i128_ss(i128 %lhs, i128 %rhs) {
184; GCN-LABEL: s_shl_i128_ss:
185; GCN:       ; %bb.0:
186; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
187; GCN-NEXT:    v_mov_b32_e32 v4, 0
188; GCN-NEXT:    v_mov_b32_e32 v5, 0
189; GCN-NEXT:    s_waitcnt lgkmcnt(0)
190; GCN-NEXT:    s_sub_i32 s9, 64, s8
191; GCN-NEXT:    s_sub_i32 s2, s8, 64
192; GCN-NEXT:    s_lshl_b64 s[0:1], s[6:7], s8
193; GCN-NEXT:    s_lshr_b64 s[10:11], s[4:5], s9
194; GCN-NEXT:    s_or_b64 s[10:11], s[0:1], s[10:11]
195; GCN-NEXT:    s_lshl_b64 s[2:3], s[4:5], s2
196; GCN-NEXT:    v_mov_b32_e32 v0, s3
197; GCN-NEXT:    v_mov_b32_e32 v1, s11
198; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
199; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
200; GCN-NEXT:    v_mov_b32_e32 v1, s7
201; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
202; GCN-NEXT:    v_cndmask_b32_e64 v3, v0, v1, s[0:1]
203; GCN-NEXT:    v_mov_b32_e32 v0, s2
204; GCN-NEXT:    v_mov_b32_e32 v1, s10
205; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
206; GCN-NEXT:    v_mov_b32_e32 v1, s6
207; GCN-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
208; GCN-NEXT:    s_lshl_b64 s[0:1], s[4:5], s8
209; GCN-NEXT:    v_mov_b32_e32 v0, s1
210; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
211; GCN-NEXT:    v_mov_b32_e32 v0, s0
212; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
213; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
214; GCN-NEXT:    s_endpgm
215  %shift = shl i128 %lhs, %rhs
216  store i128 %shift, i128 addrspace(1)* null
217  ret void
218}
219
220define amdgpu_kernel void @s_lshr_i128_ss(i128 %lhs, i128 %rhs) {
221; GCN-LABEL: s_lshr_i128_ss:
222; GCN:       ; %bb.0:
223; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
224; GCN-NEXT:    v_mov_b32_e32 v4, 0
225; GCN-NEXT:    v_mov_b32_e32 v5, 0
226; GCN-NEXT:    s_waitcnt lgkmcnt(0)
227; GCN-NEXT:    s_sub_i32 s9, 64, s8
228; GCN-NEXT:    s_sub_i32 s2, s8, 64
229; GCN-NEXT:    s_lshr_b64 s[0:1], s[4:5], s8
230; GCN-NEXT:    s_lshl_b64 s[10:11], s[6:7], s9
231; GCN-NEXT:    s_or_b64 s[10:11], s[0:1], s[10:11]
232; GCN-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2
233; GCN-NEXT:    v_mov_b32_e32 v0, s3
234; GCN-NEXT:    v_mov_b32_e32 v1, s11
235; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
236; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
237; GCN-NEXT:    v_mov_b32_e32 v1, s5
238; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
239; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
240; GCN-NEXT:    v_mov_b32_e32 v0, s2
241; GCN-NEXT:    v_mov_b32_e32 v2, s10
242; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
243; GCN-NEXT:    v_mov_b32_e32 v2, s4
244; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
245; GCN-NEXT:    s_lshr_b64 s[0:1], s[6:7], s8
246; GCN-NEXT:    v_mov_b32_e32 v2, s1
247; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
248; GCN-NEXT:    v_mov_b32_e32 v2, s0
249; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
250; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
251; GCN-NEXT:    s_endpgm
252  %shift = lshr i128 %lhs, %rhs
253  store i128 %shift, i128 addrspace(1)* null
254  ret void
255}
256
257define amdgpu_kernel void @s_ashr_i128_ss(i128 %lhs, i128 %rhs) {
258; GCN-LABEL: s_ashr_i128_ss:
259; GCN:       ; %bb.0:
260; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
261; GCN-NEXT:    s_waitcnt lgkmcnt(0)
262; GCN-NEXT:    s_ashr_i64 s[0:1], s[6:7], s8
263; GCN-NEXT:    s_ashr_i32 s2, s7, 31
264; GCN-NEXT:    v_mov_b32_e32 v2, s0
265; GCN-NEXT:    s_sub_i32 s0, s8, 64
266; GCN-NEXT:    v_mov_b32_e32 v0, s2
267; GCN-NEXT:    s_ashr_i64 s[2:3], s[6:7], s0
268; GCN-NEXT:    s_sub_i32 s0, 64, s8
269; GCN-NEXT:    v_mov_b32_e32 v1, s1
270; GCN-NEXT:    s_lshl_b64 s[0:1], s[6:7], s0
271; GCN-NEXT:    s_lshr_b64 s[6:7], s[4:5], s8
272; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
273; GCN-NEXT:    s_or_b64 s[6:7], s[6:7], s[0:1]
274; GCN-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
275; GCN-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
276; GCN-NEXT:    v_mov_b32_e32 v0, s3
277; GCN-NEXT:    v_mov_b32_e32 v1, s7
278; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
279; GCN-NEXT:    v_mov_b32_e32 v1, s5
280; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
281; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
282; GCN-NEXT:    v_mov_b32_e32 v0, s2
283; GCN-NEXT:    v_mov_b32_e32 v4, s6
284; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
285; GCN-NEXT:    v_mov_b32_e32 v6, s4
286; GCN-NEXT:    v_mov_b32_e32 v4, 0
287; GCN-NEXT:    v_mov_b32_e32 v5, 0
288; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s[0:1]
289; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
290; GCN-NEXT:    s_endpgm
291  %shift = ashr i128 %lhs, %rhs
292  store i128 %shift, i128 addrspace(1)* null
293  ret void
294}
295
296define <2 x i128> @v_shl_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
297; GCN-LABEL: v_shl_v2i128_vv:
298; GCN:       ; %bb.0:
299; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
300; GCN-NEXT:    v_sub_i32_e32 v16, vcc, 64, v8
301; GCN-NEXT:    v_lshr_b64 v[16:17], v[0:1], v16
302; GCN-NEXT:    v_lshl_b64 v[18:19], v[2:3], v8
303; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
304; GCN-NEXT:    v_cmp_gt_u64_e64 s[4:5], 64, v[8:9]
305; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
306; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
307; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
308; GCN-NEXT:    v_or_b32_e32 v19, v19, v17
309; GCN-NEXT:    v_or_b32_e32 v18, v18, v16
310; GCN-NEXT:    v_lshl_b64 v[16:17], v[0:1], v9
311; GCN-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
312; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
313; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[4:5]
314; GCN-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
315; GCN-NEXT:    v_sub_i32_e64 v9, s[6:7], 64, v12
316; GCN-NEXT:    v_cndmask_b32_e64 v11, v17, v19, s[4:5]
317; GCN-NEXT:    v_lshr_b64 v[9:10], v[4:5], v9
318; GCN-NEXT:    v_lshl_b64 v[16:17], v[6:7], v12
319; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
320; GCN-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc
321; GCN-NEXT:    v_or_b32_e32 v16, v16, v9
322; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[12:13]
323; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
324; GCN-NEXT:    v_or_b32_e32 v11, v17, v10
325; GCN-NEXT:    v_lshl_b64 v[9:10], v[4:5], v9
326; GCN-NEXT:    v_or_b32_e32 v15, v13, v15
327; GCN-NEXT:    v_or_b32_e32 v14, v12, v14
328; GCN-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
329; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
330; GCN-NEXT:    v_lshl_b64 v[0:1], v[0:1], v8
331; GCN-NEXT:    v_lshl_b64 v[4:5], v[4:5], v12
332; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
333; GCN-NEXT:    v_cndmask_b32_e64 v6, v9, v6, s[6:7]
334; GCN-NEXT:    v_cndmask_b32_e32 v9, v10, v11, vcc
335; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v7, s[6:7]
336; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v0, s[4:5]
337; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[4:5]
338; GCN-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
339; GCN-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
340; GCN-NEXT:    s_setpc_b64 s[30:31]
341  %shl = shl <2 x i128> %lhs, %rhs
342  ret <2 x i128> %shl
343}
344
345define <2 x i128> @v_lshr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
346; GCN-LABEL: v_lshr_v2i128_vv:
347; GCN:       ; %bb.0:
348; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
349; GCN-NEXT:    v_sub_i32_e32 v16, vcc, 64, v8
350; GCN-NEXT:    v_lshl_b64 v[16:17], v[2:3], v16
351; GCN-NEXT:    v_lshr_b64 v[18:19], v[0:1], v8
352; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
353; GCN-NEXT:    v_cmp_gt_u64_e64 s[4:5], 64, v[8:9]
354; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
355; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
356; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
357; GCN-NEXT:    v_or_b32_e32 v19, v19, v17
358; GCN-NEXT:    v_or_b32_e32 v18, v18, v16
359; GCN-NEXT:    v_lshr_b64 v[16:17], v[2:3], v9
360; GCN-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
361; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
362; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[4:5]
363; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
364; GCN-NEXT:    v_sub_i32_e64 v9, s[6:7], 64, v12
365; GCN-NEXT:    v_cndmask_b32_e64 v11, v17, v19, s[4:5]
366; GCN-NEXT:    v_lshl_b64 v[9:10], v[6:7], v9
367; GCN-NEXT:    v_lshr_b64 v[16:17], v[4:5], v12
368; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
369; GCN-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc
370; GCN-NEXT:    v_or_b32_e32 v16, v16, v9
371; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[12:13]
372; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
373; GCN-NEXT:    v_or_b32_e32 v11, v17, v10
374; GCN-NEXT:    v_lshr_b64 v[9:10], v[6:7], v9
375; GCN-NEXT:    v_or_b32_e32 v15, v13, v15
376; GCN-NEXT:    v_or_b32_e32 v14, v12, v14
377; GCN-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
378; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
379; GCN-NEXT:    v_lshr_b64 v[2:3], v[2:3], v8
380; GCN-NEXT:    v_lshr_b64 v[6:7], v[6:7], v12
381; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
382; GCN-NEXT:    v_cndmask_b32_e64 v4, v9, v4, s[6:7]
383; GCN-NEXT:    v_cndmask_b32_e32 v9, v10, v11, vcc
384; GCN-NEXT:    v_cndmask_b32_e64 v5, v9, v5, s[6:7]
385; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[4:5]
386; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[4:5]
387; GCN-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
388; GCN-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
389; GCN-NEXT:    s_setpc_b64 s[30:31]
390  %shl = lshr <2 x i128> %lhs, %rhs
391  ret <2 x i128> %shl
392}
393
394define <2 x i128> @v_ashr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
395; GCN-LABEL: v_ashr_v2i128_vv:
396; GCN:       ; %bb.0:
397; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
398; GCN-NEXT:    v_sub_i32_e32 v16, vcc, 64, v8
399; GCN-NEXT:    v_lshl_b64 v[16:17], v[2:3], v16
400; GCN-NEXT:    v_lshr_b64 v[18:19], v[0:1], v8
401; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
402; GCN-NEXT:    v_cmp_gt_u64_e64 s[4:5], 64, v[8:9]
403; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
404; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
405; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
406; GCN-NEXT:    v_or_b32_e32 v19, v19, v17
407; GCN-NEXT:    v_or_b32_e32 v18, v18, v16
408; GCN-NEXT:    v_ashr_i64 v[16:17], v[2:3], v9
409; GCN-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
410; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
411; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[4:5]
412; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
413; GCN-NEXT:    v_sub_i32_e64 v9, s[6:7], 64, v12
414; GCN-NEXT:    v_cndmask_b32_e64 v11, v17, v19, s[4:5]
415; GCN-NEXT:    v_lshl_b64 v[9:10], v[6:7], v9
416; GCN-NEXT:    v_lshr_b64 v[16:17], v[4:5], v12
417; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
418; GCN-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc
419; GCN-NEXT:    v_or_b32_e32 v16, v16, v9
420; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[12:13]
421; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
422; GCN-NEXT:    v_or_b32_e32 v11, v17, v10
423; GCN-NEXT:    v_ashr_i64 v[9:10], v[6:7], v9
424; GCN-NEXT:    v_or_b32_e32 v15, v13, v15
425; GCN-NEXT:    v_or_b32_e32 v14, v12, v14
426; GCN-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
427; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
428; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
429; GCN-NEXT:    v_cndmask_b32_e64 v4, v9, v4, s[6:7]
430; GCN-NEXT:    v_cndmask_b32_e32 v9, v10, v11, vcc
431; GCN-NEXT:    v_cndmask_b32_e64 v5, v9, v5, s[6:7]
432; GCN-NEXT:    v_ashr_i64 v[8:9], v[2:3], v8
433; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
434; GCN-NEXT:    v_cndmask_b32_e64 v2, v3, v8, s[4:5]
435; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v9, s[4:5]
436; GCN-NEXT:    v_ashr_i64 v[8:9], v[6:7], v12
437; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v7
438; GCN-NEXT:    v_cndmask_b32_e32 v6, v7, v8, vcc
439; GCN-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
440; GCN-NEXT:    s_setpc_b64 s[30:31]
441  %shl = ashr <2 x i128> %lhs, %rhs
442  ret <2 x i128> %shl
443}
444
445define amdgpu_kernel void @s_shl_v2i128ss(<2 x i128> %lhs, <2 x i128> %rhs) {
446; GCN-LABEL: s_shl_v2i128ss:
447; GCN:       ; %bb.0:
448; GCN-NEXT:    s_load_dwordx8 s[16:23], s[4:5], 0x8
449; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
450; GCN-NEXT:    v_mov_b32_e32 v10, 16
451; GCN-NEXT:    v_mov_b32_e32 v8, 0
452; GCN-NEXT:    v_mov_b32_e32 v11, 0
453; GCN-NEXT:    s_waitcnt lgkmcnt(0)
454; GCN-NEXT:    s_sub_i32 s6, 64, s16
455; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[16:17], 64
456; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[18:19], 0
457; GCN-NEXT:    s_sub_i32 s4, s16, 64
458; GCN-NEXT:    s_lshr_b64 s[6:7], s[8:9], s6
459; GCN-NEXT:    s_lshl_b64 s[24:25], s[10:11], s16
460; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
461; GCN-NEXT:    s_or_b64 s[0:1], s[16:17], s[18:19]
462; GCN-NEXT:    s_lshl_b64 s[4:5], s[8:9], s4
463; GCN-NEXT:    s_or_b64 s[6:7], s[24:25], s[6:7]
464; GCN-NEXT:    v_mov_b32_e32 v0, s5
465; GCN-NEXT:    v_mov_b32_e32 v1, s7
466; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
467; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
468; GCN-NEXT:    v_mov_b32_e32 v1, s11
469; GCN-NEXT:    v_cndmask_b32_e64 v3, v0, v1, s[0:1]
470; GCN-NEXT:    v_mov_b32_e32 v0, s4
471; GCN-NEXT:    v_mov_b32_e32 v1, s6
472; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
473; GCN-NEXT:    v_mov_b32_e32 v1, s10
474; GCN-NEXT:    s_sub_i32 s6, 64, s20
475; GCN-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
476; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[20:21], 64
477; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[22:23], 0
478; GCN-NEXT:    s_sub_i32 s4, s20, 64
479; GCN-NEXT:    s_lshr_b64 s[6:7], s[12:13], s6
480; GCN-NEXT:    s_lshl_b64 s[10:11], s[14:15], s20
481; GCN-NEXT:    s_lshl_b64 s[4:5], s[12:13], s4
482; GCN-NEXT:    s_or_b64 s[6:7], s[10:11], s[6:7]
483; GCN-NEXT:    s_and_b64 s[0:1], s[2:3], s[0:1]
484; GCN-NEXT:    s_or_b64 s[2:3], s[20:21], s[22:23]
485; GCN-NEXT:    v_mov_b32_e32 v0, s5
486; GCN-NEXT:    v_mov_b32_e32 v1, s7
487; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[2:3], 0
488; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[0:1]
489; GCN-NEXT:    v_mov_b32_e32 v1, s15
490; GCN-NEXT:    v_cndmask_b32_e64 v7, v0, v1, s[2:3]
491; GCN-NEXT:    v_mov_b32_e32 v0, s4
492; GCN-NEXT:    v_mov_b32_e32 v1, s6
493; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[0:1]
494; GCN-NEXT:    v_mov_b32_e32 v1, s14
495; GCN-NEXT:    v_cndmask_b32_e64 v6, v0, v1, s[2:3]
496; GCN-NEXT:    s_lshl_b64 s[2:3], s[8:9], s16
497; GCN-NEXT:    v_mov_b32_e32 v0, s3
498; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
499; GCN-NEXT:    v_mov_b32_e32 v0, s2
500; GCN-NEXT:    s_lshl_b64 s[2:3], s[12:13], s20
501; GCN-NEXT:    v_mov_b32_e32 v4, s3
502; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, v4, s[0:1]
503; GCN-NEXT:    v_mov_b32_e32 v4, s2
504; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, v4, s[0:1]
505; GCN-NEXT:    v_mov_b32_e32 v9, 0
506; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
507; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
508; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
509; GCN-NEXT:    s_endpgm
510  %shift = shl <2 x i128> %lhs, %rhs
511  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
512  ret void
513}
514
515define amdgpu_kernel void @s_lshr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
516; GCN-LABEL: s_lshr_v2i128_ss:
517; GCN:       ; %bb.0:
518; GCN-NEXT:    s_load_dwordx8 s[16:23], s[4:5], 0x8
519; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
520; GCN-NEXT:    v_mov_b32_e32 v10, 16
521; GCN-NEXT:    v_mov_b32_e32 v8, 0
522; GCN-NEXT:    v_mov_b32_e32 v11, 0
523; GCN-NEXT:    s_waitcnt lgkmcnt(0)
524; GCN-NEXT:    s_sub_i32 s6, 64, s16
525; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[16:17], 64
526; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[18:19], 0
527; GCN-NEXT:    s_sub_i32 s4, s16, 64
528; GCN-NEXT:    s_lshl_b64 s[6:7], s[10:11], s6
529; GCN-NEXT:    s_lshr_b64 s[24:25], s[8:9], s16
530; GCN-NEXT:    s_or_b64 s[6:7], s[24:25], s[6:7]
531; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
532; GCN-NEXT:    s_or_b64 s[0:1], s[16:17], s[18:19]
533; GCN-NEXT:    s_lshr_b64 s[4:5], s[10:11], s4
534; GCN-NEXT:    v_mov_b32_e32 v0, s5
535; GCN-NEXT:    v_mov_b32_e32 v1, s7
536; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
537; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
538; GCN-NEXT:    v_mov_b32_e32 v1, s9
539; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
540; GCN-NEXT:    v_mov_b32_e32 v0, s4
541; GCN-NEXT:    v_mov_b32_e32 v2, s6
542; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
543; GCN-NEXT:    v_mov_b32_e32 v2, s8
544; GCN-NEXT:    s_sub_i32 s6, 64, s20
545; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
546; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[20:21], 64
547; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[22:23], 0
548; GCN-NEXT:    s_sub_i32 s4, s20, 64
549; GCN-NEXT:    s_lshl_b64 s[6:7], s[14:15], s6
550; GCN-NEXT:    s_lshr_b64 s[8:9], s[12:13], s20
551; GCN-NEXT:    s_lshr_b64 s[4:5], s[14:15], s4
552; GCN-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
553; GCN-NEXT:    s_and_b64 s[0:1], s[2:3], s[0:1]
554; GCN-NEXT:    s_or_b64 s[2:3], s[20:21], s[22:23]
555; GCN-NEXT:    v_mov_b32_e32 v2, s5
556; GCN-NEXT:    v_mov_b32_e32 v3, s7
557; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[2:3], 0
558; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
559; GCN-NEXT:    v_mov_b32_e32 v3, s13
560; GCN-NEXT:    v_cndmask_b32_e64 v5, v2, v3, s[2:3]
561; GCN-NEXT:    v_mov_b32_e32 v2, s4
562; GCN-NEXT:    v_mov_b32_e32 v3, s6
563; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
564; GCN-NEXT:    v_mov_b32_e32 v3, s12
565; GCN-NEXT:    v_cndmask_b32_e64 v4, v2, v3, s[2:3]
566; GCN-NEXT:    s_lshr_b64 s[2:3], s[10:11], s16
567; GCN-NEXT:    v_mov_b32_e32 v2, s3
568; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
569; GCN-NEXT:    v_mov_b32_e32 v2, s2
570; GCN-NEXT:    s_lshr_b64 s[2:3], s[14:15], s20
571; GCN-NEXT:    v_mov_b32_e32 v6, s3
572; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, v6, s[0:1]
573; GCN-NEXT:    v_mov_b32_e32 v6, s2
574; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, v6, s[0:1]
575; GCN-NEXT:    v_mov_b32_e32 v9, 0
576; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
577; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
578; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
579; GCN-NEXT:    s_endpgm
580  %shift = lshr <2 x i128> %lhs, %rhs
581  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
582  ret void
583}
584
585define amdgpu_kernel void @s_ashr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
586; GCN-LABEL: s_ashr_v2i128_ss:
587; GCN:       ; %bb.0:
588; GCN-NEXT:    s_load_dwordx8 s[16:23], s[4:5], 0x8
589; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
590; GCN-NEXT:    v_mov_b32_e32 v10, 16
591; GCN-NEXT:    v_mov_b32_e32 v8, 0
592; GCN-NEXT:    v_mov_b32_e32 v11, 0
593; GCN-NEXT:    s_waitcnt lgkmcnt(0)
594; GCN-NEXT:    s_sub_i32 s6, 64, s16
595; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[16:17], 64
596; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[18:19], 0
597; GCN-NEXT:    s_sub_i32 s4, s16, 64
598; GCN-NEXT:    s_lshl_b64 s[6:7], s[10:11], s6
599; GCN-NEXT:    s_lshr_b64 s[24:25], s[8:9], s16
600; GCN-NEXT:    s_or_b64 s[6:7], s[24:25], s[6:7]
601; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
602; GCN-NEXT:    s_or_b64 s[0:1], s[16:17], s[18:19]
603; GCN-NEXT:    s_ashr_i64 s[4:5], s[10:11], s4
604; GCN-NEXT:    v_mov_b32_e32 v0, s5
605; GCN-NEXT:    v_mov_b32_e32 v1, s7
606; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
607; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
608; GCN-NEXT:    v_mov_b32_e32 v1, s9
609; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
610; GCN-NEXT:    v_mov_b32_e32 v0, s4
611; GCN-NEXT:    v_mov_b32_e32 v2, s6
612; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
613; GCN-NEXT:    v_mov_b32_e32 v2, s8
614; GCN-NEXT:    s_sub_i32 s6, 64, s20
615; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
616; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[20:21], 64
617; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[22:23], 0
618; GCN-NEXT:    s_sub_i32 s4, s20, 64
619; GCN-NEXT:    s_lshl_b64 s[6:7], s[14:15], s6
620; GCN-NEXT:    s_lshr_b64 s[8:9], s[12:13], s20
621; GCN-NEXT:    s_ashr_i64 s[4:5], s[14:15], s4
622; GCN-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
623; GCN-NEXT:    s_and_b64 s[0:1], s[2:3], s[0:1]
624; GCN-NEXT:    s_or_b64 s[2:3], s[20:21], s[22:23]
625; GCN-NEXT:    v_mov_b32_e32 v2, s5
626; GCN-NEXT:    v_mov_b32_e32 v3, s7
627; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[2:3], 0
628; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
629; GCN-NEXT:    v_mov_b32_e32 v3, s13
630; GCN-NEXT:    v_cndmask_b32_e64 v5, v2, v3, s[2:3]
631; GCN-NEXT:    v_mov_b32_e32 v2, s4
632; GCN-NEXT:    v_mov_b32_e32 v3, s6
633; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
634; GCN-NEXT:    v_mov_b32_e32 v3, s12
635; GCN-NEXT:    v_cndmask_b32_e64 v4, v2, v3, s[2:3]
636; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], s16
637; GCN-NEXT:    s_ashr_i32 s4, s11, 31
638; GCN-NEXT:    v_mov_b32_e32 v2, s4
639; GCN-NEXT:    v_mov_b32_e32 v3, s3
640; GCN-NEXT:    v_mov_b32_e32 v6, s2
641; GCN-NEXT:    s_ashr_i64 s[2:3], s[14:15], s20
642; GCN-NEXT:    s_ashr_i32 s4, s15, 31
643; GCN-NEXT:    v_cndmask_b32_e32 v3, v2, v3, vcc
644; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
645; GCN-NEXT:    v_mov_b32_e32 v6, s4
646; GCN-NEXT:    v_mov_b32_e32 v7, s3
647; GCN-NEXT:    v_mov_b32_e32 v12, s2
648; GCN-NEXT:    v_cndmask_b32_e64 v7, v6, v7, s[0:1]
649; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[0:1]
650; GCN-NEXT:    v_mov_b32_e32 v9, 0
651; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
652; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
653; GCN-NEXT:    s_endpgm
654  %shift = ashr <2 x i128> %lhs, %rhs
655  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
656  ret void
657}
658
659