1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define i128 @v_shl_i128_vv(i128 %lhs, i128 %rhs) {
5; GCN-LABEL: v_shl_i128_vv:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
9; GCN-NEXT:    v_lshl_b64 v[5:6], v[2:3], v4
10; GCN-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
11; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], 0, v4
12; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
13; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
14; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
15; GCN-NEXT:    v_lshl_b64 v[5:6], v[0:1], v5
16; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
17; GCN-NEXT:    v_lshl_b64 v[0:1], v[0:1], v4
18; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
19; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
20; GCN-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[6:7]
21; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[6:7]
22; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
23; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
24; GCN-NEXT:    s_setpc_b64 s[30:31]
25  %shl = shl i128 %lhs, %rhs
26  ret i128 %shl
27}
28
29define i128 @v_lshr_i128_vv(i128 %lhs, i128 %rhs) {
30; GCN-LABEL: v_lshr_i128_vv:
31; GCN:       ; %bb.0:
32; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
34; GCN-NEXT:    v_lshr_b64 v[5:6], v[0:1], v4
35; GCN-NEXT:    v_lshl_b64 v[7:8], v[2:3], v7
36; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], 0, v4
37; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
38; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
39; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
40; GCN-NEXT:    v_lshr_b64 v[5:6], v[2:3], v5
41; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
42; GCN-NEXT:    v_lshr_b64 v[2:3], v[2:3], v4
43; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
44; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
45; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v1, s[6:7]
46; GCN-NEXT:    v_cndmask_b32_e64 v0, v5, v0, s[6:7]
47; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
48; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
49; GCN-NEXT:    s_setpc_b64 s[30:31]
50
51  %shl = lshr i128 %lhs, %rhs
52  ret i128 %shl
53}
54
55define i128 @v_ashr_i128_vv(i128 %lhs, i128 %rhs) {
56; GCN-LABEL: v_ashr_i128_vv:
57; GCN:       ; %bb.0:
58; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
59; GCN-NEXT:    v_sub_i32_e32 v9, vcc, 64, v4
60; GCN-NEXT:    v_lshr_b64 v[7:8], v[0:1], v4
61; GCN-NEXT:    v_lshl_b64 v[9:10], v[2:3], v9
62; GCN-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
63; GCN-NEXT:    v_or_b32_e32 v8, v8, v10
64; GCN-NEXT:    v_subrev_i32_e32 v10, vcc, 64, v4
65; GCN-NEXT:    v_ashr_i64 v[5:6], v[2:3], v4
66; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], v10
67; GCN-NEXT:    v_cmp_gt_u32_e64 s[6:7], 64, v4
68; GCN-NEXT:    v_or_b32_e32 v7, v7, v9
69; GCN-NEXT:    v_cndmask_b32_e64 v5, v11, v5, s[6:7]
70; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v8, s[6:7]
71; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
72; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v7, s[6:7]
73; GCN-NEXT:    v_cndmask_b32_e64 v6, v11, v6, s[6:7]
74; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
75; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
76; GCN-NEXT:    v_mov_b32_e32 v2, v5
77; GCN-NEXT:    v_mov_b32_e32 v3, v6
78; GCN-NEXT:    s_setpc_b64 s[30:31]
79  %shl = ashr i128 %lhs, %rhs
80  ret i128 %shl
81}
82
83
84define i128 @v_shl_i128_vk(i128 %lhs) {
85; GCN-LABEL: v_shl_i128_vk:
86; GCN:       ; %bb.0:
87; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
88; GCN-NEXT:    v_lshl_b64 v[2:3], v[2:3], 17
89; GCN-NEXT:    v_lshrrev_b32_e32 v4, 15, v1
90; GCN-NEXT:    v_lshl_b64 v[0:1], v[0:1], 17
91; GCN-NEXT:    v_or_b32_e32 v2, v2, v4
92; GCN-NEXT:    s_setpc_b64 s[30:31]
93  %shl = shl i128 %lhs, 17
94  ret i128 %shl
95}
96
97define i128 @v_lshr_i128_vk(i128 %lhs) {
98; GCN-LABEL: v_lshr_i128_vk:
99; GCN:       ; %bb.0:
100; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
101; GCN-NEXT:    v_lshr_b64 v[0:1], v[2:3], 1
102; GCN-NEXT:    v_mov_b32_e32 v2, 0
103; GCN-NEXT:    v_mov_b32_e32 v3, 0
104; GCN-NEXT:    s_setpc_b64 s[30:31]
105  %shl = lshr i128 %lhs, 65
106  ret i128 %shl
107}
108
109define i128 @v_ashr_i128_vk(i128 %lhs) {
110; GCN-LABEL: v_ashr_i128_vk:
111; GCN:       ; %bb.0:
112; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113; GCN-NEXT:    v_lshl_b64 v[4:5], v[2:3], 31
114; GCN-NEXT:    v_lshrrev_b32_e32 v0, 1, v1
115; GCN-NEXT:    v_or_b32_e32 v4, v0, v4
116; GCN-NEXT:    v_mov_b32_e32 v0, v4
117; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 33
118; GCN-NEXT:    v_mov_b32_e32 v1, v5
119; GCN-NEXT:    s_setpc_b64 s[30:31]
120  %shl = ashr i128 %lhs, 33
121  ret i128 %shl
122}
123
124define i128 @v_shl_i128_kv(i128 %rhs) {
125; GCN-LABEL: v_shl_i128_kv:
126; GCN:       ; %bb.0:
127; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
128; GCN-NEXT:    v_sub_i32_e32 v1, vcc, 64, v0
129; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, 64, v0
130; GCN-NEXT:    v_lshr_b64 v[1:2], 17, v1
131; GCN-NEXT:    v_lshl_b64 v[4:5], 17, v3
132; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
133; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
134; GCN-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v0
135; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, v2, s[6:7]
136; GCN-NEXT:    v_cndmask_b32_e32 v2, v4, v1, vcc
137; GCN-NEXT:    v_lshl_b64 v[0:1], 17, v0
138; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[6:7]
139; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
140; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
141; GCN-NEXT:    s_setpc_b64 s[30:31]
142  %shl = shl i128 17, %rhs
143  ret i128 %shl
144}
145
146define i128 @v_lshr_i128_kv(i128 %rhs) {
147; GCN-LABEL: v_lshr_i128_kv:
148; GCN:       ; %bb.0:
149; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
150; GCN-NEXT:    s_mov_b32 s7, 0
151; GCN-NEXT:    s_movk_i32 s6, 0x41
152; GCN-NEXT:    v_lshr_b64 v[2:3], s[6:7], v0
153; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
154; GCN-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v0
155; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
156; GCN-NEXT:    v_mov_b32_e32 v2, 0x41
157; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
158; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[6:7]
159; GCN-NEXT:    v_mov_b32_e32 v2, 0
160; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[6:7]
161; GCN-NEXT:    v_mov_b32_e32 v3, 0
162; GCN-NEXT:    s_setpc_b64 s[30:31]
163  %shl = lshr i128 65, %rhs
164  ret i128 %shl
165}
166
167define i128 @v_ashr_i128_kv(i128 %rhs) {
168; GCN-LABEL: v_ashr_i128_kv:
169; GCN:       ; %bb.0:
170; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
171; GCN-NEXT:    v_lshr_b64 v[2:3], 33, v0
172; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
173; GCN-NEXT:    v_cmp_ne_u32_e64 s[6:7], 0, v0
174; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
175; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
176; GCN-NEXT:    v_mov_b32_e32 v2, 0
177; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[6:7]
178; GCN-NEXT:    v_cndmask_b32_e64 v0, 33, v0, s[6:7]
179; GCN-NEXT:    v_mov_b32_e32 v3, 0
180; GCN-NEXT:    s_setpc_b64 s[30:31]
181  %shl = ashr i128 33, %rhs
182  ret i128 %shl
183}
184
185define amdgpu_kernel void @s_shl_i128_ss(i128 %lhs, i128 %rhs) {
186; GCN-LABEL: s_shl_i128_ss:
187; GCN:       ; %bb.0:
188; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
189; GCN-NEXT:    v_mov_b32_e32 v4, 0
190; GCN-NEXT:    v_mov_b32_e32 v5, 0
191; GCN-NEXT:    s_waitcnt lgkmcnt(0)
192; GCN-NEXT:    s_sub_i32 s2, 64, s8
193; GCN-NEXT:    s_sub_i32 s9, s8, 64
194; GCN-NEXT:    s_lshl_b64 s[0:1], s[6:7], s8
195; GCN-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2
196; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
197; GCN-NEXT:    s_lshl_b64 s[10:11], s[4:5], s9
198; GCN-NEXT:    v_mov_b32_e32 v0, s11
199; GCN-NEXT:    v_mov_b32_e32 v1, s3
200; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
201; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
202; GCN-NEXT:    v_mov_b32_e32 v1, s7
203; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
204; GCN-NEXT:    v_cndmask_b32_e64 v3, v0, v1, s[0:1]
205; GCN-NEXT:    v_mov_b32_e32 v0, s10
206; GCN-NEXT:    v_mov_b32_e32 v1, s2
207; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
208; GCN-NEXT:    v_mov_b32_e32 v1, s6
209; GCN-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
210; GCN-NEXT:    s_lshl_b64 s[0:1], s[4:5], s8
211; GCN-NEXT:    v_mov_b32_e32 v0, s1
212; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
213; GCN-NEXT:    v_mov_b32_e32 v0, s0
214; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
215; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
216; GCN-NEXT:    s_endpgm
217; GCN-NEXT:    .section .rodata,#alloc
218; GCN-NEXT:    .p2align 6
219; GCN-NEXT:    .amdhsa_kernel s_shl_i128_ss
220; GCN-NEXT:     .amdhsa_group_segment_fixed_size 0
221; GCN-NEXT:     .amdhsa_private_segment_fixed_size 0
222; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
223; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
224; GCN-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
225; GCN-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 1
226; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
227; GCN-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 0
228; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
229; GCN-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 0
230; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
231; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
232; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
233; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
234; GCN-NEXT:     .amdhsa_system_vgpr_workitem_id 0
235; GCN-NEXT:     .amdhsa_next_free_vgpr 8
236; GCN-NEXT:     .amdhsa_next_free_sgpr 12
237; GCN-NEXT:     .amdhsa_reserve_flat_scratch 0
238; GCN-NEXT:     .amdhsa_float_round_mode_32 0
239; GCN-NEXT:     .amdhsa_float_round_mode_16_64 0
240; GCN-NEXT:     .amdhsa_float_denorm_mode_32 0
241; GCN-NEXT:     .amdhsa_float_denorm_mode_16_64 3
242; GCN-NEXT:     .amdhsa_dx10_clamp 1
243; GCN-NEXT:     .amdhsa_ieee_mode 1
244; GCN-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
245; GCN-NEXT:     .amdhsa_exception_fp_denorm_src 0
246; GCN-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
247; GCN-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
248; GCN-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
249; GCN-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
250; GCN-NEXT:     .amdhsa_exception_int_div_zero 0
251; GCN-NEXT:    .end_amdhsa_kernel
252; GCN-NEXT:    .text
253  %shift = shl i128 %lhs, %rhs
254  store i128 %shift, i128 addrspace(1)* null
255  ret void
256}
257
258define amdgpu_kernel void @s_lshr_i128_ss(i128 %lhs, i128 %rhs) {
259; GCN-LABEL: s_lshr_i128_ss:
260; GCN:       ; %bb.0:
261; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
262; GCN-NEXT:    v_mov_b32_e32 v4, 0
263; GCN-NEXT:    v_mov_b32_e32 v5, 0
264; GCN-NEXT:    s_waitcnt lgkmcnt(0)
265; GCN-NEXT:    s_sub_i32 s2, 64, s8
266; GCN-NEXT:    s_sub_i32 s9, s8, 64
267; GCN-NEXT:    s_lshr_b64 s[0:1], s[4:5], s8
268; GCN-NEXT:    s_lshl_b64 s[2:3], s[6:7], s2
269; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
270; GCN-NEXT:    s_lshr_b64 s[10:11], s[6:7], s9
271; GCN-NEXT:    v_mov_b32_e32 v0, s11
272; GCN-NEXT:    v_mov_b32_e32 v1, s3
273; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
274; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
275; GCN-NEXT:    v_mov_b32_e32 v1, s5
276; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
277; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
278; GCN-NEXT:    v_mov_b32_e32 v0, s10
279; GCN-NEXT:    v_mov_b32_e32 v2, s2
280; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
281; GCN-NEXT:    v_mov_b32_e32 v2, s4
282; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
283; GCN-NEXT:    s_lshr_b64 s[0:1], s[6:7], s8
284; GCN-NEXT:    v_mov_b32_e32 v2, s1
285; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
286; GCN-NEXT:    v_mov_b32_e32 v2, s0
287; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
288; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
289; GCN-NEXT:    s_endpgm
290; GCN-NEXT:    .section .rodata,#alloc
291; GCN-NEXT:    .p2align 6
292; GCN-NEXT:    .amdhsa_kernel s_lshr_i128_ss
293; GCN-NEXT:     .amdhsa_group_segment_fixed_size 0
294; GCN-NEXT:     .amdhsa_private_segment_fixed_size 0
295; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
296; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
297; GCN-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
298; GCN-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 1
299; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
300; GCN-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 0
301; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
302; GCN-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 0
303; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
304; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
305; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
306; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
307; GCN-NEXT:     .amdhsa_system_vgpr_workitem_id 0
308; GCN-NEXT:     .amdhsa_next_free_vgpr 8
309; GCN-NEXT:     .amdhsa_next_free_sgpr 12
310; GCN-NEXT:     .amdhsa_reserve_flat_scratch 0
311; GCN-NEXT:     .amdhsa_float_round_mode_32 0
312; GCN-NEXT:     .amdhsa_float_round_mode_16_64 0
313; GCN-NEXT:     .amdhsa_float_denorm_mode_32 0
314; GCN-NEXT:     .amdhsa_float_denorm_mode_16_64 3
315; GCN-NEXT:     .amdhsa_dx10_clamp 1
316; GCN-NEXT:     .amdhsa_ieee_mode 1
317; GCN-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
318; GCN-NEXT:     .amdhsa_exception_fp_denorm_src 0
319; GCN-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
320; GCN-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
321; GCN-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
322; GCN-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
323; GCN-NEXT:     .amdhsa_exception_int_div_zero 0
324; GCN-NEXT:    .end_amdhsa_kernel
325; GCN-NEXT:    .text
326  %shift = lshr i128 %lhs, %rhs
327  store i128 %shift, i128 addrspace(1)* null
328  ret void
329}
330
331define amdgpu_kernel void @s_ashr_i128_ss(i128 %lhs, i128 %rhs) {
332; GCN-LABEL: s_ashr_i128_ss:
333; GCN:       ; %bb.0:
334; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
335; GCN-NEXT:    s_waitcnt lgkmcnt(0)
336; GCN-NEXT:    s_sub_i32 s2, 64, s8
337; GCN-NEXT:    s_sub_i32 s9, s8, 64
338; GCN-NEXT:    s_lshr_b64 s[0:1], s[4:5], s8
339; GCN-NEXT:    s_lshl_b64 s[2:3], s[6:7], s2
340; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
341; GCN-NEXT:    s_ashr_i64 s[10:11], s[6:7], s9
342; GCN-NEXT:    v_mov_b32_e32 v0, s11
343; GCN-NEXT:    v_mov_b32_e32 v1, s3
344; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
345; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
346; GCN-NEXT:    v_mov_b32_e32 v1, s5
347; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
348; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
349; GCN-NEXT:    v_mov_b32_e32 v2, s2
350; GCN-NEXT:    v_mov_b32_e32 v0, s10
351; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
352; GCN-NEXT:    v_mov_b32_e32 v2, s4
353; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
354; GCN-NEXT:    s_ashr_i64 s[0:1], s[6:7], s8
355; GCN-NEXT:    s_ashr_i32 s2, s7, 31
356; GCN-NEXT:    v_mov_b32_e32 v2, s2
357; GCN-NEXT:    v_mov_b32_e32 v3, s1
358; GCN-NEXT:    v_mov_b32_e32 v4, s0
359; GCN-NEXT:    v_cndmask_b32_e32 v3, v2, v3, vcc
360; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
361; GCN-NEXT:    v_mov_b32_e32 v4, 0
362; GCN-NEXT:    v_mov_b32_e32 v5, 0
363; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
364; GCN-NEXT:    s_endpgm
365; GCN-NEXT:    .section .rodata,#alloc
366; GCN-NEXT:    .p2align 6
367; GCN-NEXT:    .amdhsa_kernel s_ashr_i128_ss
368; GCN-NEXT:     .amdhsa_group_segment_fixed_size 0
369; GCN-NEXT:     .amdhsa_private_segment_fixed_size 0
370; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
371; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
372; GCN-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
373; GCN-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 1
374; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
375; GCN-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 0
376; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
377; GCN-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 0
378; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
379; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
380; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
381; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
382; GCN-NEXT:     .amdhsa_system_vgpr_workitem_id 0
383; GCN-NEXT:     .amdhsa_next_free_vgpr 8
384; GCN-NEXT:     .amdhsa_next_free_sgpr 12
385; GCN-NEXT:     .amdhsa_reserve_flat_scratch 0
386; GCN-NEXT:     .amdhsa_float_round_mode_32 0
387; GCN-NEXT:     .amdhsa_float_round_mode_16_64 0
388; GCN-NEXT:     .amdhsa_float_denorm_mode_32 0
389; GCN-NEXT:     .amdhsa_float_denorm_mode_16_64 3
390; GCN-NEXT:     .amdhsa_dx10_clamp 1
391; GCN-NEXT:     .amdhsa_ieee_mode 1
392; GCN-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
393; GCN-NEXT:     .amdhsa_exception_fp_denorm_src 0
394; GCN-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
395; GCN-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
396; GCN-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
397; GCN-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
398; GCN-NEXT:     .amdhsa_exception_int_div_zero 0
399; GCN-NEXT:    .end_amdhsa_kernel
400; GCN-NEXT:    .text
401  %shift = ashr i128 %lhs, %rhs
402  store i128 %shift, i128 addrspace(1)* null
403  ret void
404}
405
406define <2 x i128> @v_shl_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
407; GCN-LABEL: v_shl_v2i128_vv:
408; GCN:       ; %bb.0:
409; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
410; GCN-NEXT:    v_sub_i32_e32 v18, vcc, 64, v8
411; GCN-NEXT:    v_lshl_b64 v[16:17], v[2:3], v8
412; GCN-NEXT:    v_lshr_b64 v[18:19], v[0:1], v18
413; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[10:11]
414; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[8:9]
415; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
416; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
417; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
418; GCN-NEXT:    v_or_b32_e32 v19, v17, v19
419; GCN-NEXT:    v_or_b32_e32 v18, v16, v18
420; GCN-NEXT:    v_lshl_b64 v[16:17], v[0:1], v9
421; GCN-NEXT:    s_and_b64 s[6:7], s[8:9], s[6:7]
422; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
423; GCN-NEXT:    v_cndmask_b32_e64 v9, v17, v19, s[6:7]
424; GCN-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
425; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[6:7]
426; GCN-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
427; GCN-NEXT:    v_sub_i32_e32 v11, vcc, 64, v12
428; GCN-NEXT:    v_lshl_b64 v[9:10], v[6:7], v12
429; GCN-NEXT:    v_lshr_b64 v[16:17], v[4:5], v11
430; GCN-NEXT:    v_cmp_gt_u64_e64 s[8:9], 64, v[12:13]
431; GCN-NEXT:    v_or_b32_e32 v16, v9, v16
432; GCN-NEXT:    v_cmp_eq_u64_e64 s[10:11], 0, v[14:15]
433; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
434; GCN-NEXT:    v_or_b32_e32 v11, v10, v17
435; GCN-NEXT:    v_lshl_b64 v[9:10], v[4:5], v9
436; GCN-NEXT:    s_and_b64 vcc, s[10:11], s[8:9]
437; GCN-NEXT:    v_cndmask_b32_e32 v17, v10, v11, vcc
438; GCN-NEXT:    v_or_b32_e32 v11, v13, v15
439; GCN-NEXT:    v_or_b32_e32 v10, v12, v14
440; GCN-NEXT:    v_lshl_b64 v[0:1], v[0:1], v8
441; GCN-NEXT:    v_lshl_b64 v[4:5], v[4:5], v12
442; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[10:11]
443; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
444; GCN-NEXT:    v_cndmask_b32_e64 v7, v17, v7, s[8:9]
445; GCN-NEXT:    v_cndmask_b32_e64 v6, v9, v6, s[8:9]
446; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[6:7]
447; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v0, s[6:7]
448; GCN-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
449; GCN-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
450; GCN-NEXT:    s_setpc_b64 s[30:31]
451  %shl = shl <2 x i128> %lhs, %rhs
452  ret <2 x i128> %shl
453}
454
455define <2 x i128> @v_lshr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
456; GCN-LABEL: v_lshr_v2i128_vv:
457; GCN:       ; %bb.0:
458; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
459; GCN-NEXT:    v_sub_i32_e32 v18, vcc, 64, v8
460; GCN-NEXT:    v_lshr_b64 v[16:17], v[0:1], v8
461; GCN-NEXT:    v_lshl_b64 v[18:19], v[2:3], v18
462; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[10:11]
463; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[8:9]
464; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
465; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
466; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
467; GCN-NEXT:    v_or_b32_e32 v19, v17, v19
468; GCN-NEXT:    v_or_b32_e32 v18, v16, v18
469; GCN-NEXT:    v_lshr_b64 v[16:17], v[2:3], v9
470; GCN-NEXT:    s_and_b64 s[6:7], s[8:9], s[6:7]
471; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
472; GCN-NEXT:    v_cndmask_b32_e64 v9, v17, v19, s[6:7]
473; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
474; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[6:7]
475; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
476; GCN-NEXT:    v_sub_i32_e32 v11, vcc, 64, v12
477; GCN-NEXT:    v_lshr_b64 v[9:10], v[4:5], v12
478; GCN-NEXT:    v_lshl_b64 v[16:17], v[6:7], v11
479; GCN-NEXT:    v_cmp_gt_u64_e64 s[8:9], 64, v[12:13]
480; GCN-NEXT:    v_or_b32_e32 v16, v9, v16
481; GCN-NEXT:    v_cmp_eq_u64_e64 s[10:11], 0, v[14:15]
482; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
483; GCN-NEXT:    v_or_b32_e32 v11, v10, v17
484; GCN-NEXT:    v_lshr_b64 v[9:10], v[6:7], v9
485; GCN-NEXT:    s_and_b64 vcc, s[10:11], s[8:9]
486; GCN-NEXT:    v_cndmask_b32_e32 v17, v10, v11, vcc
487; GCN-NEXT:    v_or_b32_e32 v11, v13, v15
488; GCN-NEXT:    v_or_b32_e32 v10, v12, v14
489; GCN-NEXT:    v_lshr_b64 v[2:3], v[2:3], v8
490; GCN-NEXT:    v_lshr_b64 v[6:7], v[6:7], v12
491; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[10:11]
492; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
493; GCN-NEXT:    v_cndmask_b32_e64 v5, v17, v5, s[8:9]
494; GCN-NEXT:    v_cndmask_b32_e64 v4, v9, v4, s[8:9]
495; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[6:7]
496; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[6:7]
497; GCN-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
498; GCN-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
499; GCN-NEXT:    s_setpc_b64 s[30:31]
500  %shl = lshr <2 x i128> %lhs, %rhs
501  ret <2 x i128> %shl
502}
503
504define <2 x i128> @v_ashr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
505; GCN-LABEL: v_ashr_v2i128_vv:
506; GCN:       ; %bb.0:
507; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
508; GCN-NEXT:    v_sub_i32_e32 v18, vcc, 64, v8
509; GCN-NEXT:    v_lshr_b64 v[16:17], v[0:1], v8
510; GCN-NEXT:    v_lshl_b64 v[18:19], v[2:3], v18
511; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[10:11]
512; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[8:9]
513; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
514; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
515; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
516; GCN-NEXT:    v_or_b32_e32 v19, v17, v19
517; GCN-NEXT:    v_or_b32_e32 v18, v16, v18
518; GCN-NEXT:    v_ashr_i64 v[16:17], v[2:3], v9
519; GCN-NEXT:    s_and_b64 s[6:7], s[8:9], s[6:7]
520; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
521; GCN-NEXT:    v_cndmask_b32_e64 v9, v17, v19, s[6:7]
522; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
523; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[6:7]
524; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
525; GCN-NEXT:    v_sub_i32_e32 v11, vcc, 64, v12
526; GCN-NEXT:    v_lshr_b64 v[9:10], v[4:5], v12
527; GCN-NEXT:    v_lshl_b64 v[16:17], v[6:7], v11
528; GCN-NEXT:    v_cmp_gt_u64_e64 s[8:9], 64, v[12:13]
529; GCN-NEXT:    v_or_b32_e32 v16, v9, v16
530; GCN-NEXT:    v_cmp_eq_u64_e64 s[10:11], 0, v[14:15]
531; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
532; GCN-NEXT:    v_or_b32_e32 v11, v10, v17
533; GCN-NEXT:    v_ashr_i64 v[9:10], v[6:7], v9
534; GCN-NEXT:    s_and_b64 vcc, s[10:11], s[8:9]
535; GCN-NEXT:    v_cndmask_b32_e32 v17, v10, v11, vcc
536; GCN-NEXT:    v_or_b32_e32 v11, v13, v15
537; GCN-NEXT:    v_or_b32_e32 v10, v12, v14
538; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[10:11]
539; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
540; GCN-NEXT:    v_cndmask_b32_e64 v4, v9, v4, s[8:9]
541; GCN-NEXT:    v_ashr_i64 v[8:9], v[2:3], v8
542; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v3
543; GCN-NEXT:    v_cndmask_b32_e64 v3, v2, v9, s[6:7]
544; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v8, s[6:7]
545; GCN-NEXT:    v_ashr_i64 v[8:9], v[6:7], v12
546; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v7
547; GCN-NEXT:    v_cndmask_b32_e32 v7, v6, v9, vcc
548; GCN-NEXT:    v_cndmask_b32_e64 v5, v17, v5, s[8:9]
549; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
550; GCN-NEXT:    s_setpc_b64 s[30:31]
551  %shl = ashr <2 x i128> %lhs, %rhs
552  ret <2 x i128> %shl
553}
554
555define amdgpu_kernel void @s_shl_v2i128ss(<2 x i128> %lhs, <2 x i128> %rhs) {
556; GCN-LABEL: s_shl_v2i128ss:
557; GCN:       ; %bb.0:
558; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
559; GCN-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x8
560; GCN-NEXT:    v_mov_b32_e32 v8, 0
561; GCN-NEXT:    v_mov_b32_e32 v9, 0
562; GCN-NEXT:    s_waitcnt lgkmcnt(0)
563; GCN-NEXT:    v_cmp_lt_u64_e64 s[16:17], s[0:1], 64
564; GCN-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[2:3], 0
565; GCN-NEXT:    s_lshl_b64 s[20:21], s[8:9], s0
566; GCN-NEXT:    s_and_b64 vcc, s[18:19], s[16:17]
567; GCN-NEXT:    s_sub_i32 s18, 64, s0
568; GCN-NEXT:    s_lshl_b64 s[16:17], s[10:11], s0
569; GCN-NEXT:    s_lshr_b64 s[18:19], s[8:9], s18
570; GCN-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
571; GCN-NEXT:    s_sub_i32 s18, s0, 64
572; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
573; GCN-NEXT:    s_lshl_b64 s[8:9], s[8:9], s18
574; GCN-NEXT:    v_mov_b32_e32 v2, s9
575; GCN-NEXT:    v_mov_b32_e32 v3, s17
576; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
577; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
578; GCN-NEXT:    v_mov_b32_e32 v3, s11
579; GCN-NEXT:    v_cndmask_b32_e64 v3, v2, v3, s[0:1]
580; GCN-NEXT:    v_mov_b32_e32 v2, s8
581; GCN-NEXT:    v_mov_b32_e32 v4, s16
582; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
583; GCN-NEXT:    v_mov_b32_e32 v4, s10
584; GCN-NEXT:    v_mov_b32_e32 v0, s21
585; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
586; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[4:5], 64
587; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
588; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
589; GCN-NEXT:    v_mov_b32_e32 v0, s20
590; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
591; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
592; GCN-NEXT:    s_sub_i32 s2, 64, s4
593; GCN-NEXT:    s_lshl_b64 s[8:9], s[12:13], s4
594; GCN-NEXT:    s_lshl_b64 s[0:1], s[14:15], s4
595; GCN-NEXT:    s_lshr_b64 s[2:3], s[12:13], s2
596; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
597; GCN-NEXT:    v_mov_b32_e32 v4, s9
598; GCN-NEXT:    s_sub_i32 s0, s4, 64
599; GCN-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
600; GCN-NEXT:    v_mov_b32_e32 v4, s8
601; GCN-NEXT:    s_lshl_b64 s[8:9], s[12:13], s0
602; GCN-NEXT:    s_or_b64 s[0:1], s[4:5], s[6:7]
603; GCN-NEXT:    v_mov_b32_e32 v6, s9
604; GCN-NEXT:    v_mov_b32_e32 v7, s3
605; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
606; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
607; GCN-NEXT:    v_mov_b32_e32 v7, s15
608; GCN-NEXT:    v_cndmask_b32_e64 v7, v6, v7, s[0:1]
609; GCN-NEXT:    v_mov_b32_e32 v6, s8
610; GCN-NEXT:    v_mov_b32_e32 v10, s2
611; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v10, vcc
612; GCN-NEXT:    v_mov_b32_e32 v10, s14
613; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s[0:1]
614; GCN-NEXT:    v_mov_b32_e32 v10, 16
615; GCN-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
616; GCN-NEXT:    v_mov_b32_e32 v11, 0
617; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
618; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
619; GCN-NEXT:    s_endpgm
620; GCN-NEXT:    .section .rodata,#alloc
621; GCN-NEXT:    .p2align 6
622; GCN-NEXT:    .amdhsa_kernel s_shl_v2i128ss
623; GCN-NEXT:     .amdhsa_group_segment_fixed_size 0
624; GCN-NEXT:     .amdhsa_private_segment_fixed_size 0
625; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
626; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
627; GCN-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
628; GCN-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 1
629; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
630; GCN-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 0
631; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
632; GCN-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 0
633; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
634; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
635; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
636; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
637; GCN-NEXT:     .amdhsa_system_vgpr_workitem_id 0
638; GCN-NEXT:     .amdhsa_next_free_vgpr 16
639; GCN-NEXT:     .amdhsa_next_free_sgpr 22
640; GCN-NEXT:     .amdhsa_reserve_flat_scratch 0
641; GCN-NEXT:     .amdhsa_float_round_mode_32 0
642; GCN-NEXT:     .amdhsa_float_round_mode_16_64 0
643; GCN-NEXT:     .amdhsa_float_denorm_mode_32 0
644; GCN-NEXT:     .amdhsa_float_denorm_mode_16_64 3
645; GCN-NEXT:     .amdhsa_dx10_clamp 1
646; GCN-NEXT:     .amdhsa_ieee_mode 1
647; GCN-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
648; GCN-NEXT:     .amdhsa_exception_fp_denorm_src 0
649; GCN-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
650; GCN-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
651; GCN-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
652; GCN-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
653; GCN-NEXT:     .amdhsa_exception_int_div_zero 0
654; GCN-NEXT:    .end_amdhsa_kernel
655; GCN-NEXT:    .text
656  %shift = shl <2 x i128> %lhs, %rhs
657  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
658  ret void
659}
660
661define amdgpu_kernel void @s_lshr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
662; GCN-LABEL: s_lshr_v2i128_ss:
663; GCN:       ; %bb.0:
664; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
665; GCN-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x8
666; GCN-NEXT:    v_mov_b32_e32 v8, 0
667; GCN-NEXT:    v_mov_b32_e32 v9, 0
668; GCN-NEXT:    s_waitcnt lgkmcnt(0)
669; GCN-NEXT:    v_cmp_lt_u64_e64 s[16:17], s[0:1], 64
670; GCN-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[2:3], 0
671; GCN-NEXT:    s_lshr_b64 s[20:21], s[10:11], s0
672; GCN-NEXT:    s_and_b64 vcc, s[18:19], s[16:17]
673; GCN-NEXT:    s_sub_i32 s18, 64, s0
674; GCN-NEXT:    s_lshr_b64 s[16:17], s[8:9], s0
675; GCN-NEXT:    s_lshl_b64 s[18:19], s[10:11], s18
676; GCN-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
677; GCN-NEXT:    s_sub_i32 s18, s0, 64
678; GCN-NEXT:    v_mov_b32_e32 v0, s21
679; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
680; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v0, vcc
681; GCN-NEXT:    v_mov_b32_e32 v0, s20
682; GCN-NEXT:    s_lshr_b64 s[10:11], s[10:11], s18
683; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v0, vcc
684; GCN-NEXT:    v_mov_b32_e32 v0, s11
685; GCN-NEXT:    v_mov_b32_e32 v1, s17
686; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
687; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
688; GCN-NEXT:    v_mov_b32_e32 v1, s9
689; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
690; GCN-NEXT:    v_mov_b32_e32 v0, s10
691; GCN-NEXT:    v_mov_b32_e32 v4, s16
692; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
693; GCN-NEXT:    v_mov_b32_e32 v4, s8
694; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
695; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[4:5], 64
696; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
697; GCN-NEXT:    s_lshr_b64 s[8:9], s[14:15], s4
698; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
699; GCN-NEXT:    s_sub_i32 s2, 64, s4
700; GCN-NEXT:    s_lshr_b64 s[0:1], s[12:13], s4
701; GCN-NEXT:    s_lshl_b64 s[2:3], s[14:15], s2
702; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
703; GCN-NEXT:    v_mov_b32_e32 v4, s9
704; GCN-NEXT:    s_sub_i32 s0, s4, 64
705; GCN-NEXT:    v_cndmask_b32_e32 v7, 0, v4, vcc
706; GCN-NEXT:    v_mov_b32_e32 v4, s8
707; GCN-NEXT:    s_lshr_b64 s[8:9], s[14:15], s0
708; GCN-NEXT:    s_or_b64 s[0:1], s[4:5], s[6:7]
709; GCN-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
710; GCN-NEXT:    v_mov_b32_e32 v4, s9
711; GCN-NEXT:    v_mov_b32_e32 v5, s3
712; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
713; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
714; GCN-NEXT:    v_mov_b32_e32 v5, s13
715; GCN-NEXT:    v_cndmask_b32_e64 v5, v4, v5, s[0:1]
716; GCN-NEXT:    v_mov_b32_e32 v4, s8
717; GCN-NEXT:    v_mov_b32_e32 v10, s2
718; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
719; GCN-NEXT:    v_mov_b32_e32 v10, s12
720; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v10, s[0:1]
721; GCN-NEXT:    v_mov_b32_e32 v10, 16
722; GCN-NEXT:    v_mov_b32_e32 v11, 0
723; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
724; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
725; GCN-NEXT:    s_endpgm
726; GCN-NEXT:    .section .rodata,#alloc
727; GCN-NEXT:    .p2align 6
728; GCN-NEXT:    .amdhsa_kernel s_lshr_v2i128_ss
729; GCN-NEXT:     .amdhsa_group_segment_fixed_size 0
730; GCN-NEXT:     .amdhsa_private_segment_fixed_size 0
731; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
732; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
733; GCN-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
734; GCN-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 1
735; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
736; GCN-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 0
737; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
738; GCN-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 0
739; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
740; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
741; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
742; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
743; GCN-NEXT:     .amdhsa_system_vgpr_workitem_id 0
744; GCN-NEXT:     .amdhsa_next_free_vgpr 16
745; GCN-NEXT:     .amdhsa_next_free_sgpr 22
746; GCN-NEXT:     .amdhsa_reserve_flat_scratch 0
747; GCN-NEXT:     .amdhsa_float_round_mode_32 0
748; GCN-NEXT:     .amdhsa_float_round_mode_16_64 0
749; GCN-NEXT:     .amdhsa_float_denorm_mode_32 0
750; GCN-NEXT:     .amdhsa_float_denorm_mode_16_64 3
751; GCN-NEXT:     .amdhsa_dx10_clamp 1
752; GCN-NEXT:     .amdhsa_ieee_mode 1
753; GCN-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
754; GCN-NEXT:     .amdhsa_exception_fp_denorm_src 0
755; GCN-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
756; GCN-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
757; GCN-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
758; GCN-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
759; GCN-NEXT:     .amdhsa_exception_int_div_zero 0
760; GCN-NEXT:    .end_amdhsa_kernel
761; GCN-NEXT:    .text
762  %shift = lshr <2 x i128> %lhs, %rhs
763  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
764  ret void
765}
766
767define amdgpu_kernel void @s_ashr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
768; GCN-LABEL: s_ashr_v2i128_ss:
769; GCN:       ; %bb.0:
770; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
771; GCN-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x8
772; GCN-NEXT:    v_mov_b32_e32 v8, 0
773; GCN-NEXT:    v_mov_b32_e32 v9, 0
774; GCN-NEXT:    s_waitcnt lgkmcnt(0)
775; GCN-NEXT:    s_ashr_i32 s22, s11, 31
776; GCN-NEXT:    v_cmp_lt_u64_e64 s[16:17], s[0:1], 64
777; GCN-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[2:3], 0
778; GCN-NEXT:    s_ashr_i64 s[20:21], s[10:11], s0
779; GCN-NEXT:    s_and_b64 vcc, s[18:19], s[16:17]
780; GCN-NEXT:    s_sub_i32 s18, 64, s0
781; GCN-NEXT:    s_lshr_b64 s[16:17], s[8:9], s0
782; GCN-NEXT:    s_lshl_b64 s[18:19], s[10:11], s18
783; GCN-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
784; GCN-NEXT:    s_sub_i32 s18, s0, 64
785; GCN-NEXT:    v_mov_b32_e32 v0, s22
786; GCN-NEXT:    v_mov_b32_e32 v1, s21
787; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
788; GCN-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
789; GCN-NEXT:    v_mov_b32_e32 v1, s20
790; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], s18
791; GCN-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
792; GCN-NEXT:    v_mov_b32_e32 v0, s11
793; GCN-NEXT:    v_mov_b32_e32 v1, s17
794; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
795; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
796; GCN-NEXT:    v_mov_b32_e32 v1, s9
797; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
798; GCN-NEXT:    v_mov_b32_e32 v0, s10
799; GCN-NEXT:    v_mov_b32_e32 v4, s16
800; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
801; GCN-NEXT:    v_mov_b32_e32 v4, s8
802; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
803; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[4:5], 64
804; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
805; GCN-NEXT:    s_ashr_i64 s[8:9], s[14:15], s4
806; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
807; GCN-NEXT:    s_sub_i32 s2, 64, s4
808; GCN-NEXT:    s_ashr_i32 s10, s15, 31
809; GCN-NEXT:    s_lshr_b64 s[0:1], s[12:13], s4
810; GCN-NEXT:    s_lshl_b64 s[2:3], s[14:15], s2
811; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
812; GCN-NEXT:    v_mov_b32_e32 v4, s10
813; GCN-NEXT:    v_mov_b32_e32 v5, s9
814; GCN-NEXT:    s_sub_i32 s0, s4, 64
815; GCN-NEXT:    v_cndmask_b32_e32 v7, v4, v5, vcc
816; GCN-NEXT:    v_mov_b32_e32 v5, s8
817; GCN-NEXT:    s_ashr_i64 s[8:9], s[14:15], s0
818; GCN-NEXT:    s_or_b64 s[0:1], s[4:5], s[6:7]
819; GCN-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc
820; GCN-NEXT:    v_mov_b32_e32 v4, s9
821; GCN-NEXT:    v_mov_b32_e32 v5, s3
822; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
823; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
824; GCN-NEXT:    v_mov_b32_e32 v5, s13
825; GCN-NEXT:    v_cndmask_b32_e64 v5, v4, v5, s[0:1]
826; GCN-NEXT:    v_mov_b32_e32 v4, s8
827; GCN-NEXT:    v_mov_b32_e32 v10, s2
828; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
829; GCN-NEXT:    v_mov_b32_e32 v10, s12
830; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v10, s[0:1]
831; GCN-NEXT:    v_mov_b32_e32 v10, 16
832; GCN-NEXT:    v_mov_b32_e32 v11, 0
833; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
834; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
835; GCN-NEXT:    s_endpgm
836; GCN-NEXT:    .section .rodata,#alloc
837; GCN-NEXT:    .p2align 6
838; GCN-NEXT:    .amdhsa_kernel s_ashr_v2i128_ss
839; GCN-NEXT:     .amdhsa_group_segment_fixed_size 0
840; GCN-NEXT:     .amdhsa_private_segment_fixed_size 0
841; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
842; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
843; GCN-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
844; GCN-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 1
845; GCN-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
846; GCN-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 0
847; GCN-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
848; GCN-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 0
849; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
850; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
851; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
852; GCN-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
853; GCN-NEXT:     .amdhsa_system_vgpr_workitem_id 0
854; GCN-NEXT:     .amdhsa_next_free_vgpr 16
855; GCN-NEXT:     .amdhsa_next_free_sgpr 23
856; GCN-NEXT:     .amdhsa_reserve_flat_scratch 0
857; GCN-NEXT:     .amdhsa_float_round_mode_32 0
858; GCN-NEXT:     .amdhsa_float_round_mode_16_64 0
859; GCN-NEXT:     .amdhsa_float_denorm_mode_32 0
860; GCN-NEXT:     .amdhsa_float_denorm_mode_16_64 3
861; GCN-NEXT:     .amdhsa_dx10_clamp 1
862; GCN-NEXT:     .amdhsa_ieee_mode 1
863; GCN-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
864; GCN-NEXT:     .amdhsa_exception_fp_denorm_src 0
865; GCN-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
866; GCN-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
867; GCN-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
868; GCN-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
869; GCN-NEXT:     .amdhsa_exception_int_div_zero 0
870; GCN-NEXT:    .end_amdhsa_kernel
871; GCN-NEXT:    .text
872  %shift = ashr <2 x i128> %lhs, %rhs
873  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
874  ret void
875}
876
877