1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define i128 @v_shl_i128_vv(i128 %lhs, i128 %rhs) {
5; GCN-LABEL: v_shl_i128_vv:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
9; GCN-NEXT:    v_lshl_b64 v[5:6], v[2:3], v4
10; GCN-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
11; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
12; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
13; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
14; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
15; GCN-NEXT:    v_lshl_b64 v[5:6], v[0:1], v5
16; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
17; GCN-NEXT:    v_lshl_b64 v[0:1], v[0:1], v4
18; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
19; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[4:5]
20; GCN-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc
21; GCN-NEXT:    v_cndmask_b32_e64 v3, v5, v3, s[4:5]
22; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
23; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
24; GCN-NEXT:    s_setpc_b64 s[30:31]
25  %shl = shl i128 %lhs, %rhs
26  ret i128 %shl
27}
28
29define i128 @v_lshr_i128_vv(i128 %lhs, i128 %rhs) {
30; GCN-LABEL: v_lshr_i128_vv:
31; GCN:       ; %bb.0:
32; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
34; GCN-NEXT:    v_lshr_b64 v[5:6], v[0:1], v4
35; GCN-NEXT:    v_lshl_b64 v[7:8], v[2:3], v7
36; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
37; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
38; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
39; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
40; GCN-NEXT:    v_lshr_b64 v[5:6], v[2:3], v5
41; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
42; GCN-NEXT:    v_lshr_b64 v[2:3], v[2:3], v4
43; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
44; GCN-NEXT:    v_cndmask_b32_e64 v0, v5, v0, s[4:5]
45; GCN-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc
46; GCN-NEXT:    v_cndmask_b32_e64 v1, v5, v1, s[4:5]
47; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
48; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
49; GCN-NEXT:    s_setpc_b64 s[30:31]
50
51  %shl = lshr i128 %lhs, %rhs
52  ret i128 %shl
53}
54
55define i128 @v_ashr_i128_vv(i128 %lhs, i128 %rhs) {
56; GCN-LABEL: v_ashr_i128_vv:
57; GCN:       ; %bb.0:
58; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
59; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 64, v4
60; GCN-NEXT:    v_lshr_b64 v[5:6], v[0:1], v4
61; GCN-NEXT:    v_lshl_b64 v[7:8], v[2:3], v7
62; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
63; GCN-NEXT:    v_or_b32_e32 v7, v5, v7
64; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 64, v4
65; GCN-NEXT:    v_or_b32_e32 v8, v6, v8
66; GCN-NEXT:    v_ashr_i64 v[5:6], v[2:3], v5
67; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
68; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
69; GCN-NEXT:    v_cndmask_b32_e64 v0, v5, v0, s[4:5]
70; GCN-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc
71; GCN-NEXT:    v_cndmask_b32_e64 v1, v5, v1, s[4:5]
72; GCN-NEXT:    v_ashr_i64 v[4:5], v[2:3], v4
73; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
74; GCN-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
75; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
76; GCN-NEXT:    s_setpc_b64 s[30:31]
77  %shl = ashr i128 %lhs, %rhs
78  ret i128 %shl
79}
80
81
82define i128 @v_shl_i128_vk(i128 %lhs) {
83; GCN-LABEL: v_shl_i128_vk:
84; GCN:       ; %bb.0:
85; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
86; GCN-NEXT:    v_lshrrev_b32_e32 v4, 15, v1
87; GCN-NEXT:    v_lshlrev_b32_e32 v5, 17, v2
88; GCN-NEXT:    v_or_b32_e32 v4, v5, v4
89; GCN-NEXT:    v_alignbit_b32 v1, v1, v0, 15
90; GCN-NEXT:    v_alignbit_b32 v3, v3, v2, 15
91; GCN-NEXT:    v_lshlrev_b32_e32 v0, 17, v0
92; GCN-NEXT:    v_mov_b32_e32 v2, v4
93; GCN-NEXT:    s_setpc_b64 s[30:31]
94  %shl = shl i128 %lhs, 17
95  ret i128 %shl
96}
97
98define i128 @v_lshr_i128_vk(i128 %lhs) {
99; GCN-LABEL: v_lshr_i128_vk:
100; GCN:       ; %bb.0:
101; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
102; GCN-NEXT:    v_alignbit_b32 v0, v3, v2, 1
103; GCN-NEXT:    v_lshrrev_b32_e32 v1, 1, v3
104; GCN-NEXT:    v_mov_b32_e32 v2, 0
105; GCN-NEXT:    v_mov_b32_e32 v3, 0
106; GCN-NEXT:    s_setpc_b64 s[30:31]
107  %shl = lshr i128 %lhs, 65
108  ret i128 %shl
109}
110
111define i128 @v_ashr_i128_vk(i128 %lhs) {
112; GCN-LABEL: v_ashr_i128_vk:
113; GCN:       ; %bb.0:
114; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
115; GCN-NEXT:    v_ashr_i64 v[4:5], v[2:3], 33
116; GCN-NEXT:    v_lshlrev_b32_e32 v0, 31, v2
117; GCN-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
118; GCN-NEXT:    v_or_b32_e32 v0, v1, v0
119; GCN-NEXT:    v_alignbit_b32 v1, v3, v2, 1
120; GCN-NEXT:    v_mov_b32_e32 v2, v4
121; GCN-NEXT:    v_mov_b32_e32 v3, v5
122; GCN-NEXT:    s_setpc_b64 s[30:31]
123  %shl = ashr i128 %lhs, 33
124  ret i128 %shl
125}
126
127define i128 @v_shl_i128_kv(i128 %rhs) {
128; GCN-LABEL: v_shl_i128_kv:
129; GCN:       ; %bb.0:
130; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
131; GCN-NEXT:    v_sub_i32_e32 v1, vcc, 64, v0
132; GCN-NEXT:    v_lshr_b64 v[2:3], 17, v1
133; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, 64, v0
134; GCN-NEXT:    v_lshl_b64 v[4:5], 17, v1
135; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
136; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc
137; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
138; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, v1, s[4:5]
139; GCN-NEXT:    v_lshl_b64 v[0:1], 17, v0
140; GCN-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
141; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[4:5]
142; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
143; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
144; GCN-NEXT:    s_setpc_b64 s[30:31]
145  %shl = shl i128 17, %rhs
146  ret i128 %shl
147}
148
149define i128 @v_lshr_i128_kv(i128 %rhs) {
150; GCN-LABEL: v_lshr_i128_kv:
151; GCN:       ; %bb.0:
152; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
153; GCN-NEXT:    s_movk_i32 s4, 0x41
154; GCN-NEXT:    s_mov_b32 s5, 0
155; GCN-NEXT:    v_lshr_b64 v[1:2], s[4:5], v0
156; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
157; GCN-NEXT:    v_mov_b32_e32 v3, s4
158; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
159; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
160; GCN-NEXT:    s_and_b64 vcc, s[4:5], vcc
161; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v1, s[4:5]
162; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
163; GCN-NEXT:    v_mov_b32_e32 v2, 0
164; GCN-NEXT:    v_mov_b32_e32 v3, 0
165; GCN-NEXT:    s_setpc_b64 s[30:31]
166  %shl = lshr i128 65, %rhs
167  ret i128 %shl
168}
169
170define i128 @v_ashr_i128_kv(i128 %rhs) {
171; GCN-LABEL: v_ashr_i128_kv:
172; GCN:       ; %bb.0:
173; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
174; GCN-NEXT:    v_lshr_b64 v[1:2], 33, v0
175; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v0
176; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
177; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
178; GCN-NEXT:    s_and_b64 vcc, s[4:5], vcc
179; GCN-NEXT:    v_cndmask_b32_e64 v0, 33, v1, s[4:5]
180; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
181; GCN-NEXT:    v_mov_b32_e32 v2, 0
182; GCN-NEXT:    v_mov_b32_e32 v3, 0
183; GCN-NEXT:    s_setpc_b64 s[30:31]
184  %shl = ashr i128 33, %rhs
185  ret i128 %shl
186}
187
188define amdgpu_kernel void @s_shl_i128_ss(i128 %lhs, i128 %rhs) {
189; GCN-LABEL: s_shl_i128_ss:
190; GCN:       ; %bb.0:
191; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
192; GCN-NEXT:    v_mov_b32_e32 v4, 0
193; GCN-NEXT:    v_mov_b32_e32 v5, 0
194; GCN-NEXT:    s_waitcnt lgkmcnt(0)
195; GCN-NEXT:    s_sub_i32 s2, 64, s8
196; GCN-NEXT:    s_sub_i32 s9, s8, 64
197; GCN-NEXT:    s_lshl_b64 s[0:1], s[6:7], s8
198; GCN-NEXT:    s_lshr_b64 s[2:3], s[4:5], s2
199; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
200; GCN-NEXT:    s_lshl_b64 s[10:11], s[4:5], s9
201; GCN-NEXT:    v_mov_b32_e32 v0, s11
202; GCN-NEXT:    v_mov_b32_e32 v1, s3
203; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
204; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
205; GCN-NEXT:    v_mov_b32_e32 v1, s7
206; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
207; GCN-NEXT:    v_cndmask_b32_e64 v3, v0, v1, s[0:1]
208; GCN-NEXT:    v_mov_b32_e32 v0, s10
209; GCN-NEXT:    v_mov_b32_e32 v1, s2
210; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
211; GCN-NEXT:    v_mov_b32_e32 v1, s6
212; GCN-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
213; GCN-NEXT:    s_lshl_b64 s[0:1], s[4:5], s8
214; GCN-NEXT:    v_mov_b32_e32 v0, s1
215; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
216; GCN-NEXT:    v_mov_b32_e32 v0, s0
217; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
218; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
219; GCN-NEXT:    s_endpgm
220  %shift = shl i128 %lhs, %rhs
221  store i128 %shift, i128 addrspace(1)* null
222  ret void
223}
224
225define amdgpu_kernel void @s_lshr_i128_ss(i128 %lhs, i128 %rhs) {
226; GCN-LABEL: s_lshr_i128_ss:
227; GCN:       ; %bb.0:
228; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
229; GCN-NEXT:    v_mov_b32_e32 v4, 0
230; GCN-NEXT:    v_mov_b32_e32 v5, 0
231; GCN-NEXT:    s_waitcnt lgkmcnt(0)
232; GCN-NEXT:    s_sub_i32 s2, 64, s8
233; GCN-NEXT:    s_sub_i32 s9, s8, 64
234; GCN-NEXT:    s_lshr_b64 s[0:1], s[4:5], s8
235; GCN-NEXT:    s_lshl_b64 s[2:3], s[6:7], s2
236; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
237; GCN-NEXT:    s_lshr_b64 s[10:11], s[6:7], s9
238; GCN-NEXT:    v_mov_b32_e32 v0, s11
239; GCN-NEXT:    v_mov_b32_e32 v1, s3
240; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
241; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
242; GCN-NEXT:    v_mov_b32_e32 v1, s5
243; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
244; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
245; GCN-NEXT:    v_mov_b32_e32 v0, s10
246; GCN-NEXT:    v_mov_b32_e32 v2, s2
247; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
248; GCN-NEXT:    v_mov_b32_e32 v2, s4
249; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
250; GCN-NEXT:    s_lshr_b64 s[0:1], s[6:7], s8
251; GCN-NEXT:    v_mov_b32_e32 v2, s1
252; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
253; GCN-NEXT:    v_mov_b32_e32 v2, s0
254; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
255; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
256; GCN-NEXT:    s_endpgm
257  %shift = lshr i128 %lhs, %rhs
258  store i128 %shift, i128 addrspace(1)* null
259  ret void
260}
261
262define amdgpu_kernel void @s_ashr_i128_ss(i128 %lhs, i128 %rhs) {
263; GCN-LABEL: s_ashr_i128_ss:
264; GCN:       ; %bb.0:
265; GCN-NEXT:    s_load_dwordx8 s[4:11], s[4:5], 0x0
266; GCN-NEXT:    s_waitcnt lgkmcnt(0)
267; GCN-NEXT:    s_sub_i32 s2, 64, s8
268; GCN-NEXT:    s_sub_i32 s9, s8, 64
269; GCN-NEXT:    s_lshr_b64 s[0:1], s[4:5], s8
270; GCN-NEXT:    s_lshl_b64 s[2:3], s[6:7], s2
271; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
272; GCN-NEXT:    s_ashr_i64 s[10:11], s[6:7], s9
273; GCN-NEXT:    v_mov_b32_e32 v0, s11
274; GCN-NEXT:    v_mov_b32_e32 v1, s3
275; GCN-NEXT:    v_cmp_lt_u32_e64 vcc, s8, 64
276; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
277; GCN-NEXT:    v_mov_b32_e32 v1, s5
278; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s8, 0
279; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
280; GCN-NEXT:    v_mov_b32_e32 v2, s2
281; GCN-NEXT:    v_mov_b32_e32 v0, s10
282; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
283; GCN-NEXT:    v_mov_b32_e32 v2, s4
284; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
285; GCN-NEXT:    s_ashr_i64 s[0:1], s[6:7], s8
286; GCN-NEXT:    s_ashr_i32 s2, s7, 31
287; GCN-NEXT:    v_mov_b32_e32 v2, s2
288; GCN-NEXT:    v_mov_b32_e32 v3, s1
289; GCN-NEXT:    v_mov_b32_e32 v4, s0
290; GCN-NEXT:    v_cndmask_b32_e32 v3, v2, v3, vcc
291; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
292; GCN-NEXT:    v_mov_b32_e32 v4, 0
293; GCN-NEXT:    v_mov_b32_e32 v5, 0
294; GCN-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
295; GCN-NEXT:    s_endpgm
296  %shift = ashr i128 %lhs, %rhs
297  store i128 %shift, i128 addrspace(1)* null
298  ret void
299}
300
301define <2 x i128> @v_shl_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
302; GCN-LABEL: v_shl_v2i128_vv:
303; GCN:       ; %bb.0:
304; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
305; GCN-NEXT:    v_sub_i32_e32 v18, vcc, 64, v8
306; GCN-NEXT:    v_lshl_b64 v[16:17], v[2:3], v8
307; GCN-NEXT:    v_lshr_b64 v[18:19], v[0:1], v18
308; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
309; GCN-NEXT:    v_cmp_gt_u64_e64 s[4:5], 64, v[8:9]
310; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
311; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
312; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
313; GCN-NEXT:    v_or_b32_e32 v19, v17, v19
314; GCN-NEXT:    v_or_b32_e32 v18, v16, v18
315; GCN-NEXT:    v_lshl_b64 v[16:17], v[0:1], v9
316; GCN-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
317; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
318; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[4:5]
319; GCN-NEXT:    v_sub_i32_e64 v16, s[6:7], 64, v12
320; GCN-NEXT:    v_cndmask_b32_e64 v11, v17, v19, s[4:5]
321; GCN-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
322; GCN-NEXT:    v_lshl_b64 v[9:10], v[6:7], v12
323; GCN-NEXT:    v_lshr_b64 v[16:17], v[4:5], v16
324; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
325; GCN-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc
326; GCN-NEXT:    v_or_b32_e32 v16, v9, v16
327; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[12:13]
328; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
329; GCN-NEXT:    v_or_b32_e32 v11, v10, v17
330; GCN-NEXT:    v_lshl_b64 v[9:10], v[4:5], v9
331; GCN-NEXT:    v_or_b32_e32 v15, v13, v15
332; GCN-NEXT:    v_or_b32_e32 v14, v12, v14
333; GCN-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
334; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
335; GCN-NEXT:    v_lshl_b64 v[0:1], v[0:1], v8
336; GCN-NEXT:    v_lshl_b64 v[4:5], v[4:5], v12
337; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
338; GCN-NEXT:    v_cndmask_b32_e64 v6, v9, v6, s[6:7]
339; GCN-NEXT:    v_cndmask_b32_e32 v9, v10, v11, vcc
340; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v7, s[6:7]
341; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, v0, s[4:5]
342; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[4:5]
343; GCN-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
344; GCN-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
345; GCN-NEXT:    s_setpc_b64 s[30:31]
346  %shl = shl <2 x i128> %lhs, %rhs
347  ret <2 x i128> %shl
348}
349
350define <2 x i128> @v_lshr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
351; GCN-LABEL: v_lshr_v2i128_vv:
352; GCN:       ; %bb.0:
353; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
354; GCN-NEXT:    v_sub_i32_e32 v18, vcc, 64, v8
355; GCN-NEXT:    v_lshr_b64 v[16:17], v[0:1], v8
356; GCN-NEXT:    v_lshl_b64 v[18:19], v[2:3], v18
357; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
358; GCN-NEXT:    v_cmp_gt_u64_e64 s[4:5], 64, v[8:9]
359; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
360; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
361; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
362; GCN-NEXT:    v_or_b32_e32 v19, v17, v19
363; GCN-NEXT:    v_or_b32_e32 v18, v16, v18
364; GCN-NEXT:    v_lshr_b64 v[16:17], v[2:3], v9
365; GCN-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
366; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
367; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[4:5]
368; GCN-NEXT:    v_sub_i32_e64 v16, s[6:7], 64, v12
369; GCN-NEXT:    v_cndmask_b32_e64 v11, v17, v19, s[4:5]
370; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
371; GCN-NEXT:    v_lshr_b64 v[9:10], v[4:5], v12
372; GCN-NEXT:    v_lshl_b64 v[16:17], v[6:7], v16
373; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
374; GCN-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc
375; GCN-NEXT:    v_or_b32_e32 v16, v9, v16
376; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[12:13]
377; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
378; GCN-NEXT:    v_or_b32_e32 v11, v10, v17
379; GCN-NEXT:    v_lshr_b64 v[9:10], v[6:7], v9
380; GCN-NEXT:    v_or_b32_e32 v15, v13, v15
381; GCN-NEXT:    v_or_b32_e32 v14, v12, v14
382; GCN-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
383; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
384; GCN-NEXT:    v_lshr_b64 v[2:3], v[2:3], v8
385; GCN-NEXT:    v_lshr_b64 v[6:7], v[6:7], v12
386; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
387; GCN-NEXT:    v_cndmask_b32_e64 v4, v9, v4, s[6:7]
388; GCN-NEXT:    v_cndmask_b32_e32 v9, v10, v11, vcc
389; GCN-NEXT:    v_cndmask_b32_e64 v5, v9, v5, s[6:7]
390; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[4:5]
391; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s[4:5]
392; GCN-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
393; GCN-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
394; GCN-NEXT:    s_setpc_b64 s[30:31]
395  %shl = lshr <2 x i128> %lhs, %rhs
396  ret <2 x i128> %shl
397}
398
399define <2 x i128> @v_ashr_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
400; GCN-LABEL: v_ashr_v2i128_vv:
401; GCN:       ; %bb.0:
402; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
403; GCN-NEXT:    v_sub_i32_e32 v18, vcc, 64, v8
404; GCN-NEXT:    v_lshr_b64 v[16:17], v[0:1], v8
405; GCN-NEXT:    v_lshl_b64 v[18:19], v[2:3], v18
406; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
407; GCN-NEXT:    v_cmp_gt_u64_e64 s[4:5], 64, v[8:9]
408; GCN-NEXT:    v_or_b32_e32 v11, v9, v11
409; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v8
410; GCN-NEXT:    v_or_b32_e32 v10, v8, v10
411; GCN-NEXT:    v_or_b32_e32 v19, v17, v19
412; GCN-NEXT:    v_or_b32_e32 v18, v16, v18
413; GCN-NEXT:    v_ashr_i64 v[16:17], v[2:3], v9
414; GCN-NEXT:    s_and_b64 s[4:5], s[6:7], s[4:5]
415; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
416; GCN-NEXT:    v_cndmask_b32_e64 v9, v16, v18, s[4:5]
417; GCN-NEXT:    v_sub_i32_e64 v16, s[6:7], 64, v12
418; GCN-NEXT:    v_cndmask_b32_e64 v11, v17, v19, s[4:5]
419; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
420; GCN-NEXT:    v_lshr_b64 v[9:10], v[4:5], v12
421; GCN-NEXT:    v_lshl_b64 v[16:17], v[6:7], v16
422; GCN-NEXT:    v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
423; GCN-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc
424; GCN-NEXT:    v_or_b32_e32 v16, v9, v16
425; GCN-NEXT:    v_cmp_gt_u64_e64 s[6:7], 64, v[12:13]
426; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, 64, v12
427; GCN-NEXT:    v_or_b32_e32 v11, v10, v17
428; GCN-NEXT:    v_ashr_i64 v[9:10], v[6:7], v9
429; GCN-NEXT:    v_or_b32_e32 v15, v13, v15
430; GCN-NEXT:    v_or_b32_e32 v14, v12, v14
431; GCN-NEXT:    s_and_b64 vcc, s[8:9], s[6:7]
432; GCN-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
433; GCN-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc
434; GCN-NEXT:    v_cndmask_b32_e64 v4, v9, v4, s[6:7]
435; GCN-NEXT:    v_cndmask_b32_e32 v9, v10, v11, vcc
436; GCN-NEXT:    v_cndmask_b32_e64 v5, v9, v5, s[6:7]
437; GCN-NEXT:    v_ashr_i64 v[8:9], v[2:3], v8
438; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
439; GCN-NEXT:    v_cndmask_b32_e64 v2, v3, v8, s[4:5]
440; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v9, s[4:5]
441; GCN-NEXT:    v_ashr_i64 v[8:9], v[6:7], v12
442; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v7
443; GCN-NEXT:    v_cndmask_b32_e32 v6, v7, v8, vcc
444; GCN-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
445; GCN-NEXT:    s_setpc_b64 s[30:31]
446  %shl = ashr <2 x i128> %lhs, %rhs
447  ret <2 x i128> %shl
448}
449
450define amdgpu_kernel void @s_shl_v2i128ss(<2 x i128> %lhs, <2 x i128> %rhs) {
451; GCN-LABEL: s_shl_v2i128ss:
452; GCN:       ; %bb.0:
453; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
454; GCN-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x8
455; GCN-NEXT:    v_mov_b32_e32 v8, 0
456; GCN-NEXT:    v_mov_b32_e32 v9, 0
457; GCN-NEXT:    s_waitcnt lgkmcnt(0)
458; GCN-NEXT:    v_cmp_lt_u64_e64 s[16:17], s[0:1], 64
459; GCN-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[2:3], 0
460; GCN-NEXT:    s_lshl_b64 s[20:21], s[8:9], s0
461; GCN-NEXT:    s_and_b64 vcc, s[18:19], s[16:17]
462; GCN-NEXT:    s_sub_i32 s18, 64, s0
463; GCN-NEXT:    s_lshl_b64 s[16:17], s[10:11], s0
464; GCN-NEXT:    s_lshr_b64 s[18:19], s[8:9], s18
465; GCN-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
466; GCN-NEXT:    s_sub_i32 s18, s0, 64
467; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
468; GCN-NEXT:    s_lshl_b64 s[8:9], s[8:9], s18
469; GCN-NEXT:    v_mov_b32_e32 v2, s9
470; GCN-NEXT:    v_mov_b32_e32 v3, s17
471; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
472; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
473; GCN-NEXT:    v_mov_b32_e32 v3, s11
474; GCN-NEXT:    v_cndmask_b32_e64 v3, v2, v3, s[0:1]
475; GCN-NEXT:    v_mov_b32_e32 v2, s8
476; GCN-NEXT:    v_mov_b32_e32 v4, s16
477; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
478; GCN-NEXT:    v_mov_b32_e32 v4, s10
479; GCN-NEXT:    v_mov_b32_e32 v0, s21
480; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
481; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[4:5], 64
482; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
483; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
484; GCN-NEXT:    v_mov_b32_e32 v0, s20
485; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
486; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
487; GCN-NEXT:    s_sub_i32 s2, 64, s4
488; GCN-NEXT:    s_lshl_b64 s[8:9], s[12:13], s4
489; GCN-NEXT:    s_lshl_b64 s[0:1], s[14:15], s4
490; GCN-NEXT:    s_lshr_b64 s[2:3], s[12:13], s2
491; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
492; GCN-NEXT:    v_mov_b32_e32 v4, s9
493; GCN-NEXT:    s_sub_i32 s0, s4, 64
494; GCN-NEXT:    v_cndmask_b32_e32 v5, 0, v4, vcc
495; GCN-NEXT:    v_mov_b32_e32 v4, s8
496; GCN-NEXT:    s_lshl_b64 s[8:9], s[12:13], s0
497; GCN-NEXT:    s_or_b64 s[0:1], s[4:5], s[6:7]
498; GCN-NEXT:    v_mov_b32_e32 v6, s9
499; GCN-NEXT:    v_mov_b32_e32 v7, s3
500; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
501; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
502; GCN-NEXT:    v_mov_b32_e32 v7, s15
503; GCN-NEXT:    v_cndmask_b32_e64 v7, v6, v7, s[0:1]
504; GCN-NEXT:    v_mov_b32_e32 v6, s8
505; GCN-NEXT:    v_mov_b32_e32 v10, s2
506; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v10, vcc
507; GCN-NEXT:    v_mov_b32_e32 v10, s14
508; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s[0:1]
509; GCN-NEXT:    v_mov_b32_e32 v10, 16
510; GCN-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
511; GCN-NEXT:    v_mov_b32_e32 v11, 0
512; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
513; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
514; GCN-NEXT:    s_endpgm
515  %shift = shl <2 x i128> %lhs, %rhs
516  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
517  ret void
518}
519
520define amdgpu_kernel void @s_lshr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
521; GCN-LABEL: s_lshr_v2i128_ss:
522; GCN:       ; %bb.0:
523; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
524; GCN-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x8
525; GCN-NEXT:    v_mov_b32_e32 v8, 0
526; GCN-NEXT:    v_mov_b32_e32 v9, 0
527; GCN-NEXT:    s_waitcnt lgkmcnt(0)
528; GCN-NEXT:    v_cmp_lt_u64_e64 s[16:17], s[0:1], 64
529; GCN-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[2:3], 0
530; GCN-NEXT:    s_lshr_b64 s[20:21], s[10:11], s0
531; GCN-NEXT:    s_and_b64 vcc, s[18:19], s[16:17]
532; GCN-NEXT:    s_sub_i32 s18, 64, s0
533; GCN-NEXT:    s_lshr_b64 s[16:17], s[8:9], s0
534; GCN-NEXT:    s_lshl_b64 s[18:19], s[10:11], s18
535; GCN-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
536; GCN-NEXT:    s_sub_i32 s18, s0, 64
537; GCN-NEXT:    v_mov_b32_e32 v0, s21
538; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
539; GCN-NEXT:    v_cndmask_b32_e32 v3, 0, v0, vcc
540; GCN-NEXT:    v_mov_b32_e32 v0, s20
541; GCN-NEXT:    s_lshr_b64 s[10:11], s[10:11], s18
542; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v0, vcc
543; GCN-NEXT:    v_mov_b32_e32 v0, s11
544; GCN-NEXT:    v_mov_b32_e32 v1, s17
545; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
546; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
547; GCN-NEXT:    v_mov_b32_e32 v1, s9
548; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
549; GCN-NEXT:    v_mov_b32_e32 v0, s10
550; GCN-NEXT:    v_mov_b32_e32 v4, s16
551; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
552; GCN-NEXT:    v_mov_b32_e32 v4, s8
553; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
554; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[4:5], 64
555; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
556; GCN-NEXT:    s_lshr_b64 s[8:9], s[14:15], s4
557; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
558; GCN-NEXT:    s_sub_i32 s2, 64, s4
559; GCN-NEXT:    s_lshr_b64 s[0:1], s[12:13], s4
560; GCN-NEXT:    s_lshl_b64 s[2:3], s[14:15], s2
561; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
562; GCN-NEXT:    v_mov_b32_e32 v4, s9
563; GCN-NEXT:    s_sub_i32 s0, s4, 64
564; GCN-NEXT:    v_cndmask_b32_e32 v7, 0, v4, vcc
565; GCN-NEXT:    v_mov_b32_e32 v4, s8
566; GCN-NEXT:    s_lshr_b64 s[8:9], s[14:15], s0
567; GCN-NEXT:    s_or_b64 s[0:1], s[4:5], s[6:7]
568; GCN-NEXT:    v_cndmask_b32_e32 v6, 0, v4, vcc
569; GCN-NEXT:    v_mov_b32_e32 v4, s9
570; GCN-NEXT:    v_mov_b32_e32 v5, s3
571; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
572; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
573; GCN-NEXT:    v_mov_b32_e32 v5, s13
574; GCN-NEXT:    v_cndmask_b32_e64 v5, v4, v5, s[0:1]
575; GCN-NEXT:    v_mov_b32_e32 v4, s8
576; GCN-NEXT:    v_mov_b32_e32 v10, s2
577; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
578; GCN-NEXT:    v_mov_b32_e32 v10, s12
579; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v10, s[0:1]
580; GCN-NEXT:    v_mov_b32_e32 v10, 16
581; GCN-NEXT:    v_mov_b32_e32 v11, 0
582; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
583; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
584; GCN-NEXT:    s_endpgm
585  %shift = lshr <2 x i128> %lhs, %rhs
586  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
587  ret void
588}
589
590define amdgpu_kernel void @s_ashr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
591; GCN-LABEL: s_ashr_v2i128_ss:
592; GCN:       ; %bb.0:
593; GCN-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x0
594; GCN-NEXT:    s_load_dwordx8 s[0:7], s[4:5], 0x8
595; GCN-NEXT:    v_mov_b32_e32 v8, 0
596; GCN-NEXT:    v_mov_b32_e32 v9, 0
597; GCN-NEXT:    s_waitcnt lgkmcnt(0)
598; GCN-NEXT:    s_ashr_i32 s22, s11, 31
599; GCN-NEXT:    v_cmp_lt_u64_e64 s[16:17], s[0:1], 64
600; GCN-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[2:3], 0
601; GCN-NEXT:    s_ashr_i64 s[20:21], s[10:11], s0
602; GCN-NEXT:    s_and_b64 vcc, s[18:19], s[16:17]
603; GCN-NEXT:    s_sub_i32 s18, 64, s0
604; GCN-NEXT:    s_lshr_b64 s[16:17], s[8:9], s0
605; GCN-NEXT:    s_lshl_b64 s[18:19], s[10:11], s18
606; GCN-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
607; GCN-NEXT:    s_sub_i32 s18, s0, 64
608; GCN-NEXT:    v_mov_b32_e32 v0, s22
609; GCN-NEXT:    v_mov_b32_e32 v1, s21
610; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
611; GCN-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
612; GCN-NEXT:    v_mov_b32_e32 v1, s20
613; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], s18
614; GCN-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
615; GCN-NEXT:    v_mov_b32_e32 v0, s11
616; GCN-NEXT:    v_mov_b32_e32 v1, s17
617; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
618; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
619; GCN-NEXT:    v_mov_b32_e32 v1, s9
620; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
621; GCN-NEXT:    v_mov_b32_e32 v0, s10
622; GCN-NEXT:    v_mov_b32_e32 v4, s16
623; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
624; GCN-NEXT:    v_mov_b32_e32 v4, s8
625; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
626; GCN-NEXT:    v_cmp_lt_u64_e64 s[0:1], s[4:5], 64
627; GCN-NEXT:    v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
628; GCN-NEXT:    s_ashr_i64 s[8:9], s[14:15], s4
629; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
630; GCN-NEXT:    s_sub_i32 s2, 64, s4
631; GCN-NEXT:    s_ashr_i32 s10, s15, 31
632; GCN-NEXT:    s_lshr_b64 s[0:1], s[12:13], s4
633; GCN-NEXT:    s_lshl_b64 s[2:3], s[14:15], s2
634; GCN-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
635; GCN-NEXT:    v_mov_b32_e32 v4, s10
636; GCN-NEXT:    v_mov_b32_e32 v5, s9
637; GCN-NEXT:    s_sub_i32 s0, s4, 64
638; GCN-NEXT:    v_cndmask_b32_e32 v7, v4, v5, vcc
639; GCN-NEXT:    v_mov_b32_e32 v5, s8
640; GCN-NEXT:    s_ashr_i64 s[8:9], s[14:15], s0
641; GCN-NEXT:    s_or_b64 s[0:1], s[4:5], s[6:7]
642; GCN-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc
643; GCN-NEXT:    v_mov_b32_e32 v4, s9
644; GCN-NEXT:    v_mov_b32_e32 v5, s3
645; GCN-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[0:1], 0
646; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
647; GCN-NEXT:    v_mov_b32_e32 v5, s13
648; GCN-NEXT:    v_cndmask_b32_e64 v5, v4, v5, s[0:1]
649; GCN-NEXT:    v_mov_b32_e32 v4, s8
650; GCN-NEXT:    v_mov_b32_e32 v10, s2
651; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
652; GCN-NEXT:    v_mov_b32_e32 v10, s12
653; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v10, s[0:1]
654; GCN-NEXT:    v_mov_b32_e32 v10, 16
655; GCN-NEXT:    v_mov_b32_e32 v11, 0
656; GCN-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
657; GCN-NEXT:    flat_store_dwordx4 v[10:11], v[4:7]
658; GCN-NEXT:    s_endpgm
659  %shift = ashr <2 x i128> %lhs, %rhs
660  store <2 x i128> %shift, <2 x i128> addrspace(1)* null
661  ret void
662}
663
664