1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
3
4; CHECK-LABEL: {{^}}phi1:
5; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
6; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]]
7define amdgpu_ps void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
8main_body:
9  %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
10  %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
11  %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0)
12  %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16)
13  %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32)
14  %tmp24 = fptosi float %tmp22 to i32
15  %tmp25 = icmp ne i32 %tmp24, 0
16  br i1 %tmp25, label %ENDIF, label %ELSE
17
18ELSE:                                             ; preds = %main_body
19  %tmp26 = fsub float -0.000000e+00, %tmp21
20  br label %ENDIF
21
22ENDIF:                                            ; preds = %ELSE, %main_body
23  %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ]
24  %tmp27 = fadd float %temp.0, %tmp23
25  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0
26  ret void
27}
28
29; Make sure this program doesn't crash
30; CHECK-LABEL: {{^}}phi2:
31define amdgpu_ps void @phi2(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 {
32main_body:
33  %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
34  %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
35  %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16)
36  %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32)
37  %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 36)
38  %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 40)
39  %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 48)
40  %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 52)
41  %tmp27 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 56)
42  %tmp28 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 64)
43  %tmp29 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 68)
44  %tmp30 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 72)
45  %tmp31 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 76)
46  %tmp32 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 80)
47  %tmp33 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 84)
48  %tmp34 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 88)
49  %tmp35 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 92)
50  %tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0
51  %tmp37 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp36, !tbaa !0
52  %tmp38 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0
53  %tmp39 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp38, !tbaa !0
54  %i.i = extractelement <2 x i32> %arg5, i32 0
55  %j.i = extractelement <2 x i32> %arg5, i32 1
56  %i.f.i = bitcast i32 %i.i to float
57  %j.f.i = bitcast i32 %j.i to float
58  %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1
59  %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1
60  %i.i19 = extractelement <2 x i32> %arg5, i32 0
61  %j.i20 = extractelement <2 x i32> %arg5, i32 1
62  %i.f.i21 = bitcast i32 %i.i19 to float
63  %j.f.i22 = bitcast i32 %j.i20 to float
64  %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #1
65  %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #1
66  %i.i13 = extractelement <2 x i32> %arg5, i32 0
67  %j.i14 = extractelement <2 x i32> %arg5, i32 1
68  %i.f.i15 = bitcast i32 %i.i13 to float
69  %j.f.i16 = bitcast i32 %j.i14 to float
70  %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #1
71  %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #1
72  %i.i7 = extractelement <2 x i32> %arg5, i32 0
73  %j.i8 = extractelement <2 x i32> %arg5, i32 1
74  %i.f.i9 = bitcast i32 %i.i7 to float
75  %j.f.i10 = bitcast i32 %j.i8 to float
76  %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #1
77  %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #1
78  %i.i1 = extractelement <2 x i32> %arg5, i32 0
79  %j.i2 = extractelement <2 x i32> %arg5, i32 1
80  %i.f.i3 = bitcast i32 %i.i1 to float
81  %j.f.i4 = bitcast i32 %j.i2 to float
82  %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #1
83  %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #1
84  %tmp45 = bitcast float %p2.i to i32
85  %tmp46 = bitcast float %p2.i24 to i32
86  %tmp47 = insertelement <2 x i32> undef, i32 %tmp45, i32 0
87  %tmp48 = insertelement <2 x i32> %tmp47, i32 %tmp46, i32 1
88  %tmp39.bc = bitcast <16 x i8> %tmp39 to <4 x i32>
89  %tmp49 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp48, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
90  %tmp50 = extractelement <4 x float> %tmp49, i32 2
91  %tmp51 = call float @llvm.fabs.f32(float %tmp50)
92  %tmp52 = fmul float %p2.i18, %p2.i18
93  %tmp53 = fmul float %p2.i12, %p2.i12
94  %tmp54 = fadd float %tmp53, %tmp52
95  %tmp55 = fmul float %p2.i6, %p2.i6
96  %tmp56 = fadd float %tmp54, %tmp55
97  %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56)
98  %tmp58 = fmul float %p2.i18, %tmp57
99  %tmp59 = fmul float %p2.i12, %tmp57
100  %tmp60 = fmul float %p2.i6, %tmp57
101  %tmp61 = fmul float %tmp58, %tmp22
102  %tmp62 = fmul float %tmp59, %tmp23
103  %tmp63 = fadd float %tmp62, %tmp61
104  %tmp64 = fmul float %tmp60, %tmp24
105  %tmp65 = fadd float %tmp63, %tmp64
106  %tmp66 = fsub float -0.000000e+00, %tmp25
107  %tmp67 = fmul float %tmp65, %tmp51
108  %tmp68 = fadd float %tmp67, %tmp66
109  %tmp69 = fmul float %tmp26, %tmp68
110  %tmp70 = fmul float %tmp27, %tmp68
111  %tmp71 = call float @llvm.fabs.f32(float %tmp69)
112  %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71
113  %tmp73 = sext i1 %tmp72 to i32
114  %tmp74 = bitcast i32 %tmp73 to float
115  %tmp75 = bitcast float %tmp74 to i32
116  %tmp76 = icmp ne i32 %tmp75, 0
117  br i1 %tmp76, label %IF, label %ENDIF
118
119IF:                                               ; preds = %main_body
120  %tmp77 = fsub float -0.000000e+00, %tmp69
121  %tmp78 = call float @llvm.exp2.f32(float %tmp77)
122  %tmp79 = fsub float -0.000000e+00, %tmp78
123  %tmp80 = fadd float 1.000000e+00, %tmp79
124  %tmp81 = fdiv float 1.000000e+00, %tmp69
125  %tmp82 = fmul float %tmp80, %tmp81
126  %tmp83 = fmul float %tmp31, %tmp82
127  br label %ENDIF
128
129ENDIF:                                            ; preds = %IF, %main_body
130  %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ]
131  %tmp84 = call float @llvm.fabs.f32(float %tmp70)
132  %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84
133  %tmp86 = sext i1 %tmp85 to i32
134  %tmp87 = bitcast i32 %tmp86 to float
135  %tmp88 = bitcast float %tmp87 to i32
136  %tmp89 = icmp ne i32 %tmp88, 0
137  br i1 %tmp89, label %IF25, label %ENDIF24
138
139IF25:                                             ; preds = %ENDIF
140  %tmp90 = fsub float -0.000000e+00, %tmp70
141  %tmp91 = call float @llvm.exp2.f32(float %tmp90)
142  %tmp92 = fsub float -0.000000e+00, %tmp91
143  %tmp93 = fadd float 1.000000e+00, %tmp92
144  %tmp94 = fdiv float 1.000000e+00, %tmp70
145  %tmp95 = fmul float %tmp93, %tmp94
146  %tmp96 = fmul float %tmp35, %tmp95
147  br label %ENDIF24
148
149ENDIF24:                                          ; preds = %IF25, %ENDIF
150  %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ]
151  %tmp97 = fmul float %tmp28, %temp4.0
152  %tmp98 = fmul float %tmp29, %temp4.0
153  %tmp99 = fmul float %tmp30, %temp4.0
154  %tmp100 = fmul float %tmp32, %temp8.0
155  %tmp101 = fadd float %tmp100, %tmp97
156  %tmp102 = fmul float %tmp33, %temp8.0
157  %tmp103 = fadd float %tmp102, %tmp98
158  %tmp104 = fmul float %tmp34, %temp8.0
159  %tmp105 = fadd float %tmp104, %tmp99
160  %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21)
161  %tmp107 = fsub float -0.000000e+00, %tmp101
162  %tmp108 = fmul float %tmp107, %tmp106
163  %tmp109 = fsub float -0.000000e+00, %tmp103
164  %tmp110 = fmul float %tmp109, %tmp106
165  %tmp111 = fsub float -0.000000e+00, %tmp105
166  %tmp112 = fmul float %tmp111, %tmp106
167  %tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110)
168  %tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00)
169  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0
170  ret void
171}
172
173; We just want ot make sure the program doesn't crash
174; CHECK-LABEL: {{^}}loop:
175define amdgpu_ps void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
176main_body:
177  %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
178  %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
179  %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0)
180  %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 4)
181  %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 8)
182  %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 12)
183  %tmp25 = fptosi float %tmp24 to i32
184  %tmp26 = bitcast i32 %tmp25 to float
185  %tmp27 = bitcast float %tmp26 to i32
186  br label %LOOP
187
188LOOP:                                             ; preds = %ENDIF, %main_body
189  %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ]
190  %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ]
191  %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ]
192  %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ]
193  %tmp28 = bitcast float %temp8.0 to i32
194  %tmp29 = icmp sge i32 %tmp28, %tmp27
195  %tmp30 = sext i1 %tmp29 to i32
196  %tmp31 = bitcast i32 %tmp30 to float
197  %tmp32 = bitcast float %tmp31 to i32
198  %tmp33 = icmp ne i32 %tmp32, 0
199  br i1 %tmp33, label %IF, label %ENDIF
200
201IF:                                               ; preds = %LOOP
202  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00, i1 true, i1 true) #0
203  ret void
204
205ENDIF:                                            ; preds = %LOOP
206  %tmp34 = bitcast float %temp8.0 to i32
207  %tmp35 = add i32 %tmp34, 1
208  %tmp36 = bitcast i32 %tmp35 to float
209  br label %LOOP
210}
211
212; This checks for a bug in the FixSGPRCopies pass where VReg96
213; registers were being identified as an SGPR regclass which was causing
214; an assertion failure.
215
216; CHECK-LABEL: {{^}}sample_v3:
217; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11
218; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13
219; CHECK: s_branch
220
221; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
222; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
223
224; CHECK: BB{{[0-9]+_[0-9]+}}:
225; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}}
226; CHECK: exp
227; CHECK: s_endpgm
228define amdgpu_ps void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
229entry:
230  %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0
231  %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
232  %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 16)
233  %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0
234  %tmp24 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp23, !tbaa !0
235  %tmp25 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 0
236  %tmp26 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp25, !tbaa !0
237  %tmp27 = fcmp oeq float %tmp22, 0.000000e+00
238  %tmp26.bc = bitcast <16 x i8> %tmp26 to <4 x i32>
239  br i1 %tmp27, label %if, label %else
240
241if:                                               ; preds = %entry
242  %val.if = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 11, i32 13>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
243  %val.if.0 = extractelement <4 x float> %val.if, i32 0
244  %val.if.1 = extractelement <4 x float> %val.if, i32 1
245  %val.if.2 = extractelement <4 x float> %val.if, i32 2
246  br label %endif
247
248else:                                             ; preds = %entry
249  %val.else = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 5, i32 7>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
250  %val.else.0 = extractelement <4 x float> %val.else, i32 0
251  %val.else.1 = extractelement <4 x float> %val.else, i32 1
252  %val.else.2 = extractelement <4 x float> %val.else, i32 2
253  br label %endif
254
255endif:                                            ; preds = %else, %if
256  %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ]
257  %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ]
258  %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ]
259  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %val.0, float %val.1, float %val.2, float 0.000000e+00, i1 true, i1 true) #0
260  ret void
261}
262
263; CHECK-LABEL: {{^}}copy1:
264; CHECK: buffer_load_dword
265; CHECK: v_add
266; CHECK: s_endpgm
267define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) {
268entry:
269  %tmp = load float, float addrspace(1)* %in0
270  %tmp1 = fcmp oeq float %tmp, 0.000000e+00
271  br i1 %tmp1, label %if0, label %endif
272
273if0:                                              ; preds = %entry
274  %tmp2 = bitcast float %tmp to i32
275  %tmp3 = fcmp olt float %tmp, 0.000000e+00
276  br i1 %tmp3, label %if1, label %endif
277
278if1:                                              ; preds = %if0
279  %tmp4 = add i32 %tmp2, 1
280  br label %endif
281
282endif:                                            ; preds = %if1, %if0, %entry
283  %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ]
284  %tmp6 = bitcast i32 %tmp5 to float
285  store float %tmp6, float addrspace(1)* %out
286  ret void
287}
288
289; This test is just checking that we don't crash / assertion fail.
290; CHECK-LABEL: {{^}}copy2:
291; CHECK: s_endpgm
292define amdgpu_ps void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
293entry:
294  br label %LOOP68
295
296LOOP68:                                           ; preds = %ENDIF69, %entry
297  %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
298  %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
299  %g = icmp eq i32 0, %t
300  %l = bitcast float %temp4.7 to i32
301  br i1 %g, label %IF70, label %ENDIF69
302
303IF70:                                             ; preds = %LOOP68
304  %q = icmp ne i32 %l, 13
305  %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00
306  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0
307  ret void
308
309ENDIF69:                                          ; preds = %LOOP68
310  %u = add i32 %l, %t
311  %v = bitcast i32 %u to float
312  %x = add i32 %t, -1
313  br label %LOOP68
314}
315
316; This test checks that image_sample resource descriptors aren't loaded into
317; vgprs.  The verifier will fail if this happens.
318; CHECK-LABEL:{{^}}sample_rsrc
319
320; CHECK: s_cmp_eq_u32
321; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]]
322
323; CHECK: v_add_i32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}
324
325; [[END]]:
326; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}}
327; CHECK: s_endpgm
328define amdgpu_ps void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
329bb:
330  %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0
331  %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !3
332  %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16)
333  %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0
334  %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !3
335  %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0
336  %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !3
337  %i.i = extractelement <2 x i32> %arg7, i32 0
338  %j.i = extractelement <2 x i32> %arg7, i32 1
339  %i.f.i = bitcast i32 %i.i to float
340  %j.f.i = bitcast i32 %j.i to float
341  %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0
342  %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0
343  %i.i1 = extractelement <2 x i32> %arg7, i32 0
344  %j.i2 = extractelement <2 x i32> %arg7, i32 1
345  %i.f.i3 = bitcast i32 %i.i1 to float
346  %j.f.i4 = bitcast i32 %j.i2 to float
347  %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #0
348  %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #0
349  %tmp31 = bitcast float %tmp23 to i32
350  %tmp36 = icmp ne i32 %tmp31, 0
351  br i1 %tmp36, label %bb38, label %bb80
352
353bb38:                                             ; preds = %bb
354  %tmp52 = bitcast float %p2.i to i32
355  %tmp53 = bitcast float %p2.i6 to i32
356  %tmp54 = insertelement <2 x i32> undef, i32 %tmp52, i32 0
357  %tmp55 = insertelement <2 x i32> %tmp54, i32 %tmp53, i32 1
358  %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32>
359  %tmp58 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp55, <8 x i32> %tmp56, <4 x i32> %tmp28, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
360  br label %bb71
361
362bb80:                                             ; preds = %bb
363  %tmp81 = bitcast float %p2.i to i32
364  %tmp82 = bitcast float %p2.i6 to i32
365  %tmp82.2 = add i32 %tmp82, 1
366  %tmp83 = insertelement <2 x i32> undef, i32 %tmp81, i32 0
367  %tmp84 = insertelement <2 x i32> %tmp83, i32 %tmp82.2, i32 1
368  %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32>
369  %tmp87 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
370  br label %bb71
371
372bb71:                                             ; preds = %bb80, %bb38
373  %tmp72 = phi <4 x float> [ %tmp58, %bb38 ], [ %tmp87, %bb80 ]
374  %tmp88 = extractelement <4 x float> %tmp72, i32 0
375  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0
376  ret void
377}
378
379; Check the the resource descriptor is stored in an sgpr.
380; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
381; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
382define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
383bb:
384  %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
385  %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
386  %tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0
387  %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
388  %tmp10 = extractelement <4 x float> %tmp9, i32 0
389  %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10)
390  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
391  ret void
392}
393
394; Check the the sampler is stored in an sgpr.
395; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
396; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
397define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 {
398bb:
399  %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
400  %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
401  %tmp8 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp7, align 16, !tbaa !0
402  %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> undef, <4 x i32> %tmp8, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
403  %tmp10 = extractelement <4 x float> %tmp9, i32 0
404  %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef)
405  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
406  ret void
407}
408
409declare float @llvm.fabs.f32(float) #1
410declare float @llvm.amdgcn.rsq.f32(float) #1
411declare float @llvm.exp2.f32(float) #1
412declare float @llvm.pow.f32(float, float) #1
413declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
414declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
415declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
416declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
417declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
418declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
419
420declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
421declare float @llvm.SI.load.const(<16 x i8>, i32) #1
422
423attributes #0 = { nounwind }
424attributes #1 = { nounwind readnone }
425
426!0 = !{!1, !1, i64 0, i32 1}
427!1 = !{!"const", !2}
428!2 = !{!"tbaa root"}
429!3 = !{!1, !1, i64 0}
430