1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
3;
4; Most SALU instructions ignore control flow, so we need to make sure
5; they don't overwrite values from other blocks.
6
7; If the branch decision is made based on a value in an SGPR then all
8; threads will execute the same code paths, so we don't need to worry
9; about instructions in different blocks overwriting each other.
10
11define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
12; SI-LABEL: sgpr_if_else_salu_br:
13; SI:       ; %bb.0: ; %entry
14; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
15; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xb
16; SI-NEXT:    s_load_dword s0, s[0:1], 0xf
17; SI-NEXT:    s_waitcnt lgkmcnt(0)
18; SI-NEXT:    s_cmp_lg_u32 s8, 0
19; SI-NEXT:    s_cbranch_scc0 BB0_2
20; SI-NEXT:  ; %bb.1: ; %else
21; SI-NEXT:    s_add_i32 s0, s11, s0
22; SI-NEXT:    s_branch BB0_3
23; SI-NEXT:  BB0_2: ; %if
24; SI-NEXT:    s_sub_i32 s0, s9, s10
25; SI-NEXT:  BB0_3: ; %endif
26; SI-NEXT:    s_add_i32 s0, s0, s8
27; SI-NEXT:    s_mov_b32 s7, 0xf000
28; SI-NEXT:    s_mov_b32 s6, -1
29; SI-NEXT:    v_mov_b32_e32 v0, s0
30; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
31; SI-NEXT:    s_endpgm
32entry:
33  %0 = icmp eq i32 %a, 0
34  br i1 %0, label %if, label %else
35
36if:
37  %1 = sub i32 %b, %c
38  br label %endif
39
40else:
41  %2 = add i32 %d, %e
42  br label %endif
43
44endif:
45  %3 = phi i32 [%1, %if], [%2, %else]
46  %4 = add i32 %3, %a
47  store i32 %4, i32 addrspace(1)* %out
48  ret void
49}
50
51define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
52; SI-LABEL: sgpr_if_else_salu_br_opt:
53; SI:       ; %bb.0: ; %entry
54; SI-NEXT:    s_load_dword s2, s[0:1], 0x13
55; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
56; SI-NEXT:    s_waitcnt lgkmcnt(0)
57; SI-NEXT:    s_cmp_lg_u32 s2, 0
58; SI-NEXT:    s_cbranch_scc0 BB1_2
59; SI-NEXT:  ; %bb.1: ; %else
60; SI-NEXT:    s_load_dword s3, s[0:1], 0x2e
61; SI-NEXT:    s_load_dword s0, s[0:1], 0x37
62; SI-NEXT:    s_branch BB1_3
63; SI-NEXT:  BB1_2: ; %if
64; SI-NEXT:    s_load_dword s3, s[0:1], 0x1c
65; SI-NEXT:    s_load_dword s0, s[0:1], 0x25
66; SI-NEXT:  BB1_3: ; %endif
67; SI-NEXT:    s_waitcnt lgkmcnt(0)
68; SI-NEXT:    s_add_i32 s0, s3, s0
69; SI-NEXT:    s_add_i32 s0, s0, s2
70; SI-NEXT:    s_mov_b32 s7, 0xf000
71; SI-NEXT:    s_mov_b32 s6, -1
72; SI-NEXT:    v_mov_b32_e32 v0, s0
73; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
74; SI-NEXT:    s_endpgm
75entry:
76  %cmp0 = icmp eq i32 %a, 0
77  br i1 %cmp0, label %if, label %else
78
79if:
80  %add0 = add i32 %b, %c
81  br label %endif
82
83else:
84  %add1 = add i32 %d, %e
85  br label %endif
86
87endif:
88  %phi = phi i32 [%add0, %if], [%add1, %else]
89  %add2 = add i32 %phi, %a
90  store i32 %add2, i32 addrspace(1)* %out
91  ret void
92}
93
94; The two S_ADD instructions should write to different registers, since
95; different threads will take different control flow paths.
96define amdgpu_kernel void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
97; SI-LABEL: sgpr_if_else_valu_br:
98; SI:       ; %bb.0: ; %entry
99; SI-NEXT:    v_cvt_f32_u32_e32 v0, v0
100; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
101; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xc
102; SI-NEXT:    ; implicit-def: $sgpr6
103; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v0
104; SI-NEXT:    s_and_saveexec_b64 s[8:9], vcc
105; SI-NEXT:    s_xor_b64 s[8:9], exec, s[8:9]
106; SI-NEXT:    s_cbranch_execz BB2_2
107; SI-NEXT:  ; %bb.1: ; %else
108; SI-NEXT:    s_waitcnt lgkmcnt(0)
109; SI-NEXT:    s_add_i32 s6, s2, s3
110; SI-NEXT:  BB2_2: ; %Flow
111; SI-NEXT:    s_waitcnt lgkmcnt(0)
112; SI-NEXT:    s_or_saveexec_b64 s[2:3], s[8:9]
113; SI-NEXT:    v_mov_b32_e32 v0, s6
114; SI-NEXT:    s_xor_b64 exec, exec, s[2:3]
115; SI-NEXT:  ; %bb.3: ; %if
116; SI-NEXT:    s_add_i32 s0, s0, s1
117; SI-NEXT:    v_mov_b32_e32 v0, s0
118; SI-NEXT:  ; %bb.4: ; %endif
119; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
120; SI-NEXT:    s_mov_b32 s7, 0xf000
121; SI-NEXT:    s_mov_b32 s6, -1
122; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
123; SI-NEXT:    s_endpgm
124entry:
125  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
126  %tid_f = uitofp i32 %tid to float
127  %tmp1 = fcmp ueq float %tid_f, 0.0
128  br i1 %tmp1, label %if, label %else
129
130if:
131  %tmp2 = add i32 %b, %c
132  br label %endif
133
134else:
135  %tmp3 = add i32 %d, %e
136  br label %endif
137
138endif:
139  %tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
140  store i32 %tmp4, i32 addrspace(1)* %out
141  ret void
142}
143
144define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
145; SI-LABEL: sgpr_if_else_valu_cmp_phi_br:
146; SI:       ; %bb.0: ; %entry
147; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
148; SI-NEXT:    s_mov_b32 s14, 0
149; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
150; SI-NEXT:    ; implicit-def: $sgpr2_sgpr3
151; SI-NEXT:    s_and_saveexec_b64 s[8:9], vcc
152; SI-NEXT:    s_xor_b64 s[8:9], exec, s[8:9]
153; SI-NEXT:    s_cbranch_execz BB3_2
154; SI-NEXT:  ; %bb.1: ; %else
155; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
156; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
157; SI-NEXT:    v_mov_b32_e32 v2, 0
158; SI-NEXT:    s_mov_b32 s15, 0xf000
159; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
160; SI-NEXT:    s_waitcnt lgkmcnt(0)
161; SI-NEXT:    buffer_load_dword v1, v[1:2], s[12:15], 0 addr64
162; SI-NEXT:    s_waitcnt vmcnt(0)
163; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v1
164; SI-NEXT:    s_and_b64 s[2:3], vcc, exec
165; SI-NEXT:    s_or_b64 s[2:3], s[0:1], s[2:3]
166; SI-NEXT:  BB3_2: ; %Flow
167; SI-NEXT:    s_or_saveexec_b64 s[0:1], s[8:9]
168; SI-NEXT:    s_xor_b64 exec, exec, s[0:1]
169; SI-NEXT:    s_cbranch_execz BB3_4
170; SI-NEXT:  ; %bb.3: ; %if
171; SI-NEXT:    s_mov_b32 s11, 0xf000
172; SI-NEXT:    s_mov_b32 s10, 0
173; SI-NEXT:    s_waitcnt lgkmcnt(0)
174; SI-NEXT:    s_mov_b64 s[8:9], s[6:7]
175; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
176; SI-NEXT:    v_mov_b32_e32 v1, 0
177; SI-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
178; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
179; SI-NEXT:    s_waitcnt vmcnt(0)
180; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
181; SI-NEXT:    s_and_b64 s[6:7], vcc, exec
182; SI-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
183; SI-NEXT:  BB3_4: ; %endif
184; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
185; SI-NEXT:    s_waitcnt lgkmcnt(0)
186; SI-NEXT:    s_mov_b32 s7, 0xf000
187; SI-NEXT:    s_mov_b32 s6, -1
188; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[2:3]
189; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
190; SI-NEXT:    s_endpgm
191entry:
192  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
193  %tmp1 = icmp eq i32 %tid, 0
194  br i1 %tmp1, label %if, label %else
195
196if:
197  %gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
198  %a.val = load i32, i32 addrspace(1)* %gep.if
199  %cmp.if = icmp eq i32 %a.val, 0
200  br label %endif
201
202else:
203  %gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
204  %b.val = load i32, i32 addrspace(1)* %gep.else
205  %cmp.else = icmp slt i32 %b.val, 0
206  br label %endif
207
208endif:
209  %tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
210  %ext = sext i1 %tmp4 to i32
211  store i32 %ext, i32 addrspace(1)* %out
212  ret void
213}
214
215declare i32 @llvm.amdgcn.workitem.id.x() #0
216
217attributes #0 = { readnone }
218