1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
3;
4; Most SALU instructions ignore control flow, so we need to make sure
5; they don't overwrite values from other blocks.
6
7; If the branch decision is made based on a value in an SGPR then all
8; threads will execute the same code paths, so we don't need to worry
9; about instructions in different blocks overwriting each other.
10
11define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
12; SI-LABEL: sgpr_if_else_salu_br:
13; SI:       ; %bb.0: ; %entry
14; SI-NEXT:	s_load_dwordx4 s[4:7], s[0:1], 0xb
15; SI-NEXT:	s_load_dword s2, s[0:1], 0xf
16; SI-NEXT:	s_load_dwordx2 s[0:1], s[0:1], 0x9
17; SI-NEXT:	s_waitcnt lgkmcnt(0)
18; SI-NEXT:	s_cmp_lg_u32 s4, 0
19; SI-NEXT:	s_cbranch_scc0 BB0_2
20; SI-NEXT:; %bb.1:                                ; %else
21; SI-NEXT:	s_add_i32 s2, s7, s2
22; SI-NEXT:	s_mov_b64 s[8:9], 0
23; SI-NEXT:	s_andn2_b64 vcc, exec, s[8:9]
24; SI-NEXT:	s_cbranch_vccz BB0_3
25; SI-NEXT:	s_branch BB0_4
26; SI-NEXT:BB0_2:
27; SI-NEXT:	s_mov_b64 s[8:9], -1
28; SI-NEXT:                                        ; implicit-def: $sgpr2
29; SI-NEXT:	s_andn2_b64 vcc, exec, s[8:9]
30; SI-NEXT:	s_cbranch_vccnz BB0_4
31; SI-NEXT:BB0_3:                                  ; %if
32; SI-NEXT:	s_sub_i32 s2, s5, s6
33; SI-NEXT:BB0_4:                                  ; %endif
34; SI-NEXT:	s_add_i32 s4, s2, s4
35; SI-NEXT:	s_mov_b32 s3, 0xf000
36; SI-NEXT:	s_mov_b32 s2, -1
37; SI-NEXT:	v_mov_b32_e32 v0, s4
38; SI-NEXT:	buffer_store_dword v0, off, s[0:3], 0
39; SI-NEXT:	s_endpgm
40entry:
41  %0 = icmp eq i32 %a, 0
42  br i1 %0, label %if, label %else
43
44if:
45  %1 = sub i32 %b, %c
46  br label %endif
47
48else:
49  %2 = add i32 %d, %e
50  br label %endif
51
52endif:
53  %3 = phi i32 [%1, %if], [%2, %else]
54  %4 = add i32 %3, %a
55  store i32 %4, i32 addrspace(1)* %out
56  ret void
57}
58
59define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
60; SI-LABEL: sgpr_if_else_salu_br_opt:
61; SI:       ; %bb.0: ; %entry
62; SI-NEXT:    s_load_dword s2, s[0:1], 0x13
63; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
64; SI-NEXT:    s_waitcnt lgkmcnt(0)
65; SI-NEXT:    s_cmp_lg_u32 s2, 0
66; SI-NEXT:    s_cbranch_scc0 BB1_2
67; SI-NEXT:  ; %bb.1: ; %else
68; SI-NEXT:    s_load_dword s3, s[0:1], 0x2e
69; SI-NEXT:    s_load_dword s6, s[0:1], 0x37
70; SI-NEXT:    s_waitcnt lgkmcnt(0)
71; SI-NEXT:    s_add_i32 s3, s3, s6
72; SI-NEXT:    s_mov_b64 s[6:7], 0
73; SI-NEXT:    s_andn2_b64 vcc, exec, s[6:7]
74; SI-NEXT:    s_cbranch_vccz BB1_3
75; SI-NEXT:    s_branch BB1_4
76; SI-NEXT:  BB1_2:
77; SI-NEXT:    s_mov_b64 s[6:7], -1
78; SI-NEXT:    ; implicit-def: $sgpr3
79; SI-NEXT:    s_andn2_b64 vcc, exec, s[6:7]
80; SI-NEXT:    s_cbranch_vccnz BB1_4
81; SI-NEXT:  BB1_3: ; %if
82; SI-NEXT:    s_load_dword s3, s[0:1], 0x1c
83; SI-NEXT:    s_load_dword s0, s[0:1], 0x25
84; SI-NEXT:    s_waitcnt lgkmcnt(0)
85; SI-NEXT:    s_add_i32 s3, s3, s0
86; SI-NEXT:  BB1_4: ; %endif
87; SI-NEXT:    s_add_i32 s0, s3, s2
88; SI-NEXT:    s_mov_b32 s7, 0xf000
89; SI-NEXT:    s_mov_b32 s6, -1
90; SI-NEXT:    v_mov_b32_e32 v0, s0
91; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
92; SI-NEXT:    s_endpgm
93entry:
94  %cmp0 = icmp eq i32 %a, 0
95  br i1 %cmp0, label %if, label %else
96
97if:
98  %add0 = add i32 %b, %c
99  br label %endif
100
101else:
102  %add1 = add i32 %d, %e
103  br label %endif
104
105endif:
106  %phi = phi i32 [%add0, %if], [%add1, %else]
107  %add2 = add i32 %phi, %a
108  store i32 %add2, i32 addrspace(1)* %out
109  ret void
110}
111
112; The two S_ADD instructions should write to different registers, since
113; different threads will take different control flow paths.
114define amdgpu_kernel void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
115; SI-LABEL: sgpr_if_else_valu_br:
116; SI:       ; %bb.0: ; %entry
117; SI-NEXT:    v_cvt_f32_u32_e32 v0, v0
118; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
119; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xc
120; SI-NEXT:    ; implicit-def: $sgpr6
121; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v0
122; SI-NEXT:    s_and_saveexec_b64 s[8:9], vcc
123; SI-NEXT:    s_xor_b64 s[8:9], exec, s[8:9]
124; SI-NEXT:    s_cbranch_execz BB2_2
125; SI-NEXT:  ; %bb.1: ; %else
126; SI-NEXT:    s_waitcnt lgkmcnt(0)
127; SI-NEXT:    s_add_i32 s6, s2, s3
128; SI-NEXT:  BB2_2: ; %Flow
129; SI-NEXT:    s_waitcnt lgkmcnt(0)
130; SI-NEXT:    s_or_saveexec_b64 s[2:3], s[8:9]
131; SI-NEXT:    v_mov_b32_e32 v0, s6
132; SI-NEXT:    s_xor_b64 exec, exec, s[2:3]
133; SI-NEXT:  ; %bb.3: ; %if
134; SI-NEXT:    s_add_i32 s0, s0, s1
135; SI-NEXT:    v_mov_b32_e32 v0, s0
136; SI-NEXT:  ; %bb.4: ; %endif
137; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
138; SI-NEXT:    s_mov_b32 s7, 0xf000
139; SI-NEXT:    s_mov_b32 s6, -1
140; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
141; SI-NEXT:    s_endpgm
142entry:
143  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
144  %tid_f = uitofp i32 %tid to float
145  %tmp1 = fcmp ueq float %tid_f, 0.0
146  br i1 %tmp1, label %if, label %else
147
148if:
149  %tmp2 = add i32 %b, %c
150  br label %endif
151
152else:
153  %tmp3 = add i32 %d, %e
154  br label %endif
155
156endif:
157  %tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
158  store i32 %tmp4, i32 addrspace(1)* %out
159  ret void
160}
161
162define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
163; SI-LABEL: sgpr_if_else_valu_cmp_phi_br:
164; SI:       ; %bb.0: ; %entry
165; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
166; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
167; SI-NEXT:    s_mov_b32 s10, 0
168; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
169; SI-NEXT:    ; implicit-def: $sgpr0_sgpr1
170; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
171; SI-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
172; SI-NEXT:    s_cbranch_execz BB3_2
173; SI-NEXT:  ; %bb.1: ; %else
174; SI-NEXT:    s_mov_b32 s11, 0xf000
175; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
176; SI-NEXT:    v_mov_b32_e32 v2, 0
177; SI-NEXT:    s_waitcnt lgkmcnt(0)
178; SI-NEXT:    buffer_load_dword v1, v[1:2], s[8:11], 0 addr64
179; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
180; SI-NEXT:    s_waitcnt vmcnt(0)
181; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v1
182; SI-NEXT:    s_and_b64 s[8:9], vcc, exec
183; SI-NEXT:    s_or_b64 s[0:1], s[0:1], s[8:9]
184; SI-NEXT:  BB3_2: ; %Flow
185; SI-NEXT:    s_or_saveexec_b64 s[2:3], s[2:3]
186; SI-NEXT:    s_xor_b64 exec, exec, s[2:3]
187; SI-NEXT:    s_cbranch_execz BB3_4
188; SI-NEXT:  ; %bb.3: ; %if
189; SI-NEXT:    s_mov_b32 s11, 0xf000
190; SI-NEXT:    s_mov_b32 s10, 0
191; SI-NEXT:    s_waitcnt lgkmcnt(0)
192; SI-NEXT:    s_mov_b64 s[8:9], s[6:7]
193; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
194; SI-NEXT:    v_mov_b32_e32 v1, 0
195; SI-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
196; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
197; SI-NEXT:    s_waitcnt vmcnt(0)
198; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
199; SI-NEXT:    s_and_b64 s[6:7], vcc, exec
200; SI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
201; SI-NEXT:  BB3_4: ; %endif
202; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
203; SI-NEXT:    s_waitcnt lgkmcnt(0)
204; SI-NEXT:    s_mov_b32 s7, 0xf000
205; SI-NEXT:    s_mov_b32 s6, -1
206; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[0:1]
207; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
208; SI-NEXT:    s_endpgm
209entry:
210  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
211  %tmp1 = icmp eq i32 %tid, 0
212  br i1 %tmp1, label %if, label %else
213
214if:
215  %gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
216  %a.val = load i32, i32 addrspace(1)* %gep.if
217  %cmp.if = icmp eq i32 %a.val, 0
218  br label %endif
219
220else:
221  %gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
222  %b.val = load i32, i32 addrspace(1)* %gep.else
223  %cmp.else = icmp slt i32 %b.val, 0
224  br label %endif
225
226endif:
227  %tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
228  %ext = sext i1 %tmp4 to i32
229  store i32 %ext, i32 addrspace(1)* %out
230  ret void
231}
232
233declare i32 @llvm.amdgcn.workitem.id.x() #0
234
235attributes #0 = { readnone }
236