1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5; FIXME: i16 promotion pass ruins the scalar cases when legal. 6 7; FUNC-LABEL: {{^}}sext_in_reg_i1_i32: 8; GCN: s_load_dword [[ARG:s[0-9]+]], 9; GCN: s_bfe_i32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000 10; GCN: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]] 11; GCN: buffer_store_dword [[EXTRACT]], 12 13; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] 14; EG: LSHR * [[ADDR]] 15; EG: BFE_INT * [[RES]], {{.*}}, 0.0, 1 16define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) #0 { 17 %shl = shl i32 %in, 31 18 %sext = ashr i32 %shl, 31 19 store i32 %sext, i32 addrspace(1)* %out 20 ret void 21} 22 23; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32: 24; GCN: s_add_i32 [[VAL:s[0-9]+]], 25; GCN: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]] 26; GCN: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] 27; GCN: buffer_store_dword [[VEXTRACT]], 28 29; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] 30; EG: ADD_INT 31; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal 32; EG-NEXT: LSHR * [[ADDR]] 33define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { 34 %c = add i32 %a, %b ; add to prevent folding into extload 35 %shl = shl i32 %c, 24 36 %ashr = ashr i32 %shl, 24 37 store i32 %ashr, i32 addrspace(1)* %out, align 4 38 ret void 39} 40 41; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i32: 42; GCN: s_add_i32 [[VAL:s[0-9]+]], 43; GCN: s_sext_i32_i16 [[EXTRACT:s[0-9]+]], [[VAL]] 44; GCN: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] 45; GCN: buffer_store_dword [[VEXTRACT]], 46 47; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] 48; EG: ADD_INT 49; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal 50; EG-NEXT: LSHR * [[ADDR]] 51define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { 52 %c = add i32 %a, %b ; add to prevent folding into extload 53 %shl = shl i32 %c, 16 54 %ashr = ashr i32 %shl, 16 55 store i32 %ashr, i32 addrspace(1)* %out, align 4 56 ret void 57} 58 59; FUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i32: 60; GCN: s_add_i32 [[VAL:s[0-9]+]], 61; GCN: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]] 62; GCN: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] 63; GCN: buffer_store_dword [[VEXTRACT]], 64 65; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] 66; EG: ADD_INT 67; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal 68; EG-NEXT: LSHR * [[ADDR]] 69define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) #0 { 70 %c = add <1 x i32> %a, %b ; add to prevent folding into extload 71 %shl = shl <1 x i32> %c, <i32 24> 72 %ashr = ashr <1 x i32> %shl, <i32 24> 73 store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4 74 ret void 75} 76 77; FUNC-LABEL: {{^}}sext_in_reg_i1_to_i64: 78; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] 79; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x10000 80; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] 81; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] 82; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 83define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { 84 %c = shl i64 %a, %b 85 %shl = shl i64 %c, 63 86 %ashr = ashr i64 %shl, 63 87 store i64 %ashr, i64 addrspace(1)* %out, align 8 88 ret void 89} 90 91; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i64: 92; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] 93; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x80000 94; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] 95; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] 96; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 97define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { 98 %c = shl i64 %a, %b 99 %shl = shl i64 %c, 56 100 %ashr = ashr i64 %shl, 56 101 store i64 %ashr, i64 addrspace(1)* %out, align 8 102 ret void 103} 104 105; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i64: 106; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] 107; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x100000 108; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] 109; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] 110; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 111 112define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { 113 %c = shl i64 %a, %b 114 %shl = shl i64 %c, 48 115 %ashr = ashr i64 %shl, 48 116 store i64 %ashr, i64 addrspace(1)* %out, align 8 117 ret void 118} 119 120; FUNC-LABEL: {{^}}sext_in_reg_i32_to_i64: 121; GCN: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] 122; GCN-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x200000 123; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] 124; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] 125; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 126define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 { 127 %c = shl i64 %a, %b 128 %shl = shl i64 %c, 32 129 %ashr = ashr i64 %shl, 32 130 store i64 %ashr, i64 addrspace(1)* %out, align 8 131 ret void 132} 133 134; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments. 135; XFUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i64: 136; XGCN: s_bfe_i32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288 137; XGCN: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31 138; XGCN: buffer_store_dword 139; XEG: BFE_INT 140; XEG: ASHR 141; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) #0 { 142; %c = add <1 x i64> %a, %b 143; %shl = shl <1 x i64> %c, <i64 56> 144; %ashr = ashr <1 x i64> %shl, <i64 56> 145; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8 146; ret void 147; } 148 149; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64: 150; SI: buffer_load_dwordx2 151; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 152 153; VI: flat_load_dwordx2 154; VI: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 155 156; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1 157; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] 158 159; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} 160; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} 161define void @v_sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { 162 %tid = call i32 @llvm.r600.read.tidig.x() 163 %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 164 %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 165 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 166 %a = load i64, i64 addrspace(1)* %a.gep, align 8 167 %b = load i64, i64 addrspace(1)* %b.gep, align 8 168 169 %c = shl i64 %a, %b 170 %shl = shl i64 %c, 63 171 %ashr = ashr i64 %shl, 63 172 store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 173 ret void 174} 175 176; FUNC-LABEL: {{^}}v_sext_in_reg_i8_to_i64: 177; SI: buffer_load_dwordx2 178; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 179 180; VI: flat_load_dwordx2 181; VI: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 182 183; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 8 184; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] 185 186; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} 187; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} 188define void @v_sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { 189 %tid = call i32 @llvm.r600.read.tidig.x() 190 %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 191 %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 192 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 193 %a = load i64, i64 addrspace(1)* %a.gep, align 8 194 %b = load i64, i64 addrspace(1)* %b.gep, align 8 195 196 %c = shl i64 %a, %b 197 %shl = shl i64 %c, 56 198 %ashr = ashr i64 %shl, 56 199 store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 200 ret void 201} 202 203; FUNC-LABEL: {{^}}v_sext_in_reg_i16_to_i64: 204; SI: buffer_load_dwordx2 205; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 206 207; VI: flat_load_dwordx2 208; VI: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 209 210; GCN: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 16 211; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] 212 213; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} 214; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} 215define void @v_sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { 216 %tid = call i32 @llvm.r600.read.tidig.x() 217 %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 218 %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 219 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 220 %a = load i64, i64 addrspace(1)* %a.gep, align 8 221 %b = load i64, i64 addrspace(1)* %b.gep, align 8 222 223 %c = shl i64 %a, %b 224 %shl = shl i64 %c, 48 225 %ashr = ashr i64 %shl, 48 226 store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 227 ret void 228} 229 230; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64: 231; SI: buffer_load_dwordx2 232; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 233 234; VI: flat_load_dwordx2 235; VI: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 236 237; GCN: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]] 238; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[SHR]]{{\]}} 239define void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) #0 { 240 %tid = call i32 @llvm.r600.read.tidig.x() 241 %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 242 %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 243 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 244 %a = load i64, i64 addrspace(1)* %a.gep, align 8 245 %b = load i64, i64 addrspace(1)* %b.gep, align 8 246 247 %c = shl i64 %a, %b 248 %shl = shl i64 %c, 32 249 %ashr = ashr i64 %shl, 32 250 store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 251 ret void 252} 253 254; FUNC-LABEL: {{^}}sext_in_reg_i1_in_i32_other_amount: 255; GCN-NOT: s_lshl 256; GCN-NOT: s_ashr 257; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001 258 259; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] 260; EG-NOT: BFE 261; EG: ADD_INT 262; EG: LSHL 263; EG: ASHR [[RES]] 264; EG: LSHR {{\*?}} [[ADDR]] 265define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { 266 %c = add i32 %a, %b 267 %x = shl i32 %c, 6 268 %y = ashr i32 %x, 7 269 store i32 %y, i32 addrspace(1)* %out 270 ret void 271} 272 273; FUNC-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount: 274; GCN-NOT: s_lshl 275; GCN-NOT: s_ashr 276; GCN-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001 277; GCN-DAG: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x190001 278; GCN: s_endpgm 279 280; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] 281; EG-NOT: BFE 282; EG: ADD_INT 283; EG: LSHL 284; EG: ASHR [[RES]] 285; EG: LSHL 286; EG: ASHR [[RES]] 287; EG: LSHR {{\*?}} [[ADDR]] 288define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 { 289 %c = add <2 x i32> %a, %b 290 %x = shl <2 x i32> %c, <i32 6, i32 6> 291 %y = ashr <2 x i32> %x, <i32 7, i32 7> 292 store <2 x i32> %y, <2 x i32> addrspace(1)* %out 293 ret void 294} 295 296 297; FUNC-LABEL: {{^}}sext_in_reg_v2i1_to_v2i32: 298; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 299; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 300; GCN: buffer_store_dwordx2 301 302; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] 303; EG: BFE_INT [[RES]] 304; EG: BFE_INT [[RES]] 305; EG: LSHR {{\*?}} [[ADDR]] 306define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 { 307 %c = add <2 x i32> %a, %b ; add to prevent folding into extload 308 %shl = shl <2 x i32> %c, <i32 31, i32 31> 309 %ashr = ashr <2 x i32> %shl, <i32 31, i32 31> 310 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8 311 ret void 312} 313 314; FUNC-LABEL: {{^}}sext_in_reg_v4i1_to_v4i32: 315; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 316; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 317; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 318; GCN: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 319; GCN: buffer_store_dwordx4 320 321; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] 322; EG: BFE_INT [[RES]] 323; EG: BFE_INT [[RES]] 324; EG: BFE_INT [[RES]] 325; EG: BFE_INT [[RES]] 326; EG: LSHR {{\*?}} [[ADDR]] 327define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) #0 { 328 %c = add <4 x i32> %a, %b ; add to prevent folding into extload 329 %shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31> 330 %ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31> 331 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8 332 ret void 333} 334 335; FUNC-LABEL: {{^}}sext_in_reg_v2i8_to_v2i32: 336; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} 337; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} 338; GCN: buffer_store_dwordx2 339 340; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] 341; EG: BFE_INT [[RES]] 342; EG: BFE_INT [[RES]] 343; EG: LSHR {{\*?}} [[ADDR]] 344define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 { 345 %c = add <2 x i32> %a, %b ; add to prevent folding into extload 346 %shl = shl <2 x i32> %c, <i32 24, i32 24> 347 %ashr = ashr <2 x i32> %shl, <i32 24, i32 24> 348 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8 349 ret void 350} 351 352; FUNC-LABEL: {{^}}sext_in_reg_v4i8_to_v4i32: 353; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} 354; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} 355; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} 356; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} 357; GCN: buffer_store_dwordx4 358 359; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] 360; EG: BFE_INT [[RES]] 361; EG: BFE_INT [[RES]] 362; EG: BFE_INT [[RES]] 363; EG: BFE_INT [[RES]] 364; EG: LSHR {{\*?}} [[ADDR]] 365define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) #0 { 366 %c = add <4 x i32> %a, %b ; add to prevent folding into extload 367 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24> 368 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24> 369 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8 370 ret void 371} 372 373; FUNC-LABEL: {{^}}sext_in_reg_v2i16_to_v2i32: 374; GCN: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}} 375; GCN: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}} 376; GCN: buffer_store_dwordx2 377 378; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] 379; EG: BFE_INT [[RES]] 380; EG: BFE_INT [[RES]] 381; EG: LSHR {{\*?}} [[ADDR]] 382define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 { 383 %c = add <2 x i32> %a, %b ; add to prevent folding into extload 384 %shl = shl <2 x i32> %c, <i32 16, i32 16> 385 %ashr = ashr <2 x i32> %shl, <i32 16, i32 16> 386 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8 387 ret void 388} 389 390; FUNC-LABEL: {{^}}testcase: 391define void @testcase(i8 addrspace(1)* %out, i8 %a) #0 { 392 %and_a_1 = and i8 %a, 1 393 %cmp_eq = icmp eq i8 %and_a_1, 0 394 %cmp_slt = icmp slt i8 %a, 0 395 %sel0 = select i1 %cmp_slt, i8 0, i8 %a 396 %sel1 = select i1 %cmp_eq, i8 0, i8 %a 397 %xor = xor i8 %sel0, %sel1 398 store i8 %xor, i8 addrspace(1)* %out 399 ret void 400} 401 402; FUNC-LABEL: {{^}}testcase_3: 403define void @testcase_3(i8 addrspace(1)* %out, i8 %a) #0 { 404 %and_a_1 = and i8 %a, 1 405 %cmp_eq = icmp eq i8 %and_a_1, 0 406 %cmp_slt = icmp slt i8 %a, 0 407 %sel0 = select i1 %cmp_slt, i8 0, i8 %a 408 %sel1 = select i1 %cmp_eq, i8 0, i8 %a 409 %xor = xor i8 %sel0, %sel1 410 store i8 %xor, i8 addrspace(1)* %out 411 ret void 412} 413 414; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i8_to_v4i32: 415; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 416; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 417; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 418; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 419define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) #0 { 420 %loada = load <4 x i32>, <4 x i32> addrspace(1)* %a, align 16 421 %loadb = load <4 x i32>, <4 x i32> addrspace(1)* %b, align 16 422 %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload 423 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24> 424 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24> 425 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8 426 ret void 427} 428 429; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i16_to_v4i32: 430; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 431; GCN: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 432define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) #0 { 433 %loada = load <4 x i32>, <4 x i32> addrspace(1)* %a, align 16 434 %loadb = load <4 x i32>, <4 x i32> addrspace(1)* %b, align 16 435 %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload 436 %shl = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16> 437 %ashr = ashr <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16> 438 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8 439 ret void 440} 441 442; FUNC-LABEL: {{^}}sext_in_reg_to_illegal_type: 443; GCN: buffer_load_sbyte 444; GCN: v_max_i32 445; GCN-NOT: bfe 446; GCN: buffer_store_short 447define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) #0 { 448 %tmp5 = load i8, i8 addrspace(1)* %src, align 1 449 %tmp2 = sext i8 %tmp5 to i32 450 %tmp2.5 = icmp sgt i32 %tmp2, 0 451 %tmp3 = select i1 %tmp2.5, i32 %tmp2, i32 0 452 %tmp4 = trunc i32 %tmp3 to i8 453 %tmp6 = sext i8 %tmp4 to i16 454 store i16 %tmp6, i16 addrspace(1)* %out, align 2 455 ret void 456} 457 458declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone 459 460; FUNC-LABEL: {{^}}bfe_0_width: 461; GCN-NOT: {{[^@]}}bfe 462; GCN: s_endpgm 463define void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { 464 %load = load i32, i32 addrspace(1)* %ptr, align 4 465 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 8, i32 0) nounwind readnone 466 store i32 %bfe, i32 addrspace(1)* %out, align 4 467 ret void 468} 469 470; FUNC-LABEL: {{^}}bfe_8_bfe_8: 471; GCN: v_bfe_i32 472; GCN-NOT: {{[^@]}}bfe 473; GCN: s_endpgm 474define void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { 475 %load = load i32, i32 addrspace(1)* %ptr, align 4 476 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone 477 %bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 8) nounwind readnone 478 store i32 %bfe1, i32 addrspace(1)* %out, align 4 479 ret void 480} 481 482; FUNC-LABEL: {{^}}bfe_8_bfe_16: 483; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 484; GCN: s_endpgm 485define void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { 486 %load = load i32, i32 addrspace(1)* %ptr, align 4 487 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone 488 %bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 16) nounwind readnone 489 store i32 %bfe1, i32 addrspace(1)* %out, align 4 490 ret void 491} 492 493; This really should be folded into 1 494; FUNC-LABEL: {{^}}bfe_16_bfe_8: 495; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 496; GCN-NOT: {{[^@]}}bfe 497; GCN: s_endpgm 498define void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { 499 %load = load i32, i32 addrspace(1)* %ptr, align 4 500 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 16) nounwind readnone 501 %bfe1 = call i32 @llvm.AMDGPU.bfe.i32(i32 %bfe0, i32 0, i32 8) nounwind readnone 502 store i32 %bfe1, i32 addrspace(1)* %out, align 4 503 ret void 504} 505 506; Make sure there isn't a redundant BFE 507; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe: 508; GCN: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}} 509; GCN-NOT: {{[^@]}}bfe 510; GCN: s_endpgm 511define void @sext_in_reg_i8_to_i32_bfe(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { 512 %c = add i32 %a, %b ; add to prevent folding into extload 513 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %c, i32 0, i32 8) nounwind readnone 514 %shl = shl i32 %bfe, 24 515 %ashr = ashr i32 %shl, 24 516 store i32 %ashr, i32 addrspace(1)* %out, align 4 517 ret void 518} 519 520; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe_wrong: 521define void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { 522 %c = add i32 %a, %b ; add to prevent folding into extload 523 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %c, i32 8, i32 0) nounwind readnone 524 %shl = shl i32 %bfe, 24 525 %ashr = ashr i32 %shl, 24 526 store i32 %ashr, i32 addrspace(1)* %out, align 4 527 ret void 528} 529 530; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe: 531; GCN: buffer_load_sbyte 532; GCN-NOT: {{[^@]}}bfe 533; GCN: s_endpgm 534define void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 { 535 %load = load i8, i8 addrspace(1)* %ptr, align 1 536 %sext = sext i8 %load to i32 537 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %sext, i32 0, i32 8) nounwind readnone 538 %shl = shl i32 %bfe, 24 539 %ashr = ashr i32 %shl, 24 540 store i32 %ashr, i32 addrspace(1)* %out, align 4 541 ret void 542} 543 544; GCN: .text 545; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe_0:{{.*$}} 546; GCN-NOT: {{[^@]}}bfe 547; GCN: s_endpgm 548define void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) #0 { 549 %load = load i8, i8 addrspace(1)* %ptr, align 1 550 %sext = sext i8 %load to i32 551 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %sext, i32 8, i32 0) nounwind readnone 552 %shl = shl i32 %bfe, 24 553 %ashr = ashr i32 %shl, 24 554 store i32 %ashr, i32 addrspace(1)* %out, align 4 555 ret void 556} 557 558; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_0: 559; GCN-NOT: shr 560; GCN-NOT: shl 561; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 562; GCN: s_endpgm 563define void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 564 %x = load i32, i32 addrspace(1)* %in, align 4 565 %shl = shl i32 %x, 31 566 %shr = ashr i32 %shl, 31 567 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 0, i32 1) 568 store i32 %bfe, i32 addrspace(1)* %out, align 4 569 ret void 570} 571 572; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_1: 573; GCN: buffer_load_dword 574; GCN-NOT: shl 575; GCN-NOT: shr 576; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1 577; GCN: s_endpgm 578define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 579 %x = load i32, i32 addrspace(1)* %in, align 4 580 %shl = shl i32 %x, 30 581 %shr = ashr i32 %shl, 30 582 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 1, i32 1) 583 store i32 %bfe, i32 addrspace(1)* %out, align 4 584 ret void 585} 586 587; FUNC-LABEL: {{^}}sext_in_reg_i2_bfe_offset_1: 588; GCN: buffer_load_dword 589; GCN-NOT: v_lshl 590; GCN-NOT: v_ashr 591; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 2 592; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2 593; GCN: s_endpgm 594define void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 595 %x = load i32, i32 addrspace(1)* %in, align 4 596 %shl = shl i32 %x, 30 597 %shr = ashr i32 %shl, 30 598 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shr, i32 1, i32 2) 599 store i32 %bfe, i32 addrspace(1)* %out, align 4 600 ret void 601} 602 603; Make sure we propagate the VALUness to users of a moved scalar BFE. 604 605; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64_move_use: 606; SI: buffer_load_dwordx2 607; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 608 609; VI: flat_load_dwordx2 610; VI: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} 611 612; GCN-DAG: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1 613; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] 614; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]] 615; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[HI]] 616; SI: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} 617; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} 618define void @v_sext_in_reg_i1_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 { 619 %tid = call i32 @llvm.r600.read.tidig.x() 620 %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 621 %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 622 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 623 %a = load i64, i64 addrspace(1)* %a.gep, align 8 624 %b = load i64, i64 addrspace(1)* %b.gep, align 8 625 626 %c = shl i64 %a, %b 627 %shl = shl i64 %c, 63 628 %ashr = ashr i64 %shl, 63 629 630 %and = and i64 %ashr, %s.val 631 store i64 %and, i64 addrspace(1)* %out.gep, align 8 632 ret void 633} 634 635; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64_move_use: 636; SI: buffer_load_dwordx2 637; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 638 639; VI: flat_load_dwordx2 640; VI: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 641 642; GCN-DAG: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]] 643; GCN-DAG: v_and_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, v[[LO]] 644; GCN-DAG: v_and_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[SHR]] 645 646; SI: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} 647; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}} 648define void @v_sext_in_reg_i32_to_i64_move_use(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 %s.val) #0 { 649 %tid = call i32 @llvm.r600.read.tidig.x() 650 %a.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 651 %b.gep = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid 652 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 653 %a = load i64, i64 addrspace(1)* %a.gep, align 8 654 %b = load i64, i64 addrspace(1)* %b.gep, align 8 655 656 %c = shl i64 %a, %b 657 %shl = shl i64 %c, 32 658 %ashr = ashr i64 %shl, 32 659 %and = and i64 %ashr, %s.val 660 store i64 %and, i64 addrspace(1)* %out.gep, align 8 661 ret void 662} 663 664; FUNC-LABEL: {{^}}s_sext_in_reg_i1_i16: 665; GCN: s_load_dword [[VAL:s[0-9]+]] 666 667; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x10000 668; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]] 669; SI: buffer_store_short [[VBFE]] 670 671; VI: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15 672; VI: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}} 673; VI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15 674define void @s_sext_in_reg_i1_i16(i16 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { 675 %ld = load i32, i32 addrspace(2)* %ptr 676 %in = trunc i32 %ld to i16 677 %shl = shl i16 %in, 15 678 %sext = ashr i16 %shl, 15 679 store i16 %sext, i16 addrspace(1)* %out 680 ret void 681} 682 683; FUNC-LABEL: {{^}}s_sext_in_reg_i2_i16: 684; GCN: s_load_dword [[VAL:s[0-9]+]] 685 686; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000 687; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]] 688; SI: buffer_store_short [[VBFE]] 689 690; VI: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14 691; VI: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}} 692; VI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14 693define void @s_sext_in_reg_i2_i16(i16 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { 694 %ld = load i32, i32 addrspace(2)* %ptr 695 %in = trunc i32 %ld to i16 696 %shl = shl i16 %in, 14 697 %sext = ashr i16 %shl, 14 698 store i16 %sext, i16 addrspace(1)* %out 699 ret void 700} 701 702; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16: 703; GCN: {{buffer|flat}}_load_ushort [[VAL:v[0-9]+]] 704; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[VAL]], 0, 1{{$}} 705 706; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]] 707define void @v_sext_in_reg_i1_i16(i16 addrspace(3)* %out, i16 addrspace(1)* %ptr) #0 { 708 %tid = call i32 @llvm.r600.read.tidig.x() 709 %gep = getelementptr i16, i16 addrspace(1)* %ptr, i32 %tid 710 %out.gep = getelementptr i16, i16 addrspace(3)* %out, i32 %tid 711 712 %in = load i16, i16 addrspace(1)* %gep 713 %shl = shl i16 %in, 15 714 %sext = ashr i16 %shl, 15 715 store i16 %sext, i16 addrspace(3)* %out.gep 716 ret void 717} 718 719; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16_nonload: 720; GCN: {{buffer|flat}}_load_ushort [[VAL0:v[0-9]+]] 721; GCN: {{buffer|flat}}_load_ushort [[VAL1:v[0-9]+]] 722 723; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], [[VAL1]], [[VAL0]] 724; VI: v_lshlrev_b16_e32 [[REG:v[0-9]+]], [[VAL1]], [[VAL0]] 725 726; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[REG]], 0, 1{{$}} 727; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]] 728define void @v_sext_in_reg_i1_i16_nonload(i16 addrspace(3)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr, i16 %s.val) nounwind { 729 %tid = call i32 @llvm.r600.read.tidig.x() 730 %a.gep = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid 731 %b.gep = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid 732 %out.gep = getelementptr i16, i16 addrspace(3)* %out, i32 %tid 733 %a = load volatile i16, i16 addrspace(1)* %a.gep, align 2 734 %b = load volatile i16, i16 addrspace(1)* %b.gep, align 2 735 736 %c = shl i16 %a, %b 737 %shl = shl i16 %c, 15 738 %ashr = ashr i16 %shl, 15 739 740 store i16 %ashr, i16 addrspace(3)* %out.gep, align 2 741 ret void 742} 743 744; FUNC-LABEL: {{^}}s_sext_in_reg_i2_i16_arg: 745; GCN: s_load_dword [[VAL:s[0-9]+]] 746 747; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000 748; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]] 749; SI: buffer_store_short [[VBFE]] 750 751; VI: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14{{$}} 752; VI: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}} 753; VI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14{{$}} 754define void @s_sext_in_reg_i2_i16_arg(i16 addrspace(1)* %out, i16 %in) #0 { 755 %shl = shl i16 %in, 14 756 %sext = ashr i16 %shl, 14 757 store i16 %sext, i16 addrspace(1)* %out 758 ret void 759} 760 761; FUNC-LABEL: {{^}}s_sext_in_reg_i8_i16_arg: 762; GCN: s_load_dword [[VAL:s[0-9]+]] 763 764; SI: s_sext_i32_i8 [[SSEXT:s[0-9]+]], [[VAL]] 765; SI: v_mov_b32_e32 [[VSEXT:v[0-9]+]], [[SSEXT]] 766; SI: buffer_store_short [[VBFE]] 767 768; VI: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 8{{$}} 769; VI: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}} 770; VI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 8{{$}} 771define void @s_sext_in_reg_i8_i16_arg(i16 addrspace(1)* %out, i16 %in) #0 { 772 %shl = shl i16 %in, 8 773 %sext = ashr i16 %shl, 8 774 store i16 %sext, i16 addrspace(1)* %out 775 ret void 776} 777 778; FUNC-LABEL: {{^}}s_sext_in_reg_i15_i16_arg: 779; GCN: s_load_dword [[VAL:s[0-9]+]] 780 781; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0xf0000 782; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]] 783; SI: buffer_store_short [[VBFE]] 784 785; VI: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1{{$}} 786; VI: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}} 787; VI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1{{$}} 788define void @s_sext_in_reg_i15_i16_arg(i16 addrspace(1)* %out, i16 %in) #0 { 789 %shl = shl i16 %in, 1 790 %sext = ashr i16 %shl, 1 791 store i16 %sext, i16 addrspace(1)* %out 792 ret void 793} 794 795declare i32 @llvm.r600.read.tidig.x() #1 796 797attributes #0 = { nounwind } 798attributes #1 = { nounwind readnone } 799