1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1030 < %s | FileCheck %s
3
4; SelectionDAG generates a setcc node with multiple uses:
5;
6;  t23: i1 = setcc t3, Constant:i32<0>, setne:ch
7;        t17: i32,i1 = subcarry Constant:i32<1>, Constant:i32<0>, t23
8;      t25: i32 = select t23, t17, Constant:i32<0>
9
10define amdgpu_cs void @main() {
11; CHECK-LABEL: main:
12; CHECK:       ; %bb.0: ; %bb
13; CHECK-NEXT:    v_mov_b32_e32 v0, 0
14; CHECK-NEXT:    ds_read_b32 v1, v0
15; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
16; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
17; CHECK-NEXT:    s_cmpk_lg_u32 vcc_lo, 0x0
18; CHECK-NEXT:    s_subb_u32 s0, 1, 0
19; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, s0, vcc_lo
20; CHECK-NEXT:  .LBB0_1: ; %bb1
21; CHECK-NEXT:    ; =>This Loop Header: Depth=1
22; CHECK-NEXT:    ; Child Loop BB0_2 Depth 2
23; CHECK-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
24; CHECK-NEXT:  .LBB0_2: ; %bb3
25; CHECK-NEXT:    ; Parent Loop BB0_1 Depth=1
26; CHECK-NEXT:    ; => This Inner Loop Header: Depth=2
27; CHECK-NEXT:    v_mov_b32_e32 v0, v1
28; CHECK-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
29; CHECK-NEXT:    s_cbranch_vccz .LBB0_2
30; CHECK-NEXT:    s_branch .LBB0_1
31bb:
32  %i = load i32, i32 addrspace(3)* null, align 16
33  br label %bb1
34
35bb1:
36  %i2 = phi i32 [ 0, %bb ], [ %i9, %bb5 ]
37  br label %bb3
38
39bb3:
40  %i4 = icmp eq i32 %i2, 0
41  br i1 %i4, label %bb5, label %bb3
42
43bb5:
44  %i6 = icmp ult i32 0, %i
45  %i7 = sext i1 %i6 to i32
46  %i8 = add i32 %i7, 1
47  %i9 = and i32 %i8, %i7
48  br label %bb1
49}
50