1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4; GCN-LABEL: {{^}}select_f16: 5; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 6; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 7; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] 8; GCN: buffer_load_ushort v[[D_F16:[0-9]+]] 9; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 10; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 11; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]] 12; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]] 13; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]] 14; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]] 15; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 16; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] 17; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc 18; GCN: buffer_store_short v[[R_F16]] 19; GCN: s_endpgm 20define amdgpu_kernel void @select_f16( 21 half addrspace(1)* %r, 22 half addrspace(1)* %a, 23 half addrspace(1)* %b, 24 half addrspace(1)* %c, 25 half addrspace(1)* %d) { 26entry: 27 %a.val = load half, half addrspace(1)* %a 28 %b.val = load half, half addrspace(1)* %b 29 %c.val = load half, half addrspace(1)* %c 30 %d.val = load half, half addrspace(1)* %d 31 %fcmp = fcmp olt half %a.val, %b.val 32 %r.val = select i1 %fcmp, half %c.val, half %d.val 33 store half %r.val, half addrspace(1)* %r 34 ret void 35} 36 37; GCN-LABEL: {{^}}select_f16_imm_a: 38; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 39; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] 40; GCN: buffer_load_ushort v[[D_F16:[0-9]+]] 41; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 42; SI: v_cmp_lt_f32_e32 vcc, 0.5, v[[B_F32]] 43; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]] 44; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]] 45; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]] 46; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 47; VI: v_cmp_lt_f16_e32 vcc, 0.5, v[[B_F16]] 48; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc 49; GCN: buffer_store_short v[[R_F16]] 50; GCN: s_endpgm 51define amdgpu_kernel void @select_f16_imm_a( 52 half addrspace(1)* %r, 53 half addrspace(1)* %b, 54 half addrspace(1)* %c, 55 half addrspace(1)* %d) { 56entry: 57 %b.val = load half, half addrspace(1)* %b 58 %c.val = load half, half addrspace(1)* %c 59 %d.val = load half, half addrspace(1)* %d 60 %fcmp = fcmp olt half 0xH3800, %b.val 61 %r.val = select i1 %fcmp, half %c.val, half %d.val 62 store half %r.val, half addrspace(1)* %r 63 ret void 64} 65 66; GCN-LABEL: {{^}}select_f16_imm_b: 67; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 68; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] 69; GCN: buffer_load_ushort v[[D_F16:[0-9]+]] 70; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 71; SI: v_cmp_gt_f32_e32 vcc, 0.5, v[[A_F32]] 72; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]] 73; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]] 74; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]] 75; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 76 77; VI: v_cmp_gt_f16_e32 vcc, 0.5, v[[A_F16]] 78; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc 79; GCN: buffer_store_short v[[R_F16]] 80; GCN: s_endpgm 81define amdgpu_kernel void @select_f16_imm_b( 82 half addrspace(1)* %r, 83 half addrspace(1)* %a, 84 half addrspace(1)* %c, 85 half addrspace(1)* %d) { 86entry: 87 %a.val = load half, half addrspace(1)* %a 88 %c.val = load half, half addrspace(1)* %c 89 %d.val = load half, half addrspace(1)* %d 90 %fcmp = fcmp olt half %a.val, 0xH3800 91 %r.val = select i1 %fcmp, half %c.val, half %d.val 92 store half %r.val, half addrspace(1)* %r 93 ret void 94} 95 96; GCN-LABEL: {{^}}select_f16_imm_c: 97; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 98; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 99; GCN: buffer_load_ushort v[[D_F16:[0-9]+]] 100; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 101; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 102; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]] 103; SI: v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]] 104; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[D_F32]], vcc 105; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 106 107; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] 108; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x3800{{$}} 109; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[C_F16]], v[[D_F16]], vcc 110; GCN: buffer_store_short v[[R_F16]] 111; GCN: s_endpgm 112define amdgpu_kernel void @select_f16_imm_c( 113 half addrspace(1)* %r, 114 half addrspace(1)* %a, 115 half addrspace(1)* %b, 116 half addrspace(1)* %d) { 117entry: 118 %a.val = load half, half addrspace(1)* %a 119 %b.val = load half, half addrspace(1)* %b 120 %d.val = load half, half addrspace(1)* %d 121 %fcmp = fcmp olt half %a.val, %b.val 122 %r.val = select i1 %fcmp, half 0xH3800, half %d.val 123 store half %r.val, half addrspace(1)* %r 124 ret void 125} 126 127; GCN-LABEL: {{^}}select_f16_imm_d: 128; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 129; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 130; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] 131; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 132; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 133; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]] 134; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]] 135; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[C_F32]] 136; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 137; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] 138; VI: v_mov_b32_e32 v[[D_F16:[0-9]+]], 0x3800{{$}} 139; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc 140; GCN: buffer_store_short v[[R_F16]] 141; GCN: s_endpgm 142define amdgpu_kernel void @select_f16_imm_d( 143 half addrspace(1)* %r, 144 half addrspace(1)* %a, 145 half addrspace(1)* %b, 146 half addrspace(1)* %c) { 147entry: 148 %a.val = load half, half addrspace(1)* %a 149 %b.val = load half, half addrspace(1)* %b 150 %c.val = load half, half addrspace(1)* %c 151 %fcmp = fcmp olt half %a.val, %b.val 152 %r.val = select i1 %fcmp, half %c.val, half 0xH3800 153 store half %r.val, half addrspace(1)* %r 154 ret void 155} 156 157; GCN-LABEL: {{^}}select_v2f16: 158; SI: v_cvt_f32_f16_e32 159; SI: v_cvt_f32_f16_e32 160; SI: v_cvt_f32_f16_e32 161; SI: v_cvt_f32_f16_e32 162; SI: v_cmp_lt_f32_e64 163; SI: v_cmp_lt_f32_e32 164; VI: v_cmp_lt_f16_e32 165; VI: v_cmp_lt_f16_e64 166; GCN: v_cndmask_b32_e32 167; GCN: v_cndmask_b32_e64 168; SI: v_cvt_f16_f32_e32 169; SI: v_cvt_f16_f32_e32 170; GCN: s_endpgm 171define amdgpu_kernel void @select_v2f16( 172 <2 x half> addrspace(1)* %r, 173 <2 x half> addrspace(1)* %a, 174 <2 x half> addrspace(1)* %b, 175 <2 x half> addrspace(1)* %c, 176 <2 x half> addrspace(1)* %d) { 177entry: 178 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 179 %b.val = load <2 x half>, <2 x half> addrspace(1)* %b 180 %c.val = load <2 x half>, <2 x half> addrspace(1)* %c 181 %d.val = load <2 x half>, <2 x half> addrspace(1)* %d 182 %fcmp = fcmp olt <2 x half> %a.val, %b.val 183 %r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val 184 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 185 ret void 186} 187 188; GCN-LABEL: {{^}}select_v2f16_imm_a: 189; SI: v_cvt_f32_f16_e32 190; SI: v_cvt_f32_f16_e32 191; SI: v_cvt_f32_f16_e32 192; SI: v_cvt_f32_f16_e32 193; SI: v_cvt_f32_f16_e32 194; SI: v_cvt_f32_f16_e32 195; SI: v_cmp_lt_f32_e64 196; SI: v_cmp_lt_f32_e32 vcc, 0.5 197 198; VI: v_cmp_lt_f16_e32 199; VI: v_cmp_lt_f16_e64 200; GCN: v_cndmask_b32_e32 201; GCN: v_cndmask_b32_e64 202; SI: v_cvt_f16_f32_e32 203; SI: v_cvt_f16_f32_e32 204; GCN: s_endpgm 205define amdgpu_kernel void @select_v2f16_imm_a( 206 <2 x half> addrspace(1)* %r, 207 <2 x half> addrspace(1)* %b, 208 <2 x half> addrspace(1)* %c, 209 <2 x half> addrspace(1)* %d) { 210entry: 211 %b.val = load <2 x half>, <2 x half> addrspace(1)* %b 212 %c.val = load <2 x half>, <2 x half> addrspace(1)* %c 213 %d.val = load <2 x half>, <2 x half> addrspace(1)* %d 214 %fcmp = fcmp olt <2 x half> <half 0xH3800, half 0xH3900>, %b.val 215 %r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val 216 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 217 ret void 218} 219 220; GCN-LABEL: {{^}}select_v2f16_imm_b: 221; SI: v_cvt_f32_f16_e32 222; SI: v_cvt_f32_f16_e32 223; SI: v_cvt_f32_f16_e32 224; SI: v_cvt_f32_f16_e32 225; SI: v_cvt_f32_f16_e32 226; SI: v_cvt_f32_f16_e32 227; SI: v_cmp_gt_f32_e64 228; SI: v_cmp_gt_f32_e32 vcc, 0.5 229 230; VI: v_cmp_gt_f16_e32 231; VI: v_cmp_gt_f16_e64 232; GCN: v_cndmask_b32_e32 233; GCN: v_cndmask_b32_e64 234 235; SI: v_cvt_f16_f32_e32 236; SI: v_cvt_f16_f32_e32 237; GCN: s_endpgm 238define amdgpu_kernel void @select_v2f16_imm_b( 239 <2 x half> addrspace(1)* %r, 240 <2 x half> addrspace(1)* %a, 241 <2 x half> addrspace(1)* %c, 242 <2 x half> addrspace(1)* %d) { 243entry: 244 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 245 %c.val = load <2 x half>, <2 x half> addrspace(1)* %c 246 %d.val = load <2 x half>, <2 x half> addrspace(1)* %d 247 %fcmp = fcmp olt <2 x half> %a.val, <half 0xH3800, half 0xH3900> 248 %r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val 249 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 250 ret void 251} 252 253; GCN-LABEL: {{^}}select_v2f16_imm_c: 254; SI: v_cvt_f32_f16_e32 255; SI: v_cvt_f32_f16_e32 256; SI: v_cvt_f32_f16_e32 257; SI: v_cvt_f32_f16_e32 258; SI: v_cvt_f32_f16_e32 259; SI: v_cvt_f32_f16_e32 260 261; SI: v_cmp_nlt_f32_e32 262; SI: v_cmp_nlt_f32_e64 263; SI: v_cndmask_b32_e64 264; SI: v_cndmask_b32_e32 265 266; VI: v_cmp_nlt_f16_e32 267; VI: v_cndmask_b32_e32 268 269; VI: v_cmp_nlt_f16_e32 270; VI: v_cndmask_b32_e32 271 272; SI: v_cvt_f16_f32_e32 273; SI: v_cvt_f16_f32_e32 274; GCN: s_endpgm 275define amdgpu_kernel void @select_v2f16_imm_c( 276 <2 x half> addrspace(1)* %r, 277 <2 x half> addrspace(1)* %a, 278 <2 x half> addrspace(1)* %b, 279 <2 x half> addrspace(1)* %d) { 280entry: 281 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 282 %b.val = load <2 x half>, <2 x half> addrspace(1)* %b 283 %d.val = load <2 x half>, <2 x half> addrspace(1)* %d 284 %fcmp = fcmp olt <2 x half> %a.val, %b.val 285 %r.val = select <2 x i1> %fcmp, <2 x half> <half 0xH3800, half 0xH3900>, <2 x half> %d.val 286 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 287 ret void 288} 289 290; GCN-LABEL: {{^}}select_v2f16_imm_d: 291; SI: v_cvt_f32_f16_e32 292; SI: v_cvt_f32_f16_e32 293; SI: v_cvt_f32_f16_e32 294; SI: v_cvt_f32_f16_e32 295; SI: v_cvt_f32_f16_e32 296; SI: v_cvt_f32_f16_e32 297; SI: v_cmp_lt_f32_e64 298; SI: v_cmp_lt_f32_e32 299 300; VI: v_cmp_lt_f16_e32 301; VI: v_cmp_lt_f16_e64 302; GCN: v_cndmask_b32 303; GCN: v_cndmask_b32 304; SI: v_cvt_f16_f32_e32 305; SI: v_cvt_f16_f32_e32 306; GCN: s_endpgm 307define amdgpu_kernel void @select_v2f16_imm_d( 308 <2 x half> addrspace(1)* %r, 309 <2 x half> addrspace(1)* %a, 310 <2 x half> addrspace(1)* %b, 311 <2 x half> addrspace(1)* %c) { 312entry: 313 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 314 %b.val = load <2 x half>, <2 x half> addrspace(1)* %b 315 %c.val = load <2 x half>, <2 x half> addrspace(1)* %c 316 %fcmp = fcmp olt <2 x half> %a.val, %b.val 317 %r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> <half 0xH3800, half 0xH3900> 318 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 319 ret void 320} 321