1; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s 3; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s 4 5; Test expansion of scalar selects on vectors. 6; Evergreen not enabled since it seems to be having problems with doubles. 7 8; GCN-LABEL: {{^}}v_select_v2i8: 9; SI: v_cndmask_b32 10; SI-NOT: cndmask 11 12; GFX9: v_cndmask_b32 13; GFX9-NOT: cndmask 14 15; This is worse when i16 is legal and packed is not because 16; SelectionDAGBuilder for some reason changes the select type. 17; VI: v_cndmask_b32 18; VI: v_cndmask_b32 19define amdgpu_kernel void @v_select_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(1)* %a.ptr, <2 x i8> addrspace(1)* %b.ptr, i32 %c) #0 { 20 %a = load <2 x i8>, <2 x i8> addrspace(1)* %a.ptr, align 2 21 %b = load <2 x i8>, <2 x i8> addrspace(1)* %b.ptr, align 2 22 %cmp = icmp eq i32 %c, 0 23 %select = select i1 %cmp, <2 x i8> %a, <2 x i8> %b 24 store <2 x i8> %select, <2 x i8> addrspace(1)* %out, align 2 25 ret void 26} 27 28; GCN-LABEL: {{^}}v_select_v4i8: 29; GCN: v_cndmask_b32_e32 30; GCN-NOT: cndmask 31define amdgpu_kernel void @v_select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %a.ptr, <4 x i8> addrspace(1)* %b.ptr, i32 %c) #0 { 32 %a = load <4 x i8>, <4 x i8> addrspace(1)* %a.ptr 33 %b = load <4 x i8>, <4 x i8> addrspace(1)* %b.ptr 34 %cmp = icmp eq i32 %c, 0 35 %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b 36 store <4 x i8> %select, <4 x i8> addrspace(1)* %out, align 4 37 ret void 38} 39 40; GCN-LABEL: {{^}}v_select_v8i8: 41; GCN: v_cndmask_b32_e32 42; GCN: v_cndmask_b32_e32 43; GCN-NOT: cndmask 44define amdgpu_kernel void @v_select_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(1)* %a.ptr, <8 x i8> addrspace(1)* %b.ptr, i32 %c) #0 { 45 %a = load <8 x i8>, <8 x i8> addrspace(1)* %a.ptr 46 %b = load <8 x i8>, <8 x i8> addrspace(1)* %b.ptr 47 %cmp = icmp eq i32 %c, 0 48 %select = select i1 %cmp, <8 x i8> %a, <8 x i8> %b 49 store <8 x i8> %select, <8 x i8> addrspace(1)* %out, align 4 50 ret void 51} 52 53; GCN-LABEL: {{^}}v_select_v16i8: 54; GCN: v_cndmask_b32_e32 55; GCN: v_cndmask_b32_e32 56; GCN: v_cndmask_b32_e32 57; GCN: v_cndmask_b32_e32 58; GCN-NOT: cndmask 59define amdgpu_kernel void @v_select_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> addrspace(1)* %a.ptr, <16 x i8> addrspace(1)* %b.ptr, i32 %c) #0 { 60 %a = load <16 x i8>, <16 x i8> addrspace(1)* %a.ptr 61 %b = load <16 x i8>, <16 x i8> addrspace(1)* %b.ptr 62 %cmp = icmp eq i32 %c, 0 63 %select = select i1 %cmp, <16 x i8> %a, <16 x i8> %b 64 store <16 x i8> %select, <16 x i8> addrspace(1)* %out, align 4 65 ret void 66} 67 68; GCN-LABEL: {{^}}select_v4i8: 69; GCN: v_cndmask_b32 70; GCN-NOT: cndmask 71define amdgpu_kernel void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, i8 %c) #0 { 72 %cmp = icmp eq i8 %c, 0 73 %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b 74 store <4 x i8> %select, <4 x i8> addrspace(1)* %out, align 4 75 ret void 76} 77 78; GCN-LABEL: {{^}}select_v2i16: 79; GFX89: s_load_dword 80; GFX89: s_load_dword 81; GFX89: s_load_dword 82; GFX89: v_cndmask_b32 83; GFX89-NOT: v_cndmask_b32 84 85; SI: v_cndmask_b32_e32 86; SI-NOT: v_cndmask_b32e 87define amdgpu_kernel void @select_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b, i32 %c) #0 { 88 %cmp = icmp eq i32 %c, 0 89 %select = select i1 %cmp, <2 x i16> %a, <2 x i16> %b 90 store <2 x i16> %select, <2 x i16> addrspace(1)* %out, align 4 91 ret void 92} 93 94; GCN-LABEL: {{^}}v_select_v2i16: 95; GCN: buffer_load_dword v 96; GCN: buffer_load_dword v 97; GCN: v_cndmask_b32 98; GCN-NOT: cndmask 99define amdgpu_kernel void @v_select_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %a.ptr, <2 x i16> addrspace(1)* %b.ptr, i32 %c) #0 { 100 %a = load <2 x i16>, <2 x i16> addrspace(1)* %a.ptr 101 %b = load <2 x i16>, <2 x i16> addrspace(1)* %b.ptr 102 %cmp = icmp eq i32 %c, 0 103 %select = select i1 %cmp, <2 x i16> %a, <2 x i16> %b 104 store <2 x i16> %select, <2 x i16> addrspace(1)* %out, align 4 105 ret void 106} 107 108; GCN-LABEL: {{^}}v_select_v3i16: 109; SI: v_cndmask_b32_e32 110; SI: cndmask 111; SI-NOT: cndmask 112 113; GFX89: v_cndmask_b32_e32 114; GFX89: cndmask 115; VI: cndmask 116; GFX89-NOT: cndmask 117define amdgpu_kernel void @v_select_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %a.ptr, <3 x i16> addrspace(1)* %b.ptr, i32 %c) #0 { 118 %a = load <3 x i16>, <3 x i16> addrspace(1)* %a.ptr 119 %b = load <3 x i16>, <3 x i16> addrspace(1)* %b.ptr 120 %cmp = icmp eq i32 %c, 0 121 %select = select i1 %cmp, <3 x i16> %a, <3 x i16> %b 122 store <3 x i16> %select, <3 x i16> addrspace(1)* %out, align 4 123 ret void 124} 125 126; GCN-LABEL: {{^}}v_select_v4i16: 127; GCN: v_cndmask_b32_e32 128; GCN: v_cndmask_b32_e32 129; GCN-NOT: cndmask 130define amdgpu_kernel void @v_select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %a.ptr, <4 x i16> addrspace(1)* %b.ptr, i32 %c) #0 { 131 %a = load <4 x i16>, <4 x i16> addrspace(1)* %a.ptr 132 %b = load <4 x i16>, <4 x i16> addrspace(1)* %b.ptr 133 %cmp = icmp eq i32 %c, 0 134 %select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b 135 store <4 x i16> %select, <4 x i16> addrspace(1)* %out, align 4 136 ret void 137} 138 139; GCN-LABEL: {{^}}v_select_v8i16: 140; GCN: v_cndmask_b32_e32 141; GCN: v_cndmask_b32_e32 142; GCN: v_cndmask_b32_e32 143; GCN: v_cndmask_b32_e32 144; GCN-NOT: cndmask 145define amdgpu_kernel void @v_select_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> addrspace(1)* %a.ptr, <8 x i16> addrspace(1)* %b.ptr, i32 %c) #0 { 146 %a = load <8 x i16>, <8 x i16> addrspace(1)* %a.ptr 147 %b = load <8 x i16>, <8 x i16> addrspace(1)* %b.ptr 148 %cmp = icmp eq i32 %c, 0 149 %select = select i1 %cmp, <8 x i16> %a, <8 x i16> %b 150 store <8 x i16> %select, <8 x i16> addrspace(1)* %out, align 4 151 ret void 152} 153 154; FIXME: Expansion with bitwise operations may be better if doing a 155; vector select with SGPR inputs. 156 157; GCN-LABEL: {{^}}s_select_v2i32: 158; GCN: v_cndmask_b32_e32 159; GCN: v_cndmask_b32_e32 160; GCN: buffer_store_dwordx2 161define amdgpu_kernel void @s_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) #0 { 162 %cmp = icmp eq i32 %c, 0 163 %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b 164 store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8 165 ret void 166} 167 168; GCN-LABEL: {{^}}s_select_v4i32: 169; GCN: v_cndmask_b32_e32 170; GCN: v_cndmask_b32_e32 171; GCN: v_cndmask_b32_e32 172; GCN: v_cndmask_b32_e32 173; GCN: buffer_store_dwordx4 174define amdgpu_kernel void @s_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) #0 { 175 %cmp = icmp eq i32 %c, 0 176 %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b 177 store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16 178 ret void 179} 180 181; GCN-LABEL: {{^}}v_select_v4i32: 182; GCN: buffer_load_dwordx4 183; GCN: v_cmp_lt_u32_e64 vcc, s{{[0-9]+}}, 32 184; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 185; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 186; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 187; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 188; GCN: buffer_store_dwordx4 189define amdgpu_kernel void @v_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %cond) #0 { 190bb: 191 %tmp2 = icmp ult i32 %cond, 32 192 %val = load <4 x i32>, <4 x i32> addrspace(1)* %in 193 %tmp3 = select i1 %tmp2, <4 x i32> %val, <4 x i32> zeroinitializer 194 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 16 195 ret void 196} 197 198; GCN-LABEL: {{^}}select_v8i32: 199; GCN: v_cndmask_b32_e32 200; GCN: v_cndmask_b32_e32 201; GCN: v_cndmask_b32_e32 202; GCN: v_cndmask_b32_e32 203; GCN: v_cndmask_b32_e32 204; GCN: v_cndmask_b32_e32 205; GCN: v_cndmask_b32_e32 206; GCN: v_cndmask_b32_e32 207define amdgpu_kernel void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) #0 { 208 %cmp = icmp eq i32 %c, 0 209 %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b 210 store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16 211 ret void 212} 213 214; GCN-LABEL: {{^}}s_select_v2f32: 215; GCN-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} 216; GCN-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} 217 218; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]] 219; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] 220; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] 221; GCN-DAG: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} 222 223; GCN-DAG: v_cndmask_b32_e32 224; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]] 225; GCN-DAG: v_cndmask_b32_e32 226; GCN: buffer_store_dwordx2 227define amdgpu_kernel void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) #0 { 228 %cmp = icmp eq i32 %c, 0 229 %select = select i1 %cmp, <2 x float> %a, <2 x float> %b 230 store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16 231 ret void 232} 233 234; GCN-LABEL: {{^}}s_select_v3f32: 235; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} 236 237; GCN: v_cndmask_b32_e32 238; GCN: v_cndmask_b32_e32 239; GCN: v_cndmask_b32_e32 240 241; GCN: buffer_store_dwordx 242define amdgpu_kernel void @s_select_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b, i32 %c) #0 { 243 %cmp = icmp eq i32 %c, 0 244 %select = select i1 %cmp, <3 x float> %a, <3 x float> %b 245 store <3 x float> %select, <3 x float> addrspace(1)* %out, align 16 246 ret void 247} 248 249; GCN-LABEL: {{^}}s_select_v4f32: 250; GCN: s_load_dwordx4 251; GCN: s_load_dwordx4 252; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} 253 254; GCN: v_cndmask_b32_e32 255; GCN: v_cndmask_b32_e32 256; GCN: v_cndmask_b32_e32 257; GCN: v_cndmask_b32_e32 258 259; GCN: buffer_store_dwordx4 260define amdgpu_kernel void @s_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) #0 { 261 %cmp = icmp eq i32 %c, 0 262 %select = select i1 %cmp, <4 x float> %a, <4 x float> %b 263 store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16 264 ret void 265} 266 267; GCN-LABEL: {{^}}v_select_v4f32: 268; GCN: buffer_load_dwordx4 269; GCN: v_cmp_lt_u32_e64 vcc, s{{[0-9]+}}, 32 270; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 271; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 272; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 273; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} 274; GCN: buffer_store_dwordx4 275define amdgpu_kernel void @v_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %cond) #0 { 276bb: 277 %tmp2 = icmp ult i32 %cond, 32 278 %val = load <4 x float>, <4 x float> addrspace(1)* %in 279 %tmp3 = select i1 %tmp2, <4 x float> %val, <4 x float> zeroinitializer 280 store <4 x float> %tmp3, <4 x float> addrspace(1)* %out, align 16 281 ret void 282} 283 284; GCN-LABEL: {{^}}s_select_v5f32: 285; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} 286 287; GCN: v_cndmask_b32_e32 288; GCN: v_cndmask_b32_e32 289; GCN: v_cndmask_b32_e32 290; GCN: v_cndmask_b32_e32 291; GCN: v_cndmask_b32_e32 292 293; GCN: buffer_store_dwordx 294define amdgpu_kernel void @s_select_v5f32(<5 x float> addrspace(1)* %out, <5 x float> %a, <5 x float> %b, i32 %c) #0 { 295 %cmp = icmp eq i32 %c, 0 296 %select = select i1 %cmp, <5 x float> %a, <5 x float> %b 297 store <5 x float> %select, <5 x float> addrspace(1)* %out, align 16 298 ret void 299} 300 301; GCN-LABEL: {{^}}select_v8f32: 302; GCN: v_cndmask_b32_e32 303; GCN: v_cndmask_b32_e32 304; GCN: v_cndmask_b32_e32 305; GCN: v_cndmask_b32_e32 306; GCN: v_cndmask_b32_e32 307; GCN: v_cndmask_b32_e32 308; GCN: v_cndmask_b32_e32 309; GCN: v_cndmask_b32_e32 310define amdgpu_kernel void @select_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b, i32 %c) #0 { 311 %cmp = icmp eq i32 %c, 0 312 %select = select i1 %cmp, <8 x float> %a, <8 x float> %b 313 store <8 x float> %select, <8 x float> addrspace(1)* %out, align 16 314 ret void 315} 316 317; GCN-LABEL: {{^}}select_v2f64: 318; GCN: v_cndmask_b32_e32 319; GCN: v_cndmask_b32_e32 320; GCN: v_cndmask_b32_e32 321; GCN: v_cndmask_b32_e32 322define amdgpu_kernel void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) #0 { 323 %cmp = icmp eq i32 %c, 0 324 %select = select i1 %cmp, <2 x double> %a, <2 x double> %b 325 store <2 x double> %select, <2 x double> addrspace(1)* %out, align 16 326 ret void 327} 328 329; GCN-LABEL: {{^}}select_v4f64: 330; GCN: v_cndmask_b32_e32 331; GCN: v_cndmask_b32_e32 332; GCN: v_cndmask_b32_e32 333; GCN: v_cndmask_b32_e32 334; GCN: v_cndmask_b32_e32 335; GCN: v_cndmask_b32_e32 336; GCN: v_cndmask_b32_e32 337; GCN: v_cndmask_b32_e32 338define amdgpu_kernel void @select_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b, i32 %c) #0 { 339 %cmp = icmp eq i32 %c, 0 340 %select = select i1 %cmp, <4 x double> %a, <4 x double> %b 341 store <4 x double> %select, <4 x double> addrspace(1)* %out, align 16 342 ret void 343} 344 345; GCN-LABEL: {{^}}select_v8f64: 346; GCN: v_cndmask_b32_e32 347; GCN: v_cndmask_b32_e32 348; GCN: v_cndmask_b32_e32 349; GCN: v_cndmask_b32_e32 350; GCN: v_cndmask_b32_e32 351; GCN: v_cndmask_b32_e32 352; GCN: v_cndmask_b32_e32 353; GCN: v_cndmask_b32_e32 354; GCN: v_cndmask_b32_e32 355; GCN: v_cndmask_b32_e32 356; GCN: v_cndmask_b32_e32 357; GCN: v_cndmask_b32_e32 358; GCN: v_cndmask_b32_e32 359; GCN: v_cndmask_b32_e32 360; GCN: v_cndmask_b32_e32 361; GCN: v_cndmask_b32_e32 362define amdgpu_kernel void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b, i32 %c) #0 { 363 %cmp = icmp eq i32 %c, 0 364 %select = select i1 %cmp, <8 x double> %a, <8 x double> %b 365 store <8 x double> %select, <8 x double> addrspace(1)* %out, align 16 366 ret void 367} 368 369; GCN-LABEL: {{^}}v_select_v2f16: 370; GCN: v_cndmask_b32 371; GCN-NOT: cndmask 372define amdgpu_kernel void @v_select_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %a.ptr, <2 x half> addrspace(1)* %b.ptr, i32 %c) #0 { 373 %a = load <2 x half>, <2 x half> addrspace(1)* %a.ptr 374 %b = load <2 x half>, <2 x half> addrspace(1)* %b.ptr 375 %cmp = icmp eq i32 %c, 0 376 %select = select i1 %cmp, <2 x half> %a, <2 x half> %b 377 store <2 x half> %select, <2 x half> addrspace(1)* %out, align 4 378 ret void 379} 380 381; GCN-LABEL: {{^}}v_select_v3f16: 382; GCN: v_cndmask_b32_e32 383; GCN: v_cndmask_b32_e32 384; GCN-NOT: cndmask 385define amdgpu_kernel void @v_select_v3f16(<3 x half> addrspace(1)* %out, <3 x half> addrspace(1)* %a.ptr, <3 x half> addrspace(1)* %b.ptr, i32 %c) #0 { 386 %a = load <3 x half>, <3 x half> addrspace(1)* %a.ptr 387 %b = load <3 x half>, <3 x half> addrspace(1)* %b.ptr 388 %cmp = icmp eq i32 %c, 0 389 %select = select i1 %cmp, <3 x half> %a, <3 x half> %b 390 store <3 x half> %select, <3 x half> addrspace(1)* %out, align 4 391 ret void 392} 393 394; GCN-LABEL: {{^}}v_select_v4f16: 395; GCN: v_cndmask_b32_e32 396; GCN: v_cndmask_b32_e32 397; GCN-NOT: cndmask 398define amdgpu_kernel void @v_select_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %a.ptr, <4 x half> addrspace(1)* %b.ptr, i32 %c) #0 { 399 %a = load <4 x half>, <4 x half> addrspace(1)* %a.ptr 400 %b = load <4 x half>, <4 x half> addrspace(1)* %b.ptr 401 %cmp = icmp eq i32 %c, 0 402 %select = select i1 %cmp, <4 x half> %a, <4 x half> %b 403 store <4 x half> %select, <4 x half> addrspace(1)* %out, align 4 404 ret void 405} 406 407; Function Attrs: nounwind readnone 408declare i32 @llvm.amdgcn.workitem.id.x() #1 409 410attributes #0 = { nounwind } 411attributes #1 = { nounwind readnone } 412