1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_sdiv:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    s_mov_b32 s7, 0xf000
10; GCN-NEXT:    s_mov_b32 s6, -1
11; GCN-NEXT:    s_waitcnt lgkmcnt(0)
12; GCN-NEXT:    s_ashr_i32 s8, s3, 31
13; GCN-NEXT:    s_add_u32 s2, s2, s8
14; GCN-NEXT:    s_mov_b32 s9, s8
15; GCN-NEXT:    s_addc_u32 s3, s3, s8
16; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
17; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s10
18; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s11
19; GCN-NEXT:    s_sub_u32 s4, 0, s10
20; GCN-NEXT:    s_subb_u32 s5, 0, s11
21; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
22; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
23; GCN-NEXT:    v_rcp_f32_e32 v0, v0
24; GCN-NEXT:    v_mov_b32_e32 v1, 0
25; GCN-NEXT:    s_waitcnt lgkmcnt(0)
26; GCN-NEXT:    s_ashr_i32 s12, s3, 31
27; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
28; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
29; GCN-NEXT:    v_trunc_f32_e32 v2, v2
30; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
31; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
32; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
33; GCN-NEXT:    s_add_u32 s2, s2, s12
34; GCN-NEXT:    s_mov_b32 s13, s12
35; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
36; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
37; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
38; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
39; GCN-NEXT:    s_addc_u32 s3, s3, s12
40; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
41; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
42; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
43; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
44; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
45; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
46; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
48; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
49; GCN-NEXT:    v_mul_hi_u32 v8, v2, v3
50; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
51; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
52; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
53; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
54; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
55; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
56; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
57; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
58; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
59; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
60; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
61; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
62; GCN-NEXT:    s_mov_b32 s5, s1
63; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
64; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
65; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
66; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
67; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
68; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
69; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
70; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
71; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
72; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
73; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
74; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
75; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
76; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
77; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
78; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
79; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
80; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
81; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
82; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
83; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
84; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
85; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
86; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
87; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
88; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
89; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
90; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
91; GCN-NEXT:    s_mov_b32 s4, s0
92; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
93; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
94; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
95; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
96; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
97; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
98; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
99; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
100; GCN-NEXT:    v_mov_b32_e32 v5, s11
101; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
102; GCN-NEXT:    v_mul_lo_u32 v3, s10, v0
103; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
104; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
105; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
106; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
107; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
108; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
109; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
110; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
111; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
113; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
114; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
115; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
116; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
117; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
118; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
119; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
120; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
121; GCN-NEXT:    v_mov_b32_e32 v6, s3
122; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
123; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
124; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
125; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
126; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
127; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
128; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
129; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
130; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
131; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
132; GCN-NEXT:    s_xor_b64 s[0:1], s[12:13], s[8:9]
133; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
134; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
135; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
136; GCN-NEXT:    v_mov_b32_e32 v2, s1
137; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
138; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
139; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
140; GCN-NEXT:    s_endpgm
141;
142; GCN-IR-LABEL: s_test_sdiv:
143; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
144; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
145; GCN-IR-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
146; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
147; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
148; GCN-IR-NEXT:    s_mov_b32 s1, s0
149; GCN-IR-NEXT:    s_ashr_i32 s2, s9, 31
150; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[0:1], s[6:7]
151; GCN-IR-NEXT:    s_mov_b32 s3, s2
152; GCN-IR-NEXT:    s_sub_u32 s10, s6, s0
153; GCN-IR-NEXT:    s_subb_u32 s11, s7, s0
154; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[8:9]
155; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
156; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
157; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
158; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
159; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
160; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
161; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
162; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
163; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
164; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
165; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
166; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
167; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
168; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
169; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
170; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
171; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
172; GCN-IR-NEXT:    s_mov_b32 s15, 0
173; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
174; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
175; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
176; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
177; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
178; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
179; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
180; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
181; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
182; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
183; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
184; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
185; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
186; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
187; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
188; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
189; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
190; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
191; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
192; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
193; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
194; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
195; GCN-IR-NEXT:    s_mov_b32 s17, s15
196; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
197; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
198; GCN-IR-NEXT:    s_mov_b32 s9, 0
199; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
200; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
201; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
202; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
203; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
204; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
205; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
206; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
207; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
208; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
209; GCN-IR-NEXT:    s_mov_b32 s15, s14
210; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
211; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
212; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
213; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
214; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
215; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
216; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
217; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
218; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
219; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
220; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
221; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
222; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
223; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
224; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
225; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
226; GCN-IR-NEXT:    s_branch .LBB0_6
227; GCN-IR-NEXT:  .LBB0_5:
228; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
229; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
230; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
231; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
232; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
233; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
234; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
235; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
236; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
237; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
238; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
239; GCN-IR-NEXT:    s_mov_b32 s6, -1
240; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
241; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
242; GCN-IR-NEXT:    s_endpgm
243  %result = sdiv i64 %x, %y
244  store i64 %result, i64 addrspace(1)* %out
245  ret void
246}
247
248define i64 @v_test_sdiv(i64 %x, i64 %y) {
249; GCN-LABEL: v_test_sdiv:
250; GCN:       ; %bb.0:
251; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
252; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
253; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
254; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
255; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
256; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
257; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
258; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
259; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
260; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
261; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
262; GCN-NEXT:    v_rcp_f32_e32 v5, v5
263; GCN-NEXT:    v_mov_b32_e32 v14, 0
264; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
265; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
266; GCN-NEXT:    v_trunc_f32_e32 v6, v6
267; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
268; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
269; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
270; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
271; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
272; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
273; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
274; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
275; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
276; GCN-NEXT:    v_mul_lo_u32 v11, v5, v9
277; GCN-NEXT:    v_mul_hi_u32 v12, v5, v10
278; GCN-NEXT:    v_mul_hi_u32 v13, v5, v9
279; GCN-NEXT:    v_mul_hi_u32 v15, v6, v9
280; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
281; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
282; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
283; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
284; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
285; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
286; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v10, vcc
287; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v14, vcc
288; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
289; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
290; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
291; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v10, vcc
292; GCN-NEXT:    v_mul_lo_u32 v9, v7, v6
293; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
294; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
295; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
296; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
297; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
298; GCN-NEXT:    v_mul_lo_u32 v11, v5, v8
299; GCN-NEXT:    v_mul_hi_u32 v12, v5, v7
300; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
301; GCN-NEXT:    v_mul_hi_u32 v10, v6, v7
302; GCN-NEXT:    v_mul_lo_u32 v7, v6, v7
303; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
304; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
305; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
306; GCN-NEXT:    v_mul_lo_u32 v8, v6, v8
307; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
308; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v10, vcc
309; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v14, vcc
310; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
311; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
312; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
313; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
314; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
315; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
316; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
317; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
318; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
319; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
320; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
321; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
322; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
323; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
324; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
325; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
326; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
327; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
328; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
329; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
330; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
331; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
332; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
333; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
334; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
335; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
336; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
337; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
338; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
339; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
340; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
341; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
342; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
343; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
344; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
345; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
346; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
347; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
348; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
349; GCN-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
350; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 2, v5
351; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
352; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
353; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
354; GCN-NEXT:    v_add_i32_e64 v12, s[4:5], 1, v5
355; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
356; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
357; GCN-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
358; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
359; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
360; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
361; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
362; GCN-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
363; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
364; GCN-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
365; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
366; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
367; GCN-NEXT:    v_xor_b32_e32 v2, v7, v4
368; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
369; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
370; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
371; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
372; GCN-NEXT:    s_setpc_b64 s[30:31]
373;
374; GCN-IR-LABEL: v_test_sdiv:
375; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
376; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
377; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
378; GCN-IR-NEXT:    v_xor_b32_e32 v0, v4, v0
379; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
380; GCN-IR-NEXT:    v_xor_b32_e32 v1, v4, v1
381; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v0, v4
382; GCN-IR-NEXT:    v_subb_u32_e32 v12, vcc, v1, v4, vcc
383; GCN-IR-NEXT:    v_xor_b32_e32 v1, v5, v2
384; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v3
385; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
386; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v0, v5, vcc
387; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
388; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[11:12]
389; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v2
390; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
391; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
392; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v3
393; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v7
394; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v11
395; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
396; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v12
397; GCN-IR-NEXT:    v_min_u32_e32 v13, v7, v8
398; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v13
399; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
400; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
401; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
402; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
403; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
404; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
405; GCN-IR-NEXT:    v_mov_b32_e32 v6, v4
406; GCN-IR-NEXT:    v_mov_b32_e32 v1, v5
407; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v12, 0, s[6:7]
408; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
409; GCN-IR-NEXT:    v_mov_b32_e32 v16, v17
410; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v11, 0, s[6:7]
411; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
412; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
413; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
414; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
415; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
416; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
417; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
418; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[11:12], v7
419; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
420; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
421; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
422; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
423; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
424; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
425; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
426; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v2
427; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v3, vcc
428; GCN-IR-NEXT:    v_not_b32_e32 v0, v0
429; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[11:12], v14
430; GCN-IR-NEXT:    v_not_b32_e32 v9, v17
431; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v0, v13
432; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v16, vcc
433; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
434; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
435; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
436; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
437; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
438; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
439; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v8
440; GCN-IR-NEXT:    v_or_b32_e32 v0, v14, v0
441; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
442; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v0
443; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
444; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
445; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v11
446; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
447; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
448; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v12, vcc
449; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
450; GCN-IR-NEXT:    v_and_b32_e32 v20, v13, v3
451; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v2
452; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
453; GCN-IR-NEXT:    v_mov_b32_e32 v11, v16
454; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v0, v13
455; GCN-IR-NEXT:    v_mov_b32_e32 v12, v17
456; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
457; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
458; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
459; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
460; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
461; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
462; GCN-IR-NEXT:  ; %bb.4: ; %Flow
463; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
464; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
465; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
466; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[7:8], 1
467; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v3
468; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v2
469; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
470; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
471; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v4
472; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v6
473; GCN-IR-NEXT:    v_xor_b32_e32 v3, v9, v0
474; GCN-IR-NEXT:    v_xor_b32_e32 v2, v10, v1
475; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
476; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
477; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
478  %result = sdiv i64 %x, %y
479  ret i64 %result
480}
481
482define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
483; GCN-LABEL: s_test_sdiv24_64:
484; GCN:       ; %bb.0:
485; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
486; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
487; GCN-NEXT:    s_mov_b32 s3, 0xf000
488; GCN-NEXT:    s_mov_b32 s2, -1
489; GCN-NEXT:    s_waitcnt lgkmcnt(0)
490; GCN-NEXT:    s_mov_b32 s0, s4
491; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
492; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
493; GCN-NEXT:    s_mov_b32 s1, s5
494; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
495; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
496; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
497; GCN-NEXT:    s_xor_b32 s4, s4, s8
498; GCN-NEXT:    s_ashr_i32 s4, s4, 30
499; GCN-NEXT:    s_or_b32 s4, s4, 1
500; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
501; GCN-NEXT:    v_trunc_f32_e32 v2, v2
502; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
503; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
504; GCN-NEXT:    v_mov_b32_e32 v3, s4
505; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
506; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
507; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
508; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
509; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
510; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
511; GCN-NEXT:    s_endpgm
512;
513; GCN-IR-LABEL: s_test_sdiv24_64:
514; GCN-IR:       ; %bb.0:
515; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
516; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
517; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
518; GCN-IR-NEXT:    s_mov_b32 s2, -1
519; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
520; GCN-IR-NEXT:    s_mov_b32 s0, s4
521; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
522; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
523; GCN-IR-NEXT:    s_mov_b32 s1, s5
524; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
525; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
526; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
527; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
528; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
529; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
530; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
531; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
532; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
533; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
534; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
535; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
536; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
537; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
538; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
539; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
540; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
541; GCN-IR-NEXT:    s_endpgm
542  %1 = ashr i64 %x, 40
543  %2 = ashr i64 %y, 40
544  %result = sdiv i64 %1, %2
545  store i64 %result, i64 addrspace(1)* %out
546  ret void
547}
548
549define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
550; GCN-LABEL: v_test_sdiv24_64:
551; GCN:       ; %bb.0:
552; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
553; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
554; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
555; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
556; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
557; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
558; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
559; GCN-NEXT:    v_trunc_f32_e32 v2, v2
560; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
561; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
562; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
563; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
564; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
565; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
566; GCN-NEXT:    s_setpc_b64 s[30:31]
567;
568; GCN-IR-LABEL: v_test_sdiv24_64:
569; GCN-IR:       ; %bb.0:
570; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
571; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
572; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, v0
573; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
574; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v1
575; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
576; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
577; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
578; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
579; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
580; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
581; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
582; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
583; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
584; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
585  %1 = lshr i64 %x, 40
586  %2 = lshr i64 %y, 40
587  %result = sdiv i64 %1, %2
588  ret i64 %result
589}
590
591define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
592; GCN-LABEL: s_test_sdiv32_64:
593; GCN:       ; %bb.0:
594; GCN-NEXT:    s_load_dword s8, s[0:1], 0xe
595; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
596; GCN-NEXT:    s_mov_b32 s7, 0xf000
597; GCN-NEXT:    s_mov_b32 s6, -1
598; GCN-NEXT:    s_waitcnt lgkmcnt(0)
599; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
600; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
601; GCN-NEXT:    s_mov_b32 s4, s0
602; GCN-NEXT:    s_xor_b32 s0, s3, s8
603; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
604; GCN-NEXT:    s_ashr_i32 s0, s0, 30
605; GCN-NEXT:    s_or_b32 s0, s0, 1
606; GCN-NEXT:    v_mov_b32_e32 v3, s0
607; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
608; GCN-NEXT:    v_trunc_f32_e32 v2, v2
609; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
610; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
611; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
612; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
613; GCN-NEXT:    s_mov_b32 s5, s1
614; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
615; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
616; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
617; GCN-NEXT:    s_endpgm
618;
619; GCN-IR-LABEL: s_test_sdiv32_64:
620; GCN-IR:       ; %bb.0:
621; GCN-IR-NEXT:    s_load_dword s8, s[0:1], 0xe
622; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
623; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
624; GCN-IR-NEXT:    s_mov_b32 s6, -1
625; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
626; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
627; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
628; GCN-IR-NEXT:    s_mov_b32 s4, s0
629; GCN-IR-NEXT:    s_xor_b32 s0, s3, s8
630; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
631; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
632; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
633; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
634; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
635; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
636; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
637; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
638; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
639; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
640; GCN-IR-NEXT:    s_mov_b32 s5, s1
641; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
642; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
643; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
644; GCN-IR-NEXT:    s_endpgm
645  %1 = ashr i64 %x, 32
646  %2 = ashr i64 %y, 32
647  %result = sdiv i64 %1, %2
648  store i64 %result, i64 addrspace(1)* %out
649  ret void
650}
651
652define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
653; GCN-LABEL: s_test_sdiv31_64:
654; GCN:       ; %bb.0:
655; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
656; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
657; GCN-NEXT:    s_mov_b32 s3, 0xf000
658; GCN-NEXT:    s_mov_b32 s2, -1
659; GCN-NEXT:    s_waitcnt lgkmcnt(0)
660; GCN-NEXT:    s_mov_b32 s0, s4
661; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
662; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
663; GCN-NEXT:    s_mov_b32 s1, s5
664; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
665; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
666; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
667; GCN-NEXT:    s_xor_b32 s4, s4, s8
668; GCN-NEXT:    s_ashr_i32 s4, s4, 30
669; GCN-NEXT:    s_or_b32 s4, s4, 1
670; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
671; GCN-NEXT:    v_trunc_f32_e32 v2, v2
672; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
673; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
674; GCN-NEXT:    v_mov_b32_e32 v3, s4
675; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
676; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
677; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
678; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
679; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
680; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
681; GCN-NEXT:    s_endpgm
682;
683; GCN-IR-LABEL: s_test_sdiv31_64:
684; GCN-IR:       ; %bb.0:
685; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
686; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
687; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
688; GCN-IR-NEXT:    s_mov_b32 s2, -1
689; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
690; GCN-IR-NEXT:    s_mov_b32 s0, s4
691; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
692; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
693; GCN-IR-NEXT:    s_mov_b32 s1, s5
694; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
695; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
696; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
697; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
698; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
699; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
700; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
701; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
702; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
703; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
704; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
705; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
706; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
707; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
708; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
709; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
710; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
711; GCN-IR-NEXT:    s_endpgm
712  %1 = ashr i64 %x, 33
713  %2 = ashr i64 %y, 33
714  %result = sdiv i64 %1, %2
715  store i64 %result, i64 addrspace(1)* %out
716  ret void
717}
718
719define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
720; GCN-LABEL: s_test_sdiv23_64:
721; GCN:       ; %bb.0:
722; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
723; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
724; GCN-NEXT:    s_mov_b32 s3, 0xf000
725; GCN-NEXT:    s_mov_b32 s2, -1
726; GCN-NEXT:    s_waitcnt lgkmcnt(0)
727; GCN-NEXT:    s_mov_b32 s0, s4
728; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
729; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
730; GCN-NEXT:    s_mov_b32 s1, s5
731; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
732; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
733; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
734; GCN-NEXT:    s_xor_b32 s4, s4, s8
735; GCN-NEXT:    s_ashr_i32 s4, s4, 30
736; GCN-NEXT:    s_or_b32 s4, s4, 1
737; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
738; GCN-NEXT:    v_trunc_f32_e32 v2, v2
739; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
740; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
741; GCN-NEXT:    v_mov_b32_e32 v3, s4
742; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
743; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
744; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
745; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
746; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
747; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
748; GCN-NEXT:    s_endpgm
749;
750; GCN-IR-LABEL: s_test_sdiv23_64:
751; GCN-IR:       ; %bb.0:
752; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
753; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
754; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
755; GCN-IR-NEXT:    s_mov_b32 s2, -1
756; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
757; GCN-IR-NEXT:    s_mov_b32 s0, s4
758; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
759; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
760; GCN-IR-NEXT:    s_mov_b32 s1, s5
761; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
762; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
763; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
764; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
765; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
766; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
767; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
768; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
769; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
770; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
771; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
772; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
773; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
774; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
775; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
776; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
777; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
778; GCN-IR-NEXT:    s_endpgm
779  %1 = ashr i64 %x, 41
780  %2 = ashr i64 %y, 41
781  %result = sdiv i64 %1, %2
782  store i64 %result, i64 addrspace(1)* %out
783  ret void
784}
785
786define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
787; GCN-LABEL: s_test_sdiv25_64:
788; GCN:       ; %bb.0:
789; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
790; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
791; GCN-NEXT:    s_mov_b32 s3, 0xf000
792; GCN-NEXT:    s_mov_b32 s2, -1
793; GCN-NEXT:    s_waitcnt lgkmcnt(0)
794; GCN-NEXT:    s_mov_b32 s0, s4
795; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
796; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
797; GCN-NEXT:    s_mov_b32 s1, s5
798; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
799; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
800; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
801; GCN-NEXT:    s_xor_b32 s4, s4, s8
802; GCN-NEXT:    s_ashr_i32 s4, s4, 30
803; GCN-NEXT:    s_or_b32 s4, s4, 1
804; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
805; GCN-NEXT:    v_trunc_f32_e32 v2, v2
806; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
807; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
808; GCN-NEXT:    v_mov_b32_e32 v3, s4
809; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
810; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
811; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
812; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
813; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
814; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
815; GCN-NEXT:    s_endpgm
816;
817; GCN-IR-LABEL: s_test_sdiv25_64:
818; GCN-IR:       ; %bb.0:
819; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
820; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
821; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
822; GCN-IR-NEXT:    s_mov_b32 s2, -1
823; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
824; GCN-IR-NEXT:    s_mov_b32 s0, s4
825; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
826; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
827; GCN-IR-NEXT:    s_mov_b32 s1, s5
828; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
829; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
830; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
831; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
832; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
833; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
834; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
835; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
836; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
837; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
838; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
839; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
840; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
841; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
842; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
843; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
844; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
845; GCN-IR-NEXT:    s_endpgm
846  %1 = ashr i64 %x, 39
847  %2 = ashr i64 %y, 39
848  %result = sdiv i64 %1, %2
849  store i64 %result, i64 addrspace(1)* %out
850  ret void
851}
852
853define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
854; GCN-LABEL: s_test_sdiv24_v2i64:
855; GCN:       ; %bb.0:
856; GCN-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
857; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
858; GCN-NEXT:    s_mov_b32 s3, 0xf000
859; GCN-NEXT:    s_mov_b32 s2, -1
860; GCN-NEXT:    s_waitcnt lgkmcnt(0)
861; GCN-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
862; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
863; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
864; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
865; GCN-NEXT:    s_xor_b32 s4, s4, s8
866; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
867; GCN-NEXT:    s_ashr_i32 s4, s4, 30
868; GCN-NEXT:    s_or_b32 s4, s4, 1
869; GCN-NEXT:    v_mov_b32_e32 v3, s4
870; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
871; GCN-NEXT:    v_trunc_f32_e32 v2, v2
872; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
873; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
874; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
875; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
876; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
877; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
878; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s10
879; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
880; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s6
881; GCN-NEXT:    s_xor_b32 s4, s6, s10
882; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
883; GCN-NEXT:    s_ashr_i32 s4, s4, 30
884; GCN-NEXT:    s_or_b32 s4, s4, 1
885; GCN-NEXT:    v_mov_b32_e32 v5, s4
886; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
887; GCN-NEXT:    v_trunc_f32_e32 v4, v4
888; GCN-NEXT:    v_mad_f32 v3, -v4, v2, v3
889; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
890; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
891; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
892; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
893; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
894; GCN-NEXT:    v_bfe_i32 v2, v2, 0, 24
895; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
896; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
897; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
898; GCN-NEXT:    s_endpgm
899;
900; GCN-IR-LABEL: s_test_sdiv24_v2i64:
901; GCN-IR:       ; %bb.0:
902; GCN-IR-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
903; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
904; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
905; GCN-IR-NEXT:    s_mov_b32 s2, -1
906; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
907; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
908; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
909; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
910; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
911; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
912; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
913; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
914; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
915; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
916; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
917; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
918; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
919; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
920; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
921; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
922; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
923; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
924; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v2, s10
925; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
926; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, s6
927; GCN-IR-NEXT:    s_xor_b32 s4, s6, s10
928; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v2
929; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
930; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
931; GCN-IR-NEXT:    v_mov_b32_e32 v5, s4
932; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
933; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
934; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v2, v3
935; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
936; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
937; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
938; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
939; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
940; GCN-IR-NEXT:    v_bfe_i32 v2, v2, 0, 24
941; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
942; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
943; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
944; GCN-IR-NEXT:    s_endpgm
945  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
946  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
947  %result = sdiv <2 x i64> %1, %2
948  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
949  ret void
950}
951
952define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
953; GCN-LABEL: s_test_sdiv24_48:
954; GCN:       ; %bb.0:
955; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
956; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
957; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
958; GCN-NEXT:    s_load_dword s8, s[0:1], 0xe
959; GCN-NEXT:    s_load_dword s0, s[0:1], 0xd
960; GCN-NEXT:    s_mov_b32 s7, 0xf000
961; GCN-NEXT:    s_waitcnt lgkmcnt(0)
962; GCN-NEXT:    v_mov_b32_e32 v2, s2
963; GCN-NEXT:    s_sext_i32_i16 s1, s3
964; GCN-NEXT:    s_sext_i32_i16 s3, s8
965; GCN-NEXT:    v_mov_b32_e32 v0, s0
966; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
967; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
968; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
969; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
970; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
971; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
972; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
973; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
974; GCN-NEXT:    s_mov_b32 s6, -1
975; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
976; GCN-NEXT:    v_trunc_f32_e32 v2, v2
977; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
978; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
979; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
980; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
981; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
982; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
983; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
984; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
985; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
986; GCN-NEXT:    s_endpgm
987;
988; GCN-IR-LABEL: s_test_sdiv24_48:
989; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
990; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
991; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
992; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
993; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
994; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
995; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
996; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
997; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
998; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[2:3], 24
999; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1000; GCN-IR-NEXT:    s_mov_b32 s3, s2
1001; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 24
1002; GCN-IR-NEXT:    s_ashr_i32 s4, s5, 31
1003; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[6:7]
1004; GCN-IR-NEXT:    s_mov_b32 s5, s4
1005; GCN-IR-NEXT:    s_sub_u32 s10, s6, s2
1006; GCN-IR-NEXT:    s_subb_u32 s11, s7, s2
1007; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], s[8:9]
1008; GCN-IR-NEXT:    s_sub_u32 s6, s6, s4
1009; GCN-IR-NEXT:    s_subb_u32 s7, s7, s4
1010; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
1011; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
1012; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1013; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
1014; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
1015; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1016; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
1017; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1018; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
1019; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1020; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
1021; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
1022; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
1023; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1024; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
1025; GCN-IR-NEXT:    s_mov_b32 s15, 0
1026; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
1027; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
1028; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
1029; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
1030; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1031; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_5
1032; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1033; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
1034; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1035; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
1036; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1037; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
1038; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1039; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1040; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
1041; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_4
1042; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1043; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
1044; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
1045; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
1046; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
1047; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
1048; GCN-IR-NEXT:    s_mov_b32 s17, s15
1049; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
1050; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1051; GCN-IR-NEXT:    s_mov_b32 s9, 0
1052; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1053; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1054; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
1055; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1056; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1057; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1058; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1059; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
1060; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
1061; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1062; GCN-IR-NEXT:    s_mov_b32 s15, s14
1063; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1064; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
1065; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
1066; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1067; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
1068; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1069; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1070; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1071; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1072; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1073; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_3
1074; GCN-IR-NEXT:  .LBB9_4: ; %Flow3
1075; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
1076; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1077; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1078; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1079; GCN-IR-NEXT:    s_branch .LBB9_6
1080; GCN-IR-NEXT:  .LBB9_5:
1081; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
1082; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
1083; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1084; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
1085; GCN-IR-NEXT:  .LBB9_6: ; %udiv-end
1086; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1087; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1088; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1089; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1090; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1091; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1092; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1093; GCN-IR-NEXT:    s_mov_b32 s2, -1
1094; GCN-IR-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
1095; GCN-IR-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1096; GCN-IR-NEXT:    s_endpgm
1097  %1 = ashr i48 %x, 24
1098  %2 = ashr i48 %y, 24
1099  %result = sdiv i48 %1, %2
1100  store i48 %result, i48 addrspace(1)* %out
1101  ret void
1102}
1103
1104define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1105; GCN-LABEL: s_test_sdiv_k_num_i64:
1106; GCN:       ; %bb.0:
1107; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1108; GCN-NEXT:    s_mov_b32 s7, 0xf000
1109; GCN-NEXT:    s_mov_b32 s6, -1
1110; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1111; GCN-NEXT:    s_ashr_i32 s8, s3, 31
1112; GCN-NEXT:    s_add_u32 s2, s2, s8
1113; GCN-NEXT:    s_mov_b32 s9, s8
1114; GCN-NEXT:    s_addc_u32 s3, s3, s8
1115; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
1116; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1117; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
1118; GCN-NEXT:    s_sub_u32 s4, 0, s2
1119; GCN-NEXT:    s_subb_u32 s5, 0, s3
1120; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1121; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1122; GCN-NEXT:    v_mov_b32_e32 v1, 0
1123; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1124; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
1125; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1126; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
1127; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1128; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1129; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
1130; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
1131; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
1132; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
1133; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1134; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1135; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
1136; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1137; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
1138; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1139; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
1140; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
1141; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1142; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
1143; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1144; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1145; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
1146; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
1147; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1148; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
1149; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1150; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
1151; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
1152; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
1153; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
1154; GCN-NEXT:    s_mov_b32 s5, s1
1155; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1156; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
1157; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1158; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
1159; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
1160; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
1161; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
1162; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
1163; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
1164; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1165; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1166; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1167; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1168; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
1169; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
1170; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1171; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1172; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1173; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1174; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1175; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1176; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1177; GCN-NEXT:    v_mov_b32_e32 v4, s3
1178; GCN-NEXT:    s_mov_b32 s4, s0
1179; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1180; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
1181; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0
1182; GCN-NEXT:    v_mul_hi_u32 v2, s2, v0
1183; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1184; GCN-NEXT:    v_mul_lo_u32 v2, s2, v0
1185; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
1186; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1187; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
1188; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v2
1189; GCN-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
1190; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v3
1191; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1192; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v4
1193; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
1194; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v3
1195; GCN-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
1196; GCN-NEXT:    v_add_i32_e64 v4, s[0:1], 2, v0
1197; GCN-NEXT:    v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
1198; GCN-NEXT:    v_add_i32_e64 v6, s[0:1], 1, v0
1199; GCN-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
1200; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1201; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
1202; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
1203; GCN-NEXT:    v_cndmask_b32_e64 v3, v7, v5, s[0:1]
1204; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1205; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
1206; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
1207; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
1208; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
1209; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1210; GCN-NEXT:    v_cndmask_b32_e64 v2, v6, v4, s[0:1]
1211; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1212; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
1213; GCN-NEXT:    v_xor_b32_e32 v0, s8, v0
1214; GCN-NEXT:    v_xor_b32_e32 v1, s8, v1
1215; GCN-NEXT:    v_mov_b32_e32 v2, s8
1216; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
1217; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1218; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1219; GCN-NEXT:    s_endpgm
1220;
1221; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1222; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1223; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1224; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1225; GCN-IR-NEXT:    s_ashr_i32 s4, s3, 31
1226; GCN-IR-NEXT:    s_mov_b32 s5, s4
1227; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1228; GCN-IR-NEXT:    s_sub_u32 s2, s2, s4
1229; GCN-IR-NEXT:    s_subb_u32 s3, s3, s4
1230; GCN-IR-NEXT:    s_flbit_i32_b32 s6, s2
1231; GCN-IR-NEXT:    s_add_i32 s6, s6, 32
1232; GCN-IR-NEXT:    s_flbit_i32_b32 s7, s3
1233; GCN-IR-NEXT:    s_min_u32 s8, s6, s7
1234; GCN-IR-NEXT:    s_add_u32 s10, s8, 0xffffffc5
1235; GCN-IR-NEXT:    s_addc_u32 s11, 0, -1
1236; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1237; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[14:15], s[10:11], 63
1238; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1239; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
1240; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[14:15], s[10:11], 63
1241; GCN-IR-NEXT:    s_xor_b64 s[16:17], s[12:13], -1
1242; GCN-IR-NEXT:    s_and_b64 s[14:15], s[16:17], s[14:15]
1243; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
1244; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_5
1245; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1246; GCN-IR-NEXT:    s_add_u32 s12, s10, 1
1247; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1248; GCN-IR-NEXT:    s_addc_u32 s13, s11, 0
1249; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1250; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1251; GCN-IR-NEXT:    s_sub_i32 s9, 63, s10
1252; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1253; GCN-IR-NEXT:    s_lshl_b64 s[10:11], 24, s9
1254; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_4
1255; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1256; GCN-IR-NEXT:    s_lshr_b64 s[14:15], 24, s12
1257; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
1258; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
1259; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1260; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1261; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1262; GCN-IR-NEXT:    s_mov_b32 s7, 0
1263; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1264; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1265; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1266; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
1267; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1268; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
1269; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
1270; GCN-IR-NEXT:    s_sub_u32 s6, s16, s14
1271; GCN-IR-NEXT:    s_subb_u32 s6, s17, s15
1272; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
1273; GCN-IR-NEXT:    s_mov_b32 s13, s12
1274; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
1275; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[2:3]
1276; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
1277; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1278; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
1279; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1280; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1281; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1282; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
1283; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
1284; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_3
1285; GCN-IR-NEXT:  .LBB10_4: ; %Flow5
1286; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[10:11], 1
1287; GCN-IR-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
1288; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1289; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1290; GCN-IR-NEXT:    s_branch .LBB10_6
1291; GCN-IR-NEXT:  .LBB10_5:
1292; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1293; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[12:13]
1294; GCN-IR-NEXT:  .LBB10_6: ; %udiv-end
1295; GCN-IR-NEXT:    v_xor_b32_e32 v0, s4, v0
1296; GCN-IR-NEXT:    v_xor_b32_e32 v1, s5, v1
1297; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1298; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
1299; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1300; GCN-IR-NEXT:    s_mov_b32 s2, -1
1301; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1302; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1303; GCN-IR-NEXT:    s_endpgm
1304  %result = sdiv i64 24, %x
1305  store i64 %result, i64 addrspace(1)* %out
1306  ret void
1307}
1308
1309define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1310; GCN-LABEL: v_test_sdiv_k_num_i64:
1311; GCN:       ; %bb.0:
1312; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1313; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1314; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1315; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1316; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1317; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1318; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1319; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1320; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1321; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1322; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1323; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1324; GCN-NEXT:    v_mov_b32_e32 v12, 0
1325; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1326; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1327; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1328; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1329; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1330; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1331; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1332; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1333; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1334; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1335; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1336; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1337; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
1338; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
1339; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
1340; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
1341; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1342; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1343; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1344; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1345; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1346; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
1347; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
1348; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
1349; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1350; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1351; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1352; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1353; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1354; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1355; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1356; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1357; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1358; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1359; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1360; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1361; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1362; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1363; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1364; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1365; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1366; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1367; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1368; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1369; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1370; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1371; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1372; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
1373; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1374; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
1375; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
1376; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1377; GCN-NEXT:    v_mul_hi_u32 v4, v4, 24
1378; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1379; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1380; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1381; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1382; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1383; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1384; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1385; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 24, v5
1386; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1387; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1388; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1389; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1390; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1391; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1392; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1393; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1394; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1395; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1396; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1397; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1398; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1399; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1400; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1401; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1402; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1403; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1404; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1405; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1406; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1407; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1408; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1409; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1410; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1411; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1412; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1413; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1414; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1415; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1416; GCN-NEXT:    s_setpc_b64 s[30:31]
1417;
1418; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1419; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1420; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1421; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1422; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1423; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1424; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1425; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1426; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1427; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1428; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1429; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1430; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1431; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1432; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1433; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1434; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1435; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1436; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1437; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1438; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, 24, 0, s[4:5]
1439; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1440; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1441; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1442; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1443; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1444; GCN-IR-NEXT:    s_cbranch_execz .LBB11_6
1445; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1446; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1447; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1448; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1449; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1450; GCN-IR-NEXT:    v_lshl_b64 v[4:5], 24, v4
1451; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1452; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1453; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1454; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1455; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1456; GCN-IR-NEXT:    s_cbranch_execz .LBB11_5
1457; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1458; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1459; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1460; GCN-IR-NEXT:    v_lshr_b64 v[10:11], 24, v10
1461; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 58, v8
1462; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1463; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1464; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1465; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1466; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1467; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1468; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1469; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1470; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1471; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1472; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1473; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1474; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1475; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1476; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1477; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1478; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1479; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1480; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1481; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1482; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1483; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1484; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1485; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1486; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1487; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1488; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1489; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1490; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1491; GCN-IR-NEXT:    s_cbranch_execnz .LBB11_3
1492; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1493; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1494; GCN-IR-NEXT:  .LBB11_5: ; %Flow3
1495; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1496; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1497; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1498; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1499; GCN-IR-NEXT:  .LBB11_6: ; %Flow4
1500; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1501; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1502; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1503; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1504; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1505; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1506  %result = sdiv i64 24, %x
1507  ret i64 %result
1508}
1509
1510define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1511; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1512; GCN:       ; %bb.0:
1513; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1514; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1515; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1516; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1517; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1518; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1519; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1520; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1521; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1522; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1523; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1524; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1525; GCN-NEXT:    v_mov_b32_e32 v12, 0
1526; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1527; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1528; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1529; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1530; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1531; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1532; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1533; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1534; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1535; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1536; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1537; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1538; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
1539; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
1540; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
1541; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
1542; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1543; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1544; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1545; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1546; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1547; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
1548; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
1549; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
1550; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1551; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1552; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1553; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1554; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1555; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1556; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1557; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1558; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1559; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1560; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1561; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1562; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1563; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1564; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1565; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1566; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1567; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1568; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1569; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1570; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1571; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1572; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1573; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
1574; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1575; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v4, v6, vcc
1576; GCN-NEXT:    v_lshrrev_b32_e32 v3, 17, v3
1577; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1578; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1579; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1580; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1581; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1582; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0x8000, v5
1583; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1584; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1585; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1586; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1587; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1588; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1589; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1590; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1591; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1592; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1593; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1594; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1595; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1596; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1597; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1598; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1599; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1600; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1601; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1602; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1603; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1604; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1605; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1606; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1607; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1608; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1609; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1610; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1611; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1612; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1613; GCN-NEXT:    s_setpc_b64 s[30:31]
1614;
1615; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1616; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1617; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1618; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1619; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1620; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1621; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1622; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1623; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1624; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1625; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1626; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1627; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1628; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1629; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1630; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1631; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1632; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1633; GCN-IR-NEXT:    v_mov_b32_e32 v6, s8
1634; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1635; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1636; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1637; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[4:5]
1638; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1639; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1640; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1641; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1642; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1643; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1644; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1645; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1646; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1647; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1648; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1649; GCN-IR-NEXT:    v_lshl_b64 v[4:5], s[8:9], v4
1650; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1651; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1652; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1653; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1654; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1655; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1656; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1657; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1658; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1659; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1660; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v10
1661; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1662; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1663; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1664; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1665; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1666; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1667; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1668; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1669; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1670; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1671; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1672; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1673; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1674; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1675; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1676; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1677; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1678; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1679; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1680; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1681; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1682; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1683; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1684; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1685; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1686; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1687; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1688; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1689; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1690; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1691; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1692; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1693; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1694; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1695; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1696; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1697; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1698; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1699; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1700; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1701; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1702; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1703; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1704; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1705; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1706  %result = sdiv i64 32768, %x
1707  ret i64 %result
1708}
1709
1710define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1711; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1712; GCN:       ; %bb.0:
1713; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1714; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1715; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1716; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1717; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1718; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1719; GCN-NEXT:    s_setpc_b64 s[30:31]
1720;
1721; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1722; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1723; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1724; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1725; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1726; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1727; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v2
1728; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v1, v2, vcc
1729; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v7
1730; GCN-IR-NEXT:    v_add_i32_e64 v0, s[4:5], 32, v0
1731; GCN-IR-NEXT:    v_ffbh_u32_e32 v1, v8
1732; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v1
1733; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 48, v0
1734; GCN-IR-NEXT:    v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1735; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1736; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1737; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1738; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1739; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1740; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1741; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1742; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1743; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1744; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1745; GCN-IR-NEXT:    s_cbranch_execz .LBB13_6
1746; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1747; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
1748; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
1749; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4]
1750; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v3
1751; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[7:8], v3
1752; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1753; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1754; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1755; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1756; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1757; GCN-IR-NEXT:    s_cbranch_execz .LBB13_5
1758; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1759; GCN-IR-NEXT:    v_lshr_b64 v[9:10], v[7:8], v9
1760; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1761; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1762; GCN-IR-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1763; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1764; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1765; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1766; GCN-IR-NEXT:  .LBB13_3: ; %udiv-do-while
1767; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1768; GCN-IR-NEXT:    v_lshl_b64 v[9:10], v[9:10], 1
1769; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v4
1770; GCN-IR-NEXT:    v_or_b32_e32 v0, v9, v0
1771; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1772; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, s12, v0
1773; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v10, vcc
1774; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1775; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
1776; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1777; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
1778; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
1779; GCN-IR-NEXT:    v_and_b32_e32 v5, 1, v9
1780; GCN-IR-NEXT:    v_and_b32_e32 v9, 0x8000, v9
1781; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
1782; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1783; GCN-IR-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v9
1784; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1785; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1786; GCN-IR-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5]
1787; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1788; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1789; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1790; GCN-IR-NEXT:    s_cbranch_execnz .LBB13_3
1791; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1792; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1793; GCN-IR-NEXT:  .LBB13_5: ; %Flow3
1794; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1795; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1796; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1797; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1798; GCN-IR-NEXT:  .LBB13_6: ; %Flow4
1799; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1800; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v2
1801; GCN-IR-NEXT:    v_xor_b32_e32 v3, v6, v1
1802; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1803; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
1804; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1805  %result = sdiv i64 %x, 32768
1806  ret i64 %result
1807}
1808
1809define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1810; GCN-LABEL: s_test_sdiv24_k_num_i64:
1811; GCN:       ; %bb.0:
1812; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1813; GCN-NEXT:    s_mov_b32 s7, 0xf000
1814; GCN-NEXT:    s_mov_b32 s6, -1
1815; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1816; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1817; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1818; GCN-NEXT:    s_mov_b32 s3, 0x41c00000
1819; GCN-NEXT:    s_mov_b32 s4, s0
1820; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1821; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1822; GCN-NEXT:    s_or_b32 s0, s0, 1
1823; GCN-NEXT:    v_mov_b32_e32 v3, s0
1824; GCN-NEXT:    s_mov_b32 s5, s1
1825; GCN-NEXT:    v_mul_f32_e32 v1, s3, v1
1826; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1827; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s3
1828; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1829; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1830; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1831; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1832; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1833; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1834; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1835; GCN-NEXT:    s_endpgm
1836;
1837; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1838; GCN-IR:       ; %bb.0:
1839; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1840; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1841; GCN-IR-NEXT:    s_mov_b32 s6, -1
1842; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1843; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1844; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1845; GCN-IR-NEXT:    s_mov_b32 s3, 0x41c00000
1846; GCN-IR-NEXT:    s_mov_b32 s4, s0
1847; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1848; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1849; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1850; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
1851; GCN-IR-NEXT:    s_mov_b32 s5, s1
1852; GCN-IR-NEXT:    v_mul_f32_e32 v1, s3, v1
1853; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1854; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s3
1855; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1856; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1857; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1858; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1859; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1860; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1861; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1862; GCN-IR-NEXT:    s_endpgm
1863  %x.shr = ashr i64 %x, 40
1864  %result = sdiv i64 24, %x.shr
1865  store i64 %result, i64 addrspace(1)* %out
1866  ret void
1867}
1868
1869define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1870; GCN-LABEL: s_test_sdiv24_k_den_i64:
1871; GCN:       ; %bb.0:
1872; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1873; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1874; GCN-NEXT:    s_mov_b32 s7, 0xf000
1875; GCN-NEXT:    s_mov_b32 s6, -1
1876; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1877; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1878; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1879; GCN-NEXT:    s_mov_b32 s4, s0
1880; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1881; GCN-NEXT:    s_or_b32 s0, s0, 1
1882; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1883; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1884; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
1885; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1886; GCN-NEXT:    v_mov_b32_e32 v2, s0
1887; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1888; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1889; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1890; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1891; GCN-NEXT:    s_mov_b32 s5, s1
1892; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1893; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1894; GCN-NEXT:    s_endpgm
1895;
1896; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1897; GCN-IR:       ; %bb.0:
1898; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1899; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
1900; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1901; GCN-IR-NEXT:    s_mov_b32 s6, -1
1902; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1903; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1904; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1905; GCN-IR-NEXT:    s_mov_b32 s4, s0
1906; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1907; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1908; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1909; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1910; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
1911; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1912; GCN-IR-NEXT:    v_mov_b32_e32 v2, s0
1913; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1914; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1915; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1916; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1917; GCN-IR-NEXT:    s_mov_b32 s5, s1
1918; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1919; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1920; GCN-IR-NEXT:    s_endpgm
1921  %x.shr = ashr i64 %x, 40
1922  %result = sdiv i64 %x.shr, 23423
1923  store i64 %result, i64 addrspace(1)* %out
1924  ret void
1925}
1926
1927define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
1928; GCN-LABEL: v_test_sdiv24_k_num_i64:
1929; GCN:       ; %bb.0:
1930; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1931; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1932; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1933; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1934; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1935; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1936; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1937; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1938; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1939; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1940; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1941; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1942; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1943; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1944; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1945; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1946; GCN-NEXT:    s_setpc_b64 s[30:31]
1947;
1948; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
1949; GCN-IR:       ; %bb.0:
1950; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1951; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1952; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1953; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1954; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1955; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
1956; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1957; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1958; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1959; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
1960; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
1961; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1962; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1963; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1964; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1965; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1966; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1967  %x.shr = ashr i64 %x, 40
1968  %result = sdiv i64 24, %x.shr
1969  ret i64 %result
1970}
1971
1972define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
1973; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
1974; GCN:       ; %bb.0:
1975; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1976; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1977; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1978; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1979; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1980; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1981; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1982; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1983; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1984; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1985; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1986; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1987; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1988; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1989; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1990; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1991; GCN-NEXT:    s_setpc_b64 s[30:31]
1992;
1993; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
1994; GCN-IR:       ; %bb.0:
1995; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1996; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1997; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1998; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1999; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2000; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2001; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2002; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2003; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2004; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2005; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2006; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2007; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2008; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2009; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2010; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2011; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2012  %x.shr = ashr i64 %x, 40
2013  %result = sdiv i64 32768, %x.shr
2014  ret i64 %result
2015}
2016
2017define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
2018; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
2019; GCN:       ; %bb.0:
2020; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2021; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2022; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2023; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2024; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2025; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
2026; GCN-NEXT:    s_setpc_b64 s[30:31]
2027;
2028; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
2029; GCN-IR:       ; %bb.0:
2030; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2031; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2032; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2033; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2034; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2035; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2036; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
2037; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2038; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
2039; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2040; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2041; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2042; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2043; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2044; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2045; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2046  %x.shr = ashr i64 %x, 40
2047  %result = sdiv i64 %x.shr, 32768
2048  ret i64 %result
2049}
2050