1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_sdiv:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    v_mov_b32_e32 v7, 0
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    s_ashr_i32 s8, s3, 31
14; GCN-NEXT:    s_add_u32 s2, s2, s8
15; GCN-NEXT:    s_mov_b32 s9, s8
16; GCN-NEXT:    s_addc_u32 s3, s3, s8
17; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
18; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s10
19; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s11
20; GCN-NEXT:    s_sub_u32 s4, 0, s10
21; GCN-NEXT:    s_subb_u32 s5, 0, s11
22; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
23; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
24; GCN-NEXT:    v_rcp_f32_e32 v0, v0
25; GCN-NEXT:    v_mov_b32_e32 v1, 0
26; GCN-NEXT:    s_waitcnt lgkmcnt(0)
27; GCN-NEXT:    s_ashr_i32 s12, s3, 31
28; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
29; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
30; GCN-NEXT:    v_trunc_f32_e32 v2, v2
31; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
32; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
33; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
34; GCN-NEXT:    s_add_u32 s2, s2, s12
35; GCN-NEXT:    s_mov_b32 s13, s12
36; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
37; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
38; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
39; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
40; GCN-NEXT:    s_addc_u32 s3, s3, s12
41; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
42; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
43; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
44; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
45; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
46; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
47; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
48; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
49; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
50; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
51; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
52; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
53; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
54; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
55; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
56; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
57; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
58; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
59; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
60; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
61; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
62; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
63; GCN-NEXT:    s_mov_b32 s5, s1
64; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
65; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
66; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
67; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
68; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
69; GCN-NEXT:    v_mul_hi_u32 v10, v0, v3
70; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
71; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
72; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
73; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
74; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v7, v10, vcc
75; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
76; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
77; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v6, vcc
78; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
79; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
80; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
81; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
82; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
83; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
84; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
85; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
86; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
87; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
88; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
89; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
90; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
91; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
92; GCN-NEXT:    s_mov_b32 s4, s0
93; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
94; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
95; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
96; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
97; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
98; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
99; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
100; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
101; GCN-NEXT:    v_mov_b32_e32 v5, s11
102; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
103; GCN-NEXT:    v_mul_lo_u32 v3, s10, v0
104; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
105; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
106; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
107; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
108; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
109; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
110; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
111; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
112; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
113; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
114; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
115; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
116; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
117; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
118; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
119; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
120; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
121; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
122; GCN-NEXT:    v_mov_b32_e32 v6, s3
123; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
124; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
125; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
126; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
127; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
128; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
129; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
130; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
131; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
132; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
133; GCN-NEXT:    s_xor_b64 s[0:1], s[12:13], s[8:9]
134; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
135; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
136; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
137; GCN-NEXT:    v_mov_b32_e32 v2, s1
138; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
139; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
140; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
141; GCN-NEXT:    s_endpgm
142;
143; GCN-IR-LABEL: s_test_sdiv:
144; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
145; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
146; GCN-IR-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
147; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
148; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
149; GCN-IR-NEXT:    s_mov_b32 s1, s0
150; GCN-IR-NEXT:    s_ashr_i32 s2, s9, 31
151; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[0:1], s[6:7]
152; GCN-IR-NEXT:    s_mov_b32 s3, s2
153; GCN-IR-NEXT:    s_sub_u32 s10, s6, s0
154; GCN-IR-NEXT:    s_subb_u32 s11, s7, s0
155; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[8:9]
156; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
157; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
158; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
159; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
160; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
161; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
162; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
163; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
164; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
165; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
166; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
167; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
168; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
169; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
170; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
171; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
172; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
173; GCN-IR-NEXT:    s_mov_b32 s15, 0
174; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
175; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
176; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
177; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
178; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
179; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
180; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
181; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
182; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
183; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
184; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
185; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
186; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
187; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
188; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
189; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
190; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
191; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
192; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
193; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
194; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
195; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
196; GCN-IR-NEXT:    s_mov_b32 s17, s15
197; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
198; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
199; GCN-IR-NEXT:    s_mov_b32 s9, 0
200; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
201; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
202; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
203; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
204; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
205; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
206; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
207; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
208; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
209; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
210; GCN-IR-NEXT:    s_mov_b32 s15, s14
211; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
212; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
213; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
214; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
215; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
216; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
217; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
218; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
219; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
220; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
221; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
222; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
223; GCN-IR-NEXT:  BB0_4: ; %Flow6
224; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
225; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
226; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
227; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
228; GCN-IR-NEXT:    s_branch BB0_6
229; GCN-IR-NEXT:  BB0_5:
230; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
231; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
232; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
233; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
234; GCN-IR-NEXT:  BB0_6: ; %udiv-end
235; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
236; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
237; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
238; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
239; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
240; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
241; GCN-IR-NEXT:    s_mov_b32 s6, -1
242; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
243; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
244; GCN-IR-NEXT:    s_endpgm
245  %result = sdiv i64 %x, %y
246  store i64 %result, i64 addrspace(1)* %out
247  ret void
248}
249
250define i64 @v_test_sdiv(i64 %x, i64 %y) {
251; GCN-LABEL: v_test_sdiv:
252; GCN:       ; %bb.0:
253; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
254; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
255; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
256; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
257; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
258; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
259; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
260; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
261; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
262; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
263; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
264; GCN-NEXT:    v_rcp_f32_e32 v5, v5
265; GCN-NEXT:    v_mov_b32_e32 v15, 0
266; GCN-NEXT:    v_mov_b32_e32 v14, 0
267; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
268; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
269; GCN-NEXT:    v_trunc_f32_e32 v6, v6
270; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
271; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
272; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
273; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
274; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
275; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
276; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
277; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
278; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
279; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
280; GCN-NEXT:    v_mul_hi_u32 v13, v5, v10
281; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
282; GCN-NEXT:    v_mul_hi_u32 v16, v6, v9
283; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
284; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
285; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
286; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
287; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v11, vcc
288; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
289; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v10, vcc
290; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v16, v14, vcc
291; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
292; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v11, vcc
293; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
294; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v10, vcc
295; GCN-NEXT:    v_mul_lo_u32 v9, v7, v6
296; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
297; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
298; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
299; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
300; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
301; GCN-NEXT:    v_mul_lo_u32 v11, v5, v8
302; GCN-NEXT:    v_mul_hi_u32 v12, v5, v7
303; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
304; GCN-NEXT:    v_mul_hi_u32 v10, v6, v7
305; GCN-NEXT:    v_mul_lo_u32 v7, v6, v7
306; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
307; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
308; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v15, v13, vcc
309; GCN-NEXT:    v_mul_lo_u32 v8, v6, v8
310; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
311; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v10, vcc
312; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v14, vcc
313; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
314; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v15, v9, vcc
315; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
316; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
317; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
318; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
319; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
320; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
321; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
322; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
323; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
324; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
325; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
326; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v15, v10, vcc
327; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
328; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
329; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
330; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
331; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
332; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
333; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
334; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
335; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v8, vcc
336; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
337; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
338; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
339; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
340; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
341; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
342; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
343; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
344; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
345; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
346; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
347; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
348; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
349; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
350; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
351; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
352; GCN-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
353; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 2, v5
354; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
355; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
356; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
357; GCN-NEXT:    v_add_i32_e64 v12, s[4:5], 1, v5
358; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
359; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
360; GCN-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
361; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
362; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
363; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
364; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
365; GCN-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
366; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
367; GCN-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
368; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
369; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
370; GCN-NEXT:    v_xor_b32_e32 v2, v7, v4
371; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
372; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
373; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
374; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
375; GCN-NEXT:    s_setpc_b64 s[30:31]
376;
377; GCN-IR-LABEL: v_test_sdiv:
378; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
379; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
380; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
381; GCN-IR-NEXT:    v_xor_b32_e32 v0, v4, v0
382; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
383; GCN-IR-NEXT:    v_xor_b32_e32 v1, v4, v1
384; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v0, v4
385; GCN-IR-NEXT:    v_subb_u32_e32 v12, vcc, v1, v4, vcc
386; GCN-IR-NEXT:    v_xor_b32_e32 v1, v5, v2
387; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v3
388; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
389; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v0, v5, vcc
390; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
391; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[11:12]
392; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v2
393; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
394; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
395; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v3
396; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v7
397; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v11
398; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
399; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v12
400; GCN-IR-NEXT:    v_min_u32_e32 v13, v7, v8
401; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v13
402; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
403; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
404; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
405; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
406; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
407; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
408; GCN-IR-NEXT:    v_mov_b32_e32 v6, v4
409; GCN-IR-NEXT:    v_mov_b32_e32 v1, v5
410; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v12, 0, s[6:7]
411; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
412; GCN-IR-NEXT:    v_mov_b32_e32 v16, v17
413; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v11, 0, s[6:7]
414; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
415; GCN-IR-NEXT:    s_cbranch_execz BB1_6
416; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
417; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
418; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
419; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
420; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
421; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[11:12], v7
422; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
423; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
424; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
425; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
426; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
427; GCN-IR-NEXT:    s_cbranch_execz BB1_5
428; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
429; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v2
430; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v3, vcc
431; GCN-IR-NEXT:    v_not_b32_e32 v0, v0
432; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[11:12], v14
433; GCN-IR-NEXT:    v_not_b32_e32 v9, v17
434; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v0, v13
435; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v16, vcc
436; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
437; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
438; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
439; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
440; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
441; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
442; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v8
443; GCN-IR-NEXT:    v_or_b32_e32 v0, v14, v0
444; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
445; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v0
446; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
447; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
448; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v11
449; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
450; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
451; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v12, vcc
452; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
453; GCN-IR-NEXT:    v_and_b32_e32 v20, v13, v3
454; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v2
455; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
456; GCN-IR-NEXT:    v_mov_b32_e32 v11, v16
457; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v0, v13
458; GCN-IR-NEXT:    v_mov_b32_e32 v12, v17
459; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
460; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
461; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
462; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
463; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
464; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
465; GCN-IR-NEXT:  ; %bb.4: ; %Flow
466; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
467; GCN-IR-NEXT:  BB1_5: ; %Flow3
468; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
469; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[7:8], 1
470; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v3
471; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v2
472; GCN-IR-NEXT:  BB1_6: ; %Flow4
473; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
474; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v4
475; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v6
476; GCN-IR-NEXT:    v_xor_b32_e32 v3, v9, v0
477; GCN-IR-NEXT:    v_xor_b32_e32 v2, v10, v1
478; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
479; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
480; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
481  %result = sdiv i64 %x, %y
482  ret i64 %result
483}
484
485define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
486; GCN-LABEL: s_test_sdiv24_64:
487; GCN:       ; %bb.0:
488; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
489; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
490; GCN-NEXT:    s_mov_b32 s3, 0xf000
491; GCN-NEXT:    s_mov_b32 s2, -1
492; GCN-NEXT:    s_waitcnt lgkmcnt(0)
493; GCN-NEXT:    s_mov_b32 s0, s4
494; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
495; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
496; GCN-NEXT:    s_mov_b32 s1, s5
497; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
498; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
499; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
500; GCN-NEXT:    s_xor_b32 s4, s4, s8
501; GCN-NEXT:    s_ashr_i32 s4, s4, 30
502; GCN-NEXT:    s_or_b32 s4, s4, 1
503; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
504; GCN-NEXT:    v_trunc_f32_e32 v2, v2
505; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
506; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
507; GCN-NEXT:    v_mov_b32_e32 v3, s4
508; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
509; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
510; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
511; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
512; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
513; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
514; GCN-NEXT:    s_endpgm
515;
516; GCN-IR-LABEL: s_test_sdiv24_64:
517; GCN-IR:       ; %bb.0:
518; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
519; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
520; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
521; GCN-IR-NEXT:    s_mov_b32 s2, -1
522; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
523; GCN-IR-NEXT:    s_mov_b32 s0, s4
524; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
525; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
526; GCN-IR-NEXT:    s_mov_b32 s1, s5
527; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
528; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
529; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
530; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
531; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
532; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
533; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
534; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
535; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
536; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
537; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
538; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
539; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
540; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
541; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
542; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
543; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
544; GCN-IR-NEXT:    s_endpgm
545  %1 = ashr i64 %x, 40
546  %2 = ashr i64 %y, 40
547  %result = sdiv i64 %1, %2
548  store i64 %result, i64 addrspace(1)* %out
549  ret void
550}
551
552define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
553; GCN-LABEL: v_test_sdiv24_64:
554; GCN:       ; %bb.0:
555; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
556; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
557; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
558; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
559; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
560; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
561; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
562; GCN-NEXT:    v_trunc_f32_e32 v2, v2
563; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
564; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
565; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
566; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
567; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
568; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
569; GCN-NEXT:    s_setpc_b64 s[30:31]
570;
571; GCN-IR-LABEL: v_test_sdiv24_64:
572; GCN-IR:       ; %bb.0:
573; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
574; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
575; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, v0
576; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
577; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v1
578; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
579; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
580; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
581; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
582; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
583; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
584; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
585; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
586; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
587; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
588  %1 = lshr i64 %x, 40
589  %2 = lshr i64 %y, 40
590  %result = sdiv i64 %1, %2
591  ret i64 %result
592}
593
594define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
595; GCN-LABEL: s_test_sdiv32_64:
596; GCN:       ; %bb.0:
597; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
598; GCN-NEXT:    s_waitcnt lgkmcnt(0)
599; GCN-NEXT:    s_load_dword s6, s[0:1], 0xe
600; GCN-NEXT:    s_mov_b32 s3, 0xf000
601; GCN-NEXT:    s_mov_b32 s2, -1
602; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
603; GCN-NEXT:    s_waitcnt lgkmcnt(0)
604; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
605; GCN-NEXT:    s_mov_b32 s0, s4
606; GCN-NEXT:    s_xor_b32 s4, s7, s6
607; GCN-NEXT:    s_ashr_i32 s4, s4, 30
608; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
609; GCN-NEXT:    s_or_b32 s4, s4, 1
610; GCN-NEXT:    v_mov_b32_e32 v3, s4
611; GCN-NEXT:    s_mov_b32 s1, s5
612; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
613; GCN-NEXT:    v_trunc_f32_e32 v2, v2
614; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
615; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
616; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
617; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
618; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
619; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
620; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
621; GCN-NEXT:    s_endpgm
622;
623; GCN-IR-LABEL: s_test_sdiv32_64:
624; GCN-IR:       ; %bb.0:
625; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
626; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
627; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xe
628; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
629; GCN-IR-NEXT:    s_mov_b32 s2, -1
630; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
631; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
632; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
633; GCN-IR-NEXT:    s_mov_b32 s0, s4
634; GCN-IR-NEXT:    s_xor_b32 s4, s7, s6
635; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
636; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
637; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
638; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
639; GCN-IR-NEXT:    s_mov_b32 s1, s5
640; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
641; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
642; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
643; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
644; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
645; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
646; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
647; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
648; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
649; GCN-IR-NEXT:    s_endpgm
650  %1 = ashr i64 %x, 32
651  %2 = ashr i64 %y, 32
652  %result = sdiv i64 %1, %2
653  store i64 %result, i64 addrspace(1)* %out
654  ret void
655}
656
657define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
658; GCN-LABEL: s_test_sdiv31_64:
659; GCN:       ; %bb.0:
660; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
661; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
662; GCN-NEXT:    s_mov_b32 s3, 0xf000
663; GCN-NEXT:    s_mov_b32 s2, -1
664; GCN-NEXT:    s_waitcnt lgkmcnt(0)
665; GCN-NEXT:    s_mov_b32 s0, s4
666; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
667; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
668; GCN-NEXT:    s_mov_b32 s1, s5
669; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
670; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
671; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
672; GCN-NEXT:    s_xor_b32 s4, s4, s8
673; GCN-NEXT:    s_ashr_i32 s4, s4, 30
674; GCN-NEXT:    s_or_b32 s4, s4, 1
675; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
676; GCN-NEXT:    v_trunc_f32_e32 v2, v2
677; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
678; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
679; GCN-NEXT:    v_mov_b32_e32 v3, s4
680; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
681; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
682; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
683; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
684; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
685; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
686; GCN-NEXT:    s_endpgm
687;
688; GCN-IR-LABEL: s_test_sdiv31_64:
689; GCN-IR:       ; %bb.0:
690; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
691; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
692; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
693; GCN-IR-NEXT:    s_mov_b32 s2, -1
694; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
695; GCN-IR-NEXT:    s_mov_b32 s0, s4
696; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
697; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
698; GCN-IR-NEXT:    s_mov_b32 s1, s5
699; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
700; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
701; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
702; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
703; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
704; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
705; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
706; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
707; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
708; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
709; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
710; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
711; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
712; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
713; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
714; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
715; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
716; GCN-IR-NEXT:    s_endpgm
717  %1 = ashr i64 %x, 33
718  %2 = ashr i64 %y, 33
719  %result = sdiv i64 %1, %2
720  store i64 %result, i64 addrspace(1)* %out
721  ret void
722}
723
724define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
725; GCN-LABEL: s_test_sdiv23_64:
726; GCN:       ; %bb.0:
727; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
728; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
729; GCN-NEXT:    s_mov_b32 s3, 0xf000
730; GCN-NEXT:    s_mov_b32 s2, -1
731; GCN-NEXT:    s_waitcnt lgkmcnt(0)
732; GCN-NEXT:    s_mov_b32 s0, s4
733; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
734; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
735; GCN-NEXT:    s_mov_b32 s1, s5
736; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
737; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
738; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
739; GCN-NEXT:    s_xor_b32 s4, s4, s8
740; GCN-NEXT:    s_ashr_i32 s4, s4, 30
741; GCN-NEXT:    s_or_b32 s4, s4, 1
742; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
743; GCN-NEXT:    v_trunc_f32_e32 v2, v2
744; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
745; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
746; GCN-NEXT:    v_mov_b32_e32 v3, s4
747; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
748; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
749; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
750; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
751; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
752; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
753; GCN-NEXT:    s_endpgm
754;
755; GCN-IR-LABEL: s_test_sdiv23_64:
756; GCN-IR:       ; %bb.0:
757; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
758; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
759; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
760; GCN-IR-NEXT:    s_mov_b32 s2, -1
761; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
762; GCN-IR-NEXT:    s_mov_b32 s0, s4
763; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
764; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
765; GCN-IR-NEXT:    s_mov_b32 s1, s5
766; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
767; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
768; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
769; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
770; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
771; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
772; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
773; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
774; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
775; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
776; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
777; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
778; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
779; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
780; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
781; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
782; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
783; GCN-IR-NEXT:    s_endpgm
784  %1 = ashr i64 %x, 41
785  %2 = ashr i64 %y, 41
786  %result = sdiv i64 %1, %2
787  store i64 %result, i64 addrspace(1)* %out
788  ret void
789}
790
791define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
792; GCN-LABEL: s_test_sdiv25_64:
793; GCN:       ; %bb.0:
794; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
795; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
796; GCN-NEXT:    s_mov_b32 s3, 0xf000
797; GCN-NEXT:    s_mov_b32 s2, -1
798; GCN-NEXT:    s_waitcnt lgkmcnt(0)
799; GCN-NEXT:    s_mov_b32 s0, s4
800; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
801; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
802; GCN-NEXT:    s_mov_b32 s1, s5
803; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
804; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
805; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
806; GCN-NEXT:    s_xor_b32 s4, s4, s8
807; GCN-NEXT:    s_ashr_i32 s4, s4, 30
808; GCN-NEXT:    s_or_b32 s4, s4, 1
809; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
810; GCN-NEXT:    v_trunc_f32_e32 v2, v2
811; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
812; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
813; GCN-NEXT:    v_mov_b32_e32 v3, s4
814; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
815; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
816; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
817; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
818; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
819; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
820; GCN-NEXT:    s_endpgm
821;
822; GCN-IR-LABEL: s_test_sdiv25_64:
823; GCN-IR:       ; %bb.0:
824; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
825; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
826; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
827; GCN-IR-NEXT:    s_mov_b32 s2, -1
828; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
829; GCN-IR-NEXT:    s_mov_b32 s0, s4
830; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
831; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
832; GCN-IR-NEXT:    s_mov_b32 s1, s5
833; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
834; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
835; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
836; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
837; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
838; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
839; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
840; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
841; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
842; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
843; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
844; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
845; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
846; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
847; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
848; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
849; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
850; GCN-IR-NEXT:    s_endpgm
851  %1 = ashr i64 %x, 39
852  %2 = ashr i64 %y, 39
853  %result = sdiv i64 %1, %2
854  store i64 %result, i64 addrspace(1)* %out
855  ret void
856}
857
858define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
859; GCN-LABEL: s_test_sdiv24_v2i64:
860; GCN:       ; %bb.0:
861; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
862; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
863; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
864; GCN-NEXT:    s_mov_b32 s7, 0xf000
865; GCN-NEXT:    s_mov_b32 s6, -1
866; GCN-NEXT:    s_waitcnt lgkmcnt(0)
867; GCN-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
868; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
869; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
870; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s8
871; GCN-NEXT:    s_xor_b32 s0, s8, s0
872; GCN-NEXT:    s_ashr_i32 s0, s0, 30
873; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
874; GCN-NEXT:    s_or_b32 s0, s0, 1
875; GCN-NEXT:    v_mov_b32_e32 v3, s0
876; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
877; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
878; GCN-NEXT:    v_trunc_f32_e32 v2, v2
879; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
880; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
881; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
882; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
883; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
884; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
885; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s2
886; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s10
887; GCN-NEXT:    s_xor_b32 s0, s10, s2
888; GCN-NEXT:    s_ashr_i32 s0, s0, 30
889; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
890; GCN-NEXT:    s_or_b32 s0, s0, 1
891; GCN-NEXT:    v_mov_b32_e32 v5, s0
892; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
893; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
894; GCN-NEXT:    v_trunc_f32_e32 v4, v4
895; GCN-NEXT:    v_mad_f32 v3, -v4, v2, v3
896; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
897; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
898; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
899; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
900; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
901; GCN-NEXT:    v_bfe_i32 v2, v2, 0, 24
902; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
903; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
904; GCN-NEXT:    s_endpgm
905;
906; GCN-IR-LABEL: s_test_sdiv24_v2i64:
907; GCN-IR:       ; %bb.0:
908; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
909; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
910; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
911; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
912; GCN-IR-NEXT:    s_mov_b32 s6, -1
913; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
914; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
915; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
916; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
917; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s8
918; GCN-IR-NEXT:    s_xor_b32 s0, s8, s0
919; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
920; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
921; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
922; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
923; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
924; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
925; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
926; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
927; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
928; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
929; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
930; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
931; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
932; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v2, s2
933; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, s10
934; GCN-IR-NEXT:    s_xor_b32 s0, s10, s2
935; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
936; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v2
937; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
938; GCN-IR-NEXT:    v_mov_b32_e32 v5, s0
939; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
940; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
941; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
942; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v2, v3
943; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
944; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
945; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
946; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
947; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
948; GCN-IR-NEXT:    v_bfe_i32 v2, v2, 0, 24
949; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
950; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
951; GCN-IR-NEXT:    s_endpgm
952  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
953  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
954  %result = sdiv <2 x i64> %1, %2
955  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
956  ret void
957}
958
959define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
960; GCN-LABEL: s_test_sdiv24_48:
961; GCN:       ; %bb.0:
962; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
963; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
964; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
965; GCN-NEXT:    s_load_dword s8, s[0:1], 0xd
966; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
967; GCN-NEXT:    s_mov_b32 s7, 0xf000
968; GCN-NEXT:    s_waitcnt lgkmcnt(0)
969; GCN-NEXT:    v_mov_b32_e32 v2, s2
970; GCN-NEXT:    s_sext_i32_i16 s1, s3
971; GCN-NEXT:    v_mov_b32_e32 v0, s8
972; GCN-NEXT:    s_sext_i32_i16 s0, s0
973; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
974; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
975; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
976; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
977; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
978; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
979; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
980; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
981; GCN-NEXT:    s_mov_b32 s6, -1
982; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
983; GCN-NEXT:    v_trunc_f32_e32 v2, v2
984; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
985; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
986; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
987; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
988; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
989; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
990; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
991; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
992; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
993; GCN-NEXT:    s_endpgm
994;
995; GCN-IR-LABEL: s_test_sdiv24_48:
996; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
997; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
998; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
999; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1000; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
1001; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
1002; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1003; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1004; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[2:3], 24
1005; GCN-IR-NEXT:    s_sext_i32_i16 s7, s0
1006; GCN-IR-NEXT:    s_ashr_i32 s0, s3, 31
1007; GCN-IR-NEXT:    s_mov_b32 s1, s0
1008; GCN-IR-NEXT:    s_ashr_i64 s[12:13], s[6:7], 24
1009; GCN-IR-NEXT:    s_ashr_i32 s2, s7, 31
1010; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]
1011; GCN-IR-NEXT:    s_mov_b32 s3, s2
1012; GCN-IR-NEXT:    s_sub_u32 s10, s6, s0
1013; GCN-IR-NEXT:    s_subb_u32 s11, s7, s0
1014; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[12:13]
1015; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
1016; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
1017; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
1018; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
1019; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1020; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
1021; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
1022; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1023; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
1024; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1025; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
1026; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1027; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
1028; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
1029; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
1030; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1031; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
1032; GCN-IR-NEXT:    s_mov_b32 s15, 0
1033; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
1034; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
1035; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
1036; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
1037; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1038; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1039; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1040; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
1041; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1042; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
1043; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1044; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
1045; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1046; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1047; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
1048; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1049; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1050; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
1051; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
1052; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
1053; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
1054; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
1055; GCN-IR-NEXT:    s_mov_b32 s17, s15
1056; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
1057; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1058; GCN-IR-NEXT:    s_mov_b32 s9, 0
1059; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1060; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1061; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
1062; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1063; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1064; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1065; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1066; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
1067; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
1068; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1069; GCN-IR-NEXT:    s_mov_b32 s15, s14
1070; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1071; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
1072; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
1073; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1074; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
1075; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1076; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1077; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1078; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1079; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1080; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1081; GCN-IR-NEXT:    s_cbranch_vccz BB9_3
1082; GCN-IR-NEXT:  BB9_4: ; %Flow3
1083; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
1084; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1085; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1086; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1087; GCN-IR-NEXT:    s_branch BB9_6
1088; GCN-IR-NEXT:  BB9_5:
1089; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
1090; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
1091; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1092; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
1093; GCN-IR-NEXT:  BB9_6: ; %udiv-end
1094; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
1095; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1096; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1097; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1098; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1099; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1100; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1101; GCN-IR-NEXT:    s_mov_b32 s6, -1
1102; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1103; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1104; GCN-IR-NEXT:    s_endpgm
1105  %1 = ashr i48 %x, 24
1106  %2 = ashr i48 %y, 24
1107  %result = sdiv i48 %1, %2
1108  store i48 %result, i48 addrspace(1)* %out
1109  ret void
1110}
1111
1112define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1113; GCN-LABEL: s_test_sdiv_k_num_i64:
1114; GCN:       ; %bb.0:
1115; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1116; GCN-NEXT:    v_mov_b32_e32 v2, 0
1117; GCN-NEXT:    s_mov_b32 s7, 0xf000
1118; GCN-NEXT:    s_mov_b32 s6, -1
1119; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1120; GCN-NEXT:    s_ashr_i32 s8, s3, 31
1121; GCN-NEXT:    s_add_u32 s2, s2, s8
1122; GCN-NEXT:    s_mov_b32 s9, s8
1123; GCN-NEXT:    s_addc_u32 s3, s3, s8
1124; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
1125; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1126; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
1127; GCN-NEXT:    s_sub_u32 s4, 0, s2
1128; GCN-NEXT:    s_subb_u32 s5, 0, s3
1129; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1130; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1131; GCN-NEXT:    v_mov_b32_e32 v1, 0
1132; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1133; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1134; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1135; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1136; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1137; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1138; GCN-NEXT:    v_mul_lo_u32 v4, s4, v3
1139; GCN-NEXT:    v_mul_hi_u32 v5, s4, v0
1140; GCN-NEXT:    v_mul_lo_u32 v7, s5, v0
1141; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
1142; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1143; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1144; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1145; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1146; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1147; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1148; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1149; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1150; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1151; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1152; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1153; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
1154; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1155; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
1156; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1157; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1158; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1159; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1160; GCN-NEXT:    v_mul_lo_u32 v4, s4, v3
1161; GCN-NEXT:    v_mul_hi_u32 v5, s4, v0
1162; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
1163; GCN-NEXT:    s_mov_b32 s5, s1
1164; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1165; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
1166; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
1167; GCN-NEXT:    v_mul_lo_u32 v8, v0, v4
1168; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
1169; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
1170; GCN-NEXT:    v_mul_hi_u32 v7, v3, v5
1171; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1172; GCN-NEXT:    v_mul_hi_u32 v6, v3, v4
1173; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1174; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v2, v10, vcc
1175; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1176; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1177; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v7, vcc
1178; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
1179; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1180; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1181; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1182; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
1183; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
1184; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1185; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1186; GCN-NEXT:    v_mov_b32_e32 v5, s3
1187; GCN-NEXT:    s_mov_b32 s4, s0
1188; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1189; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
1190; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0
1191; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
1192; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1193; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
1194; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
1195; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
1196; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
1197; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
1198; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
1199; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
1200; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
1201; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
1202; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1203; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
1204; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
1205; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
1206; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1]
1207; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
1208; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1209; GCN-NEXT:    v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1210; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
1211; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
1212; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1213; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
1214; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1215; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
1216; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v3, vcc
1217; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
1218; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1219; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
1220; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
1221; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1222; GCN-NEXT:    v_xor_b32_e32 v0, s8, v0
1223; GCN-NEXT:    v_xor_b32_e32 v1, s8, v1
1224; GCN-NEXT:    v_mov_b32_e32 v2, s8
1225; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
1226; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1227; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1228; GCN-NEXT:    s_endpgm
1229;
1230; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1231; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1232; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1233; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1234; GCN-IR-NEXT:    s_ashr_i32 s4, s3, 31
1235; GCN-IR-NEXT:    s_mov_b32 s5, s4
1236; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1237; GCN-IR-NEXT:    s_sub_u32 s2, s2, s4
1238; GCN-IR-NEXT:    s_subb_u32 s3, s3, s4
1239; GCN-IR-NEXT:    s_flbit_i32_b32 s6, s2
1240; GCN-IR-NEXT:    s_add_i32 s6, s6, 32
1241; GCN-IR-NEXT:    s_flbit_i32_b32 s7, s3
1242; GCN-IR-NEXT:    s_min_u32 s8, s6, s7
1243; GCN-IR-NEXT:    s_add_u32 s10, s8, 0xffffffc5
1244; GCN-IR-NEXT:    s_addc_u32 s11, 0, -1
1245; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1246; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[14:15], s[10:11], 63
1247; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1248; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
1249; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[14:15], s[10:11], 63
1250; GCN-IR-NEXT:    s_xor_b64 s[16:17], s[12:13], -1
1251; GCN-IR-NEXT:    s_and_b64 s[14:15], s[16:17], s[14:15]
1252; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
1253; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1254; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1255; GCN-IR-NEXT:    s_add_u32 s12, s10, 1
1256; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1257; GCN-IR-NEXT:    s_addc_u32 s13, s11, 0
1258; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1259; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1260; GCN-IR-NEXT:    s_sub_i32 s9, 63, s10
1261; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1262; GCN-IR-NEXT:    s_lshl_b64 s[10:11], 24, s9
1263; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1264; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1265; GCN-IR-NEXT:    s_lshr_b64 s[14:15], 24, s12
1266; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
1267; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
1268; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1269; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1270; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1271; GCN-IR-NEXT:    s_mov_b32 s7, 0
1272; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1273; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1274; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1275; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
1276; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1277; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
1278; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
1279; GCN-IR-NEXT:    s_sub_u32 s6, s16, s14
1280; GCN-IR-NEXT:    s_subb_u32 s6, s17, s15
1281; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
1282; GCN-IR-NEXT:    s_mov_b32 s13, s12
1283; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
1284; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[2:3]
1285; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
1286; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1287; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
1288; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1289; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1290; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1291; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
1292; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
1293; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1294; GCN-IR-NEXT:    s_cbranch_vccz BB10_3
1295; GCN-IR-NEXT:  BB10_4: ; %Flow5
1296; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[10:11], 1
1297; GCN-IR-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
1298; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1299; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1300; GCN-IR-NEXT:    s_branch BB10_6
1301; GCN-IR-NEXT:  BB10_5:
1302; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1303; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[12:13]
1304; GCN-IR-NEXT:  BB10_6: ; %udiv-end
1305; GCN-IR-NEXT:    v_xor_b32_e32 v0, s4, v0
1306; GCN-IR-NEXT:    v_xor_b32_e32 v1, s5, v1
1307; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1308; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
1309; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1310; GCN-IR-NEXT:    s_mov_b32 s2, -1
1311; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1312; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1313; GCN-IR-NEXT:    s_endpgm
1314  %result = sdiv i64 24, %x
1315  store i64 %result, i64 addrspace(1)* %out
1316  ret void
1317}
1318
1319define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1320; GCN-LABEL: v_test_sdiv_k_num_i64:
1321; GCN:       ; %bb.0:
1322; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1323; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1324; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1325; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1326; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1327; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1328; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1329; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1330; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1331; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1332; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1333; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1334; GCN-NEXT:    v_mov_b32_e32 v13, 0
1335; GCN-NEXT:    v_mov_b32_e32 v12, 0
1336; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1337; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1338; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1339; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1340; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1341; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1342; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1343; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1344; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1345; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1346; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1347; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1348; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1349; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1350; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1351; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1352; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1353; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1354; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1355; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1356; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1357; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1358; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1359; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1360; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1361; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1362; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1363; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1364; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1365; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1366; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1367; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1368; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1369; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1370; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1371; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1372; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1373; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1374; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1375; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1376; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1377; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v13, v11, vcc
1378; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1379; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1380; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1381; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1382; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1383; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1384; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1385; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
1386; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
1387; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1388; GCN-NEXT:    v_mul_hi_u32 v4, v4, 24
1389; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1390; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v13, v4, vcc
1391; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1392; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1393; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1394; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1395; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1396; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 24, v5
1397; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1398; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1399; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1400; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1401; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1402; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1403; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1404; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1405; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1406; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1407; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, v13, s[4:5]
1408; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1409; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, v13, s[4:5]
1410; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1411; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1412; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1413; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1414; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1415; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1416; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1417; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1418; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1419; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1420; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1421; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1422; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1423; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1424; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1425; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1426; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1427; GCN-NEXT:    s_setpc_b64 s[30:31]
1428;
1429; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1430; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1431; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1432; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1433; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1434; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1435; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1436; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1437; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1438; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1439; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1440; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1441; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1442; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1443; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1444; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1445; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1446; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1447; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1448; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1449; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, 24, 0, s[4:5]
1450; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1451; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1452; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1453; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1454; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1455; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1456; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1457; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1458; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1459; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1460; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1461; GCN-IR-NEXT:    v_lshl_b64 v[4:5], 24, v4
1462; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1463; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1464; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1465; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1466; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1467; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1468; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1469; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1470; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1471; GCN-IR-NEXT:    v_lshr_b64 v[10:11], 24, v10
1472; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 58, v8
1473; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1474; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1475; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1476; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1477; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1478; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1479; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1480; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1481; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1482; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1483; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1484; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1485; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1486; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1487; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1488; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1489; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1490; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1491; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1492; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1493; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1494; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1495; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1496; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1497; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1498; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1499; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1500; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1501; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1502; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1503; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1504; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1505; GCN-IR-NEXT:  BB11_5: ; %Flow3
1506; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1507; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1508; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1509; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1510; GCN-IR-NEXT:  BB11_6: ; %Flow4
1511; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1512; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1513; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1514; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1515; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1516; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1517  %result = sdiv i64 24, %x
1518  ret i64 %result
1519}
1520
1521define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1522; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1523; GCN:       ; %bb.0:
1524; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1525; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1526; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1527; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1528; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1529; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1530; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1531; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1532; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1533; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1534; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1535; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1536; GCN-NEXT:    v_mov_b32_e32 v13, 0
1537; GCN-NEXT:    v_mov_b32_e32 v12, 0
1538; GCN-NEXT:    s_mov_b32 s4, 0x8000
1539; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1540; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1541; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1542; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1543; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1544; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1545; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1546; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1547; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1548; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1549; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1550; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1551; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1552; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1553; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1554; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1555; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1556; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1557; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1558; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1559; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1560; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1561; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1562; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1563; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1564; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1565; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1566; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1567; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1568; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1569; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1570; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1571; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1572; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1573; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1574; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1575; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1576; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1577; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1578; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1579; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1580; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v13, v11, vcc
1581; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1582; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1583; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1584; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1585; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1586; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1587; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1588; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
1589; GCN-NEXT:    v_lshrrev_b32_e32 v5, 17, v4
1590; GCN-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
1591; GCN-NEXT:    v_lshrrev_b32_e32 v3, 17, v3
1592; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
1593; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v13, v5, vcc
1594; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1595; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1596; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1597; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1598; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1599; GCN-NEXT:    v_sub_i32_e32 v5, vcc, s4, v5
1600; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1601; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1602; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1603; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1604; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1605; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1606; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1607; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1608; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1609; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1610; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, v13, s[4:5]
1611; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1612; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, v13, s[4:5]
1613; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1614; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1615; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1616; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1617; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1618; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1619; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1620; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1621; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1622; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1623; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1624; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1625; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1626; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1627; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1628; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1629; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1630; GCN-NEXT:    s_setpc_b64 s[30:31]
1631;
1632; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1633; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1634; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1635; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1636; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1637; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1638; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1639; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1640; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1641; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1642; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1643; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1644; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1645; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1646; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1647; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1648; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1649; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1650; GCN-IR-NEXT:    v_mov_b32_e32 v6, s8
1651; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1652; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1653; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1654; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[4:5]
1655; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1656; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1657; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1658; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1659; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1660; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1661; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1662; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1663; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1664; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1665; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1666; GCN-IR-NEXT:    v_lshl_b64 v[4:5], s[8:9], v4
1667; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1668; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1669; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1670; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1671; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1672; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1673; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1674; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1675; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1676; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1677; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v10
1678; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1679; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1680; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1681; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1682; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1683; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1684; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1685; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1686; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1687; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1688; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1689; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1690; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1691; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1692; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1693; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1694; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1695; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1696; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1697; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1698; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1699; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1700; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1701; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1702; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1703; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1704; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1705; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1706; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1707; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1708; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1709; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1710; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1711; GCN-IR-NEXT:  BB12_5: ; %Flow3
1712; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1713; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1714; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1715; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1716; GCN-IR-NEXT:  BB12_6: ; %Flow4
1717; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1718; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1719; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1720; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1721; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1722; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1723  %result = sdiv i64 32768, %x
1724  ret i64 %result
1725}
1726
1727define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1728; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1729; GCN:       ; %bb.0:
1730; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1731; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1732; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1733; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1734; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1735; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1736; GCN-NEXT:    s_setpc_b64 s[30:31]
1737;
1738; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1739; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1740; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1741; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1742; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1743; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1744; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v2
1745; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v1, v2, vcc
1746; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v7
1747; GCN-IR-NEXT:    v_add_i32_e64 v0, s[4:5], 32, v0
1748; GCN-IR-NEXT:    v_ffbh_u32_e32 v1, v8
1749; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v1
1750; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 48, v0
1751; GCN-IR-NEXT:    v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1752; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1753; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1754; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1755; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1756; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1757; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1758; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1759; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1760; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1761; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1762; GCN-IR-NEXT:    s_cbranch_execz BB13_6
1763; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1764; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
1765; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
1766; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4]
1767; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v3
1768; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[7:8], v3
1769; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1770; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1771; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1772; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1773; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1774; GCN-IR-NEXT:    s_cbranch_execz BB13_5
1775; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1776; GCN-IR-NEXT:    v_lshr_b64 v[9:10], v[7:8], v9
1777; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1778; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1779; GCN-IR-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1780; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1781; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1782; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1783; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
1784; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1785; GCN-IR-NEXT:    v_lshl_b64 v[9:10], v[9:10], 1
1786; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v4
1787; GCN-IR-NEXT:    v_or_b32_e32 v0, v9, v0
1788; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1789; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, s12, v0
1790; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v10, vcc
1791; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1792; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
1793; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1794; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
1795; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
1796; GCN-IR-NEXT:    v_and_b32_e32 v5, 1, v9
1797; GCN-IR-NEXT:    v_and_b32_e32 v9, 0x8000, v9
1798; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
1799; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1800; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1801; GCN-IR-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v9
1802; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1803; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1804; GCN-IR-NEXT:    v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5]
1805; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1806; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1807; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1808; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
1809; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1810; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1811; GCN-IR-NEXT:  BB13_5: ; %Flow3
1812; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1813; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1814; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1815; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1816; GCN-IR-NEXT:  BB13_6: ; %Flow4
1817; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1818; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v2
1819; GCN-IR-NEXT:    v_xor_b32_e32 v3, v6, v1
1820; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1821; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
1822; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1823  %result = sdiv i64 %x, 32768
1824  ret i64 %result
1825}
1826
1827define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1828; GCN-LABEL: s_test_sdiv24_k_num_i64:
1829; GCN:       ; %bb.0:
1830; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1831; GCN-NEXT:    s_mov_b32 s7, 0xf000
1832; GCN-NEXT:    s_mov_b32 s6, -1
1833; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1834; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1835; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1836; GCN-NEXT:    s_mov_b32 s3, 0x41c00000
1837; GCN-NEXT:    s_mov_b32 s4, s0
1838; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1839; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1840; GCN-NEXT:    s_or_b32 s0, s0, 1
1841; GCN-NEXT:    v_mov_b32_e32 v3, s0
1842; GCN-NEXT:    s_mov_b32 s5, s1
1843; GCN-NEXT:    v_mul_f32_e32 v1, s3, v1
1844; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1845; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s3
1846; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1847; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1848; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1849; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1850; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1851; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1852; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1853; GCN-NEXT:    s_endpgm
1854;
1855; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1856; GCN-IR:       ; %bb.0:
1857; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1858; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1859; GCN-IR-NEXT:    s_mov_b32 s6, -1
1860; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1861; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1862; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1863; GCN-IR-NEXT:    s_mov_b32 s3, 0x41c00000
1864; GCN-IR-NEXT:    s_mov_b32 s4, s0
1865; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1866; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1867; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1868; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
1869; GCN-IR-NEXT:    s_mov_b32 s5, s1
1870; GCN-IR-NEXT:    v_mul_f32_e32 v1, s3, v1
1871; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1872; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s3
1873; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1874; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1875; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1876; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1877; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1878; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1879; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1880; GCN-IR-NEXT:    s_endpgm
1881  %x.shr = ashr i64 %x, 40
1882  %result = sdiv i64 24, %x.shr
1883  store i64 %result, i64 addrspace(1)* %out
1884  ret void
1885}
1886
1887define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1888; GCN-LABEL: s_test_sdiv24_k_den_i64:
1889; GCN:       ; %bb.0:
1890; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1891; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1892; GCN-NEXT:    s_mov_b32 s3, 0xf000
1893; GCN-NEXT:    s_mov_b32 s2, -1
1894; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1895; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1896; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
1897; GCN-NEXT:    s_mov_b32 s0, s4
1898; GCN-NEXT:    s_ashr_i32 s4, s6, 30
1899; GCN-NEXT:    s_or_b32 s4, s4, 1
1900; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1901; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1902; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
1903; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1904; GCN-NEXT:    v_mov_b32_e32 v2, s4
1905; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1906; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1907; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1908; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1909; GCN-NEXT:    s_mov_b32 s1, s5
1910; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1911; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1912; GCN-NEXT:    s_endpgm
1913;
1914; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1915; GCN-IR:       ; %bb.0:
1916; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1917; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
1918; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1919; GCN-IR-NEXT:    s_mov_b32 s2, -1
1920; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1921; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1922; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
1923; GCN-IR-NEXT:    s_mov_b32 s0, s4
1924; GCN-IR-NEXT:    s_ashr_i32 s4, s6, 30
1925; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
1926; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1927; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1928; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
1929; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1930; GCN-IR-NEXT:    v_mov_b32_e32 v2, s4
1931; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1932; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1933; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1934; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1935; GCN-IR-NEXT:    s_mov_b32 s1, s5
1936; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1937; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1938; GCN-IR-NEXT:    s_endpgm
1939  %x.shr = ashr i64 %x, 40
1940  %result = sdiv i64 %x.shr, 23423
1941  store i64 %result, i64 addrspace(1)* %out
1942  ret void
1943}
1944
1945define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
1946; GCN-LABEL: v_test_sdiv24_k_num_i64:
1947; GCN:       ; %bb.0:
1948; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1949; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1950; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1951; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1952; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1953; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1954; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1955; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1956; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1957; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1958; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1959; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1960; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1961; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1962; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1963; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1964; GCN-NEXT:    s_setpc_b64 s[30:31]
1965;
1966; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
1967; GCN-IR:       ; %bb.0:
1968; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1969; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1970; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1971; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1972; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1973; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
1974; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1975; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1976; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1977; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
1978; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
1979; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1980; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1981; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1982; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1983; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1984; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1985  %x.shr = ashr i64 %x, 40
1986  %result = sdiv i64 24, %x.shr
1987  ret i64 %result
1988}
1989
1990define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
1991; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
1992; GCN:       ; %bb.0:
1993; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1994; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1995; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1996; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1997; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1998; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1999; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2000; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2001; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2002; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
2003; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2004; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2005; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2006; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2007; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2008; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2009; GCN-NEXT:    s_setpc_b64 s[30:31]
2010;
2011; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
2012; GCN-IR:       ; %bb.0:
2013; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2014; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2015; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2016; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2017; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2018; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2019; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2020; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2021; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2022; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2023; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2024; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2025; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2026; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2027; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2028; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2029; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2030  %x.shr = ashr i64 %x, 40
2031  %result = sdiv i64 32768, %x.shr
2032  ret i64 %result
2033}
2034
2035define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
2036; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
2037; GCN:       ; %bb.0:
2038; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2039; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2040; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2041; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2042; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2043; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
2044; GCN-NEXT:    s_setpc_b64 s[30:31]
2045;
2046; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
2047; GCN-IR:       ; %bb.0:
2048; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2049; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2050; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2051; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2052; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2053; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2054; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
2055; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2056; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
2057; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2058; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2059; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2060; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2061; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2062; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2063; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2064  %x.shr = ashr i64 %x, 40
2065  %result = sdiv i64 %x.shr, 32768
2066  ret i64 %result
2067}
2068