1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_sdiv:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    v_mov_b32_e32 v7, 0
10; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    s_ashr_i32 s12, s3, 31
15; GCN-NEXT:    s_add_u32 s2, s2, s12
16; GCN-NEXT:    s_mov_b32 s13, s12
17; GCN-NEXT:    s_addc_u32 s3, s3, s12
18; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
19; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
20; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
21; GCN-NEXT:    s_sub_u32 s4, 0, s2
22; GCN-NEXT:    s_subb_u32 s5, 0, s3
23; GCN-NEXT:    s_ashr_i32 s14, s11, 31
24; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
25; GCN-NEXT:    v_rcp_f32_e32 v0, v0
26; GCN-NEXT:    v_mov_b32_e32 v1, 0
27; GCN-NEXT:    s_mov_b32 s15, s14
28; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
29; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
30; GCN-NEXT:    v_trunc_f32_e32 v2, v2
31; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
32; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
33; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
34; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
35; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
36; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
37; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
38; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
39; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
40; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
41; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
42; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
43; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
44; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
45; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
47; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
48; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
49; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
50; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
51; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
52; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
53; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
54; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
55; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
56; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
57; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
58; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
59; GCN-NEXT:    s_mov_b32 s5, s9
60; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
61; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
62; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
63; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
64; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
65; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
66; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
67; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
68; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
69; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
70; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
71; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
72; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
73; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
74; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
75; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
76; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
77; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
78; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
79; GCN-NEXT:    s_add_u32 s0, s10, s14
80; GCN-NEXT:    s_addc_u32 s1, s11, s14
81; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
82; GCN-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
83; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
84; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
85; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
86; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
87; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
88; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
89; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
90; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
91; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
92; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
93; GCN-NEXT:    s_mov_b32 s4, s8
94; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
95; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
96; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
97; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
98; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
99; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
100; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
101; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
102; GCN-NEXT:    v_mov_b32_e32 v5, s3
103; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
104; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
105; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
106; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
107; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
108; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
109; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
110; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
111; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
112; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
113; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
114; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
115; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
116; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
117; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
118; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
119; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
120; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
121; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
122; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
123; GCN-NEXT:    v_mov_b32_e32 v6, s11
124; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
125; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
126; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
127; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
128; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
129; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
130; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
131; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
132; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
133; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
134; GCN-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
135; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
136; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
137; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
138; GCN-NEXT:    v_mov_b32_e32 v2, s1
139; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
140; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
141; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
142; GCN-NEXT:    s_endpgm
143;
144; GCN-IR-LABEL: s_test_sdiv:
145; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
146; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
147; GCN-IR-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
148; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
149; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
150; GCN-IR-NEXT:    s_mov_b32 s1, s0
151; GCN-IR-NEXT:    s_ashr_i32 s2, s9, 31
152; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[0:1], s[6:7]
153; GCN-IR-NEXT:    s_sub_u32 s10, s6, s0
154; GCN-IR-NEXT:    s_mov_b32 s3, s2
155; GCN-IR-NEXT:    s_subb_u32 s11, s7, s0
156; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[8:9]
157; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
158; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
159; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
160; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
161; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
162; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
163; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
164; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
165; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
166; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
167; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
168; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
169; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
170; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
171; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
172; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
173; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
174; GCN-IR-NEXT:    s_mov_b32 s15, 0
175; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
176; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
177; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
178; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
179; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
180; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
181; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
182; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
183; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
184; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
185; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
186; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
187; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
188; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
189; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
190; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
191; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
192; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
193; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
194; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
195; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
196; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
197; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
198; GCN-IR-NEXT:    s_mov_b32 s17, s15
199; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
200; GCN-IR-NEXT:    s_mov_b32 s9, 0
201; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
202; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
203; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
204; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
205; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
206; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
207; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
208; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
209; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
210; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
211; GCN-IR-NEXT:    s_mov_b32 s15, s14
212; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
213; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
214; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
215; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
216; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
217; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
218; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
219; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
220; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
221; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
222; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
223; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
224; GCN-IR-NEXT:  BB0_4: ; %Flow6
225; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
226; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
227; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
228; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
229; GCN-IR-NEXT:    s_branch BB0_6
230; GCN-IR-NEXT:  BB0_5:
231; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
232; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
233; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
234; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
235; GCN-IR-NEXT:  BB0_6: ; %udiv-end
236; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
237; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
238; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
239; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
240; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
241; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
242; GCN-IR-NEXT:    s_mov_b32 s6, -1
243; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
244; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
245; GCN-IR-NEXT:    s_endpgm
246  %result = sdiv i64 %x, %y
247  store i64 %result, i64 addrspace(1)* %out
248  ret void
249}
250
251define i64 @v_test_sdiv(i64 %x, i64 %y) {
252; GCN-LABEL: v_test_sdiv:
253; GCN:       ; %bb.0:
254; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
255; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
256; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
257; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
258; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
259; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
260; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
261; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
262; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
263; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
264; GCN-NEXT:    v_mov_b32_e32 v15, 0
265; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
266; GCN-NEXT:    v_rcp_f32_e32 v5, v5
267; GCN-NEXT:    v_mov_b32_e32 v14, 0
268; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
269; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
270; GCN-NEXT:    v_trunc_f32_e32 v6, v6
271; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
272; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
273; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
274; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
275; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
276; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
277; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
278; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
279; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
280; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
281; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
282; GCN-NEXT:    v_mul_hi_u32 v13, v5, v10
283; GCN-NEXT:    v_mul_hi_u32 v16, v6, v9
284; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
285; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
286; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
287; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
288; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v11, vcc
289; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
290; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v10, vcc
291; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v16, v14, vcc
292; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
293; GCN-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
294; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v11, vcc
295; GCN-NEXT:    v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
296; GCN-NEXT:    v_mul_lo_u32 v11, v7, v9
297; GCN-NEXT:    v_mul_hi_u32 v12, v7, v5
298; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
299; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
300; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
301; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
302; GCN-NEXT:    v_mul_lo_u32 v13, v5, v8
303; GCN-NEXT:    v_mul_hi_u32 v16, v5, v7
304; GCN-NEXT:    v_mul_hi_u32 v17, v5, v8
305; GCN-NEXT:    v_mul_hi_u32 v12, v9, v7
306; GCN-NEXT:    v_mul_lo_u32 v7, v9, v7
307; GCN-NEXT:    v_add_i32_e32 v13, vcc, v16, v13
308; GCN-NEXT:    v_mul_hi_u32 v11, v9, v8
309; GCN-NEXT:    v_addc_u32_e32 v16, vcc, v15, v17, vcc
310; GCN-NEXT:    v_mul_lo_u32 v8, v9, v8
311; GCN-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
312; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v16, v12, vcc
313; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v14, vcc
314; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
315; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v15, v9, vcc
316; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
317; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
318; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
319; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
320; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
321; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
322; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
323; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
324; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
325; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
326; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
327; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
328; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
329; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v15, v10, vcc
330; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
331; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
332; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
333; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
334; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
335; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
336; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
337; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
338; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v8, vcc
339; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
340; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
341; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
342; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
343; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
344; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
345; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
346; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
347; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
348; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
349; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
350; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
351; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
352; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
353; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
354; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
355; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
356; GCN-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
357; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 2, v5
358; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
359; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
360; GCN-NEXT:    v_add_i32_e64 v12, s[4:5], 1, v5
361; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
362; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
363; GCN-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
364; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
365; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
366; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
367; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
368; GCN-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
369; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
370; GCN-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
371; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
372; GCN-NEXT:    v_xor_b32_e32 v2, v7, v4
373; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
374; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
375; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
376; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
377; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
378; GCN-NEXT:    s_setpc_b64 s[30:31]
379;
380; GCN-IR-LABEL: v_test_sdiv:
381; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
382; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
383; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
384; GCN-IR-NEXT:    v_xor_b32_e32 v0, v4, v0
385; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
386; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v0, v4
387; GCN-IR-NEXT:    v_xor_b32_e32 v1, v4, v1
388; GCN-IR-NEXT:    v_subb_u32_e32 v10, vcc, v1, v4, vcc
389; GCN-IR-NEXT:    v_xor_b32_e32 v1, v5, v2
390; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
391; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v3
392; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v0, v5, vcc
393; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
394; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[9:10]
395; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v2
396; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
397; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
398; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v3
399; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v7
400; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v9
401; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
402; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v10
403; GCN-IR-NEXT:    v_min_u32_e32 v13, v7, v8
404; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v13
405; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
406; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
407; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
408; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
409; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
410; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
411; GCN-IR-NEXT:    v_mov_b32_e32 v6, v4
412; GCN-IR-NEXT:    v_mov_b32_e32 v1, v5
413; GCN-IR-NEXT:    v_cndmask_b32_e64 v12, v10, 0, s[6:7]
414; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
415; GCN-IR-NEXT:    v_mov_b32_e32 v14, v17
416; GCN-IR-NEXT:    v_cndmask_b32_e64 v11, v9, 0, s[6:7]
417; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
418; GCN-IR-NEXT:    s_cbranch_execz BB1_6
419; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
420; GCN-IR-NEXT:    v_add_i32_e32 v15, vcc, 1, v7
421; GCN-IR-NEXT:    v_addc_u32_e32 v16, vcc, 0, v8, vcc
422; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[15:16], v[7:8]
423; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
424; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
425; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[9:10], v7
426; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
427; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
428; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
429; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
430; GCN-IR-NEXT:    s_cbranch_execz BB1_5
431; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
432; GCN-IR-NEXT:    v_add_i32_e32 v19, vcc, -1, v2
433; GCN-IR-NEXT:    v_addc_u32_e32 v20, vcc, -1, v3, vcc
434; GCN-IR-NEXT:    v_not_b32_e32 v0, v0
435; GCN-IR-NEXT:    v_lshr_b64 v[15:16], v[9:10], v15
436; GCN-IR-NEXT:    v_not_b32_e32 v10, v17
437; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, v0, v13
438; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
439; GCN-IR-NEXT:    v_mov_b32_e32 v18, 0
440; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, v10, v14, vcc
441; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
442; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
443; GCN-IR-NEXT:    v_lshl_b64 v[13:14], v[15:16], 1
444; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v8
445; GCN-IR-NEXT:    v_or_b32_e32 v0, v13, v0
446; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
447; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v19, v0
448; GCN-IR-NEXT:    v_subb_u32_e32 v11, vcc, v20, v14, vcc
449; GCN-IR-NEXT:    v_or_b32_e32 v7, v17, v7
450; GCN-IR-NEXT:    v_add_i32_e32 v17, vcc, 1, v9
451; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v11
452; GCN-IR-NEXT:    v_or_b32_e32 v8, v18, v8
453; GCN-IR-NEXT:    v_addc_u32_e32 v18, vcc, 0, v10, vcc
454; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[17:18], v[9:10]
455; GCN-IR-NEXT:    v_mov_b32_e32 v9, v17
456; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
457; GCN-IR-NEXT:    v_and_b32_e32 v11, 1, v13
458; GCN-IR-NEXT:    v_and_b32_e32 v16, v13, v3
459; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v2
460; GCN-IR-NEXT:    v_sub_i32_e64 v15, s[4:5], v0, v13
461; GCN-IR-NEXT:    v_mov_b32_e32 v10, v18
462; GCN-IR-NEXT:    v_mov_b32_e32 v18, v12
463; GCN-IR-NEXT:    v_subb_u32_e64 v16, s[4:5], v14, v16, s[4:5]
464; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
465; GCN-IR-NEXT:    v_mov_b32_e32 v17, v11
466; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
467; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
468; GCN-IR-NEXT:  ; %bb.4: ; %Flow
469; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
470; GCN-IR-NEXT:  BB1_5: ; %Flow3
471; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
472; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[7:8], 1
473; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v3
474; GCN-IR-NEXT:    v_or_b32_e32 v11, v11, v2
475; GCN-IR-NEXT:  BB1_6: ; %Flow4
476; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
477; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v4
478; GCN-IR-NEXT:    v_xor_b32_e32 v3, v11, v0
479; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v6
480; GCN-IR-NEXT:    v_xor_b32_e32 v2, v12, v1
481; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
482; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
483; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
484  %result = sdiv i64 %x, %y
485  ret i64 %result
486}
487
488define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
489; GCN-LABEL: s_test_sdiv24_64:
490; GCN:       ; %bb.0:
491; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
492; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
493; GCN-NEXT:    s_mov_b32 s3, 0xf000
494; GCN-NEXT:    s_mov_b32 s2, -1
495; GCN-NEXT:    s_waitcnt lgkmcnt(0)
496; GCN-NEXT:    s_mov_b32 s0, s4
497; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
498; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
499; GCN-NEXT:    s_mov_b32 s1, s5
500; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
501; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
502; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
503; GCN-NEXT:    s_xor_b32 s4, s4, s8
504; GCN-NEXT:    s_ashr_i32 s4, s4, 30
505; GCN-NEXT:    s_or_b32 s4, s4, 1
506; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
507; GCN-NEXT:    v_trunc_f32_e32 v2, v2
508; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
509; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
510; GCN-NEXT:    v_mov_b32_e32 v3, s4
511; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
512; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
513; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
514; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
515; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
516; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
517; GCN-NEXT:    s_endpgm
518;
519; GCN-IR-LABEL: s_test_sdiv24_64:
520; GCN-IR:       ; %bb.0:
521; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
522; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
523; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
524; GCN-IR-NEXT:    s_mov_b32 s2, -1
525; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
526; GCN-IR-NEXT:    s_mov_b32 s0, s4
527; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
528; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
529; GCN-IR-NEXT:    s_mov_b32 s1, s5
530; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
531; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
532; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
533; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
534; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
535; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
536; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
537; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
538; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
539; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
540; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
541; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
542; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
543; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
544; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
545; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
546; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
547; GCN-IR-NEXT:    s_endpgm
548  %1 = ashr i64 %x, 40
549  %2 = ashr i64 %y, 40
550  %result = sdiv i64 %1, %2
551  store i64 %result, i64 addrspace(1)* %out
552  ret void
553}
554
555define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
556; GCN-LABEL: v_test_sdiv24_64:
557; GCN:       ; %bb.0:
558; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
559; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
560; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
561; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
562; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
563; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
564; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
565; GCN-NEXT:    v_trunc_f32_e32 v2, v2
566; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
567; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
568; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
569; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
570; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
571; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
572; GCN-NEXT:    s_setpc_b64 s[30:31]
573;
574; GCN-IR-LABEL: v_test_sdiv24_64:
575; GCN-IR:       ; %bb.0:
576; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
577; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
578; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, v0
579; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
580; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v1
581; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
582; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
583; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
584; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
585; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
586; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
587; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
588; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
589; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
590; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
591  %1 = lshr i64 %x, 40
592  %2 = lshr i64 %y, 40
593  %result = sdiv i64 %1, %2
594  ret i64 %result
595}
596
597define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
598; GCN-LABEL: s_test_sdiv32_64:
599; GCN:       ; %bb.0:
600; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
601; GCN-NEXT:    s_waitcnt lgkmcnt(0)
602; GCN-NEXT:    s_load_dword s6, s[0:1], 0xe
603; GCN-NEXT:    s_mov_b32 s3, 0xf000
604; GCN-NEXT:    s_mov_b32 s2, -1
605; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
606; GCN-NEXT:    s_waitcnt lgkmcnt(0)
607; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
608; GCN-NEXT:    s_mov_b32 s0, s4
609; GCN-NEXT:    s_xor_b32 s4, s7, s6
610; GCN-NEXT:    s_ashr_i32 s4, s4, 30
611; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
612; GCN-NEXT:    s_or_b32 s4, s4, 1
613; GCN-NEXT:    v_mov_b32_e32 v3, s4
614; GCN-NEXT:    s_mov_b32 s1, s5
615; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
616; GCN-NEXT:    v_trunc_f32_e32 v2, v2
617; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
618; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
619; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
620; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
621; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
622; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
623; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
624; GCN-NEXT:    s_endpgm
625;
626; GCN-IR-LABEL: s_test_sdiv32_64:
627; GCN-IR:       ; %bb.0:
628; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
629; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
630; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xe
631; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
632; GCN-IR-NEXT:    s_mov_b32 s2, -1
633; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
634; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
635; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
636; GCN-IR-NEXT:    s_mov_b32 s0, s4
637; GCN-IR-NEXT:    s_xor_b32 s4, s7, s6
638; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
639; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
640; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
641; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
642; GCN-IR-NEXT:    s_mov_b32 s1, s5
643; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
644; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
645; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
646; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
647; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
648; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
649; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
650; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
651; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
652; GCN-IR-NEXT:    s_endpgm
653  %1 = ashr i64 %x, 32
654  %2 = ashr i64 %y, 32
655  %result = sdiv i64 %1, %2
656  store i64 %result, i64 addrspace(1)* %out
657  ret void
658}
659
660define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
661; GCN-LABEL: s_test_sdiv31_64:
662; GCN:       ; %bb.0:
663; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
664; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
665; GCN-NEXT:    s_mov_b32 s3, 0xf000
666; GCN-NEXT:    s_mov_b32 s2, -1
667; GCN-NEXT:    s_waitcnt lgkmcnt(0)
668; GCN-NEXT:    s_mov_b32 s0, s4
669; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
670; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
671; GCN-NEXT:    s_mov_b32 s1, s5
672; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
673; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
674; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
675; GCN-NEXT:    s_xor_b32 s4, s4, s8
676; GCN-NEXT:    s_ashr_i32 s4, s4, 30
677; GCN-NEXT:    s_or_b32 s4, s4, 1
678; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
679; GCN-NEXT:    v_trunc_f32_e32 v2, v2
680; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
681; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
682; GCN-NEXT:    v_mov_b32_e32 v3, s4
683; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
684; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
685; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
686; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
687; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
688; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
689; GCN-NEXT:    s_endpgm
690;
691; GCN-IR-LABEL: s_test_sdiv31_64:
692; GCN-IR:       ; %bb.0:
693; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
694; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
695; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
696; GCN-IR-NEXT:    s_mov_b32 s2, -1
697; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
698; GCN-IR-NEXT:    s_mov_b32 s0, s4
699; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
700; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
701; GCN-IR-NEXT:    s_mov_b32 s1, s5
702; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
703; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
704; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
705; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
706; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
707; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
708; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
709; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
710; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
711; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
712; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
713; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
714; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
715; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
716; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
717; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
718; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
719; GCN-IR-NEXT:    s_endpgm
720  %1 = ashr i64 %x, 33
721  %2 = ashr i64 %y, 33
722  %result = sdiv i64 %1, %2
723  store i64 %result, i64 addrspace(1)* %out
724  ret void
725}
726
727define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
728; GCN-LABEL: s_test_sdiv23_64:
729; GCN:       ; %bb.0:
730; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
731; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
732; GCN-NEXT:    s_mov_b32 s3, 0xf000
733; GCN-NEXT:    s_mov_b32 s2, -1
734; GCN-NEXT:    s_waitcnt lgkmcnt(0)
735; GCN-NEXT:    s_mov_b32 s0, s4
736; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
737; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
738; GCN-NEXT:    s_mov_b32 s1, s5
739; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
740; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
741; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
742; GCN-NEXT:    s_xor_b32 s4, s4, s8
743; GCN-NEXT:    s_ashr_i32 s4, s4, 30
744; GCN-NEXT:    s_or_b32 s4, s4, 1
745; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
746; GCN-NEXT:    v_trunc_f32_e32 v2, v2
747; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
748; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
749; GCN-NEXT:    v_mov_b32_e32 v3, s4
750; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
751; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
752; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
753; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
754; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
755; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
756; GCN-NEXT:    s_endpgm
757;
758; GCN-IR-LABEL: s_test_sdiv23_64:
759; GCN-IR:       ; %bb.0:
760; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
761; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
762; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
763; GCN-IR-NEXT:    s_mov_b32 s2, -1
764; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
765; GCN-IR-NEXT:    s_mov_b32 s0, s4
766; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
767; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
768; GCN-IR-NEXT:    s_mov_b32 s1, s5
769; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
770; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
771; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
772; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
773; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
774; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
775; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
776; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
777; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
778; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
779; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
780; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
781; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
782; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
783; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
784; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
785; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
786; GCN-IR-NEXT:    s_endpgm
787  %1 = ashr i64 %x, 41
788  %2 = ashr i64 %y, 41
789  %result = sdiv i64 %1, %2
790  store i64 %result, i64 addrspace(1)* %out
791  ret void
792}
793
794define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
795; GCN-LABEL: s_test_sdiv25_64:
796; GCN:       ; %bb.0:
797; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
798; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
799; GCN-NEXT:    s_mov_b32 s3, 0xf000
800; GCN-NEXT:    s_mov_b32 s2, -1
801; GCN-NEXT:    s_waitcnt lgkmcnt(0)
802; GCN-NEXT:    s_mov_b32 s0, s4
803; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
804; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
805; GCN-NEXT:    s_mov_b32 s1, s5
806; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
807; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
808; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
809; GCN-NEXT:    s_xor_b32 s4, s4, s8
810; GCN-NEXT:    s_ashr_i32 s4, s4, 30
811; GCN-NEXT:    s_or_b32 s4, s4, 1
812; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
813; GCN-NEXT:    v_trunc_f32_e32 v2, v2
814; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
815; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
816; GCN-NEXT:    v_mov_b32_e32 v3, s4
817; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
818; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
819; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
820; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
821; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
822; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
823; GCN-NEXT:    s_endpgm
824;
825; GCN-IR-LABEL: s_test_sdiv25_64:
826; GCN-IR:       ; %bb.0:
827; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
828; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
829; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
830; GCN-IR-NEXT:    s_mov_b32 s2, -1
831; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
832; GCN-IR-NEXT:    s_mov_b32 s0, s4
833; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
834; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
835; GCN-IR-NEXT:    s_mov_b32 s1, s5
836; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
837; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
838; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
839; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
840; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
841; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
842; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
843; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
844; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
845; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
846; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
847; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
848; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
849; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
850; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
851; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
852; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
853; GCN-IR-NEXT:    s_endpgm
854  %1 = ashr i64 %x, 39
855  %2 = ashr i64 %y, 39
856  %result = sdiv i64 %1, %2
857  store i64 %result, i64 addrspace(1)* %out
858  ret void
859}
860
861define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
862; GCN-LABEL: s_test_sdiv24_v2i64:
863; GCN:       ; %bb.0:
864; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
865; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
866; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
867; GCN-NEXT:    s_mov_b32 s7, 0xf000
868; GCN-NEXT:    s_mov_b32 s6, -1
869; GCN-NEXT:    s_waitcnt lgkmcnt(0)
870; GCN-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
871; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
872; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
873; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s8
874; GCN-NEXT:    s_xor_b32 s0, s8, s0
875; GCN-NEXT:    s_ashr_i32 s0, s0, 30
876; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
877; GCN-NEXT:    s_or_b32 s0, s0, 1
878; GCN-NEXT:    v_mov_b32_e32 v3, s0
879; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
880; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
881; GCN-NEXT:    v_trunc_f32_e32 v2, v2
882; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
883; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
884; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
885; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
886; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
887; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
888; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s2
889; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s10
890; GCN-NEXT:    s_xor_b32 s0, s10, s2
891; GCN-NEXT:    s_ashr_i32 s0, s0, 30
892; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
893; GCN-NEXT:    s_or_b32 s0, s0, 1
894; GCN-NEXT:    v_mov_b32_e32 v5, s0
895; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
896; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
897; GCN-NEXT:    v_trunc_f32_e32 v4, v4
898; GCN-NEXT:    v_mad_f32 v3, -v4, v2, v3
899; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
900; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
901; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
902; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
903; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
904; GCN-NEXT:    v_bfe_i32 v2, v2, 0, 24
905; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
906; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
907; GCN-NEXT:    s_endpgm
908;
909; GCN-IR-LABEL: s_test_sdiv24_v2i64:
910; GCN-IR:       ; %bb.0:
911; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
912; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
913; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
914; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
915; GCN-IR-NEXT:    s_mov_b32 s6, -1
916; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
917; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
918; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
919; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
920; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s8
921; GCN-IR-NEXT:    s_xor_b32 s0, s8, s0
922; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
923; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
924; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
925; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
926; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
927; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
928; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
929; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
930; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
931; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
932; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
933; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
934; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
935; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v2, s2
936; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, s10
937; GCN-IR-NEXT:    s_xor_b32 s0, s10, s2
938; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
939; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v2
940; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
941; GCN-IR-NEXT:    v_mov_b32_e32 v5, s0
942; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
943; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
944; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
945; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v2, v3
946; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
947; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
948; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
949; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
950; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
951; GCN-IR-NEXT:    v_bfe_i32 v2, v2, 0, 24
952; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
953; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
954; GCN-IR-NEXT:    s_endpgm
955  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
956  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
957  %result = sdiv <2 x i64> %1, %2
958  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
959  ret void
960}
961
962define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
963; GCN-LABEL: s_test_sdiv24_48:
964; GCN:       ; %bb.0:
965; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
966; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
967; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
968; GCN-NEXT:    s_load_dword s8, s[0:1], 0xd
969; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
970; GCN-NEXT:    s_mov_b32 s7, 0xf000
971; GCN-NEXT:    s_waitcnt lgkmcnt(0)
972; GCN-NEXT:    v_mov_b32_e32 v2, s2
973; GCN-NEXT:    s_sext_i32_i16 s1, s3
974; GCN-NEXT:    v_mov_b32_e32 v0, s8
975; GCN-NEXT:    s_sext_i32_i16 s0, s0
976; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
977; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
978; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
979; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
980; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
981; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
982; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
983; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
984; GCN-NEXT:    s_mov_b32 s6, -1
985; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
986; GCN-NEXT:    v_trunc_f32_e32 v2, v2
987; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
988; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
989; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
990; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
991; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
992; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
993; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
994; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
995; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
996; GCN-NEXT:    s_endpgm
997;
998; GCN-IR-LABEL: s_test_sdiv24_48:
999; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1000; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1001; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1002; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1003; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
1004; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
1005; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1006; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1007; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[2:3], 24
1008; GCN-IR-NEXT:    s_sext_i32_i16 s7, s0
1009; GCN-IR-NEXT:    s_ashr_i32 s0, s3, 31
1010; GCN-IR-NEXT:    s_mov_b32 s1, s0
1011; GCN-IR-NEXT:    s_ashr_i32 s2, s7, 31
1012; GCN-IR-NEXT:    s_ashr_i64 s[12:13], s[6:7], 24
1013; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]
1014; GCN-IR-NEXT:    s_sub_u32 s10, s6, s0
1015; GCN-IR-NEXT:    s_mov_b32 s3, s2
1016; GCN-IR-NEXT:    s_subb_u32 s11, s7, s0
1017; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[12:13]
1018; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
1019; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
1020; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
1021; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
1022; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1023; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
1024; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
1025; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1026; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
1027; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1028; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
1029; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1030; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
1031; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
1032; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
1033; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1034; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
1035; GCN-IR-NEXT:    s_mov_b32 s15, 0
1036; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
1037; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
1038; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
1039; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
1040; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1041; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1042; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1043; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
1044; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1045; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
1046; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1047; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
1048; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1049; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1050; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
1051; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1052; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1053; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
1054; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
1055; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
1056; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
1057; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
1058; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
1059; GCN-IR-NEXT:    s_mov_b32 s17, s15
1060; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1061; GCN-IR-NEXT:    s_mov_b32 s9, 0
1062; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1063; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1064; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1065; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
1066; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1067; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1068; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1069; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
1070; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
1071; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1072; GCN-IR-NEXT:    s_mov_b32 s15, s14
1073; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1074; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
1075; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
1076; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1077; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
1078; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1079; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1080; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1081; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1082; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1083; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1084; GCN-IR-NEXT:    s_cbranch_vccz BB9_3
1085; GCN-IR-NEXT:  BB9_4: ; %Flow3
1086; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
1087; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1088; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1089; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1090; GCN-IR-NEXT:    s_branch BB9_6
1091; GCN-IR-NEXT:  BB9_5:
1092; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
1093; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
1094; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1095; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
1096; GCN-IR-NEXT:  BB9_6: ; %udiv-end
1097; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
1098; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1099; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1100; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1101; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1102; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1103; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1104; GCN-IR-NEXT:    s_mov_b32 s6, -1
1105; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1106; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1107; GCN-IR-NEXT:    s_endpgm
1108  %1 = ashr i48 %x, 24
1109  %2 = ashr i48 %y, 24
1110  %result = sdiv i48 %1, %2
1111  store i48 %result, i48 addrspace(1)* %out
1112  ret void
1113}
1114
1115define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1116; GCN-LABEL: s_test_sdiv_k_num_i64:
1117; GCN:       ; %bb.0:
1118; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1119; GCN-NEXT:    v_mov_b32_e32 v2, 0
1120; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1121; GCN-NEXT:    s_ashr_i32 s2, s7, 31
1122; GCN-NEXT:    s_add_u32 s0, s6, s2
1123; GCN-NEXT:    s_addc_u32 s1, s7, s2
1124; GCN-NEXT:    s_mov_b32 s3, s2
1125; GCN-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
1126; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1127; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1128; GCN-NEXT:    s_sub_u32 s3, 0, s8
1129; GCN-NEXT:    s_subb_u32 s6, 0, s9
1130; GCN-NEXT:    s_mov_b32 s7, 0xf000
1131; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1132; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1133; GCN-NEXT:    v_mov_b32_e32 v1, 0
1134; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1135; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1136; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1137; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1138; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1139; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1140; GCN-NEXT:    v_mul_hi_u32 v5, s3, v0
1141; GCN-NEXT:    v_mul_lo_u32 v4, s3, v3
1142; GCN-NEXT:    v_mul_lo_u32 v7, s6, v0
1143; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
1144; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1145; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1146; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1147; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1148; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1149; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1150; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1151; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1152; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1153; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1154; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1155; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
1156; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1157; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
1158; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1159; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
1160; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1161; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
1162; GCN-NEXT:    v_mul_lo_u32 v6, s3, v4
1163; GCN-NEXT:    v_mul_hi_u32 v7, s3, v0
1164; GCN-NEXT:    v_mul_lo_u32 v8, s6, v0
1165; GCN-NEXT:    s_mov_b32 s6, -1
1166; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1167; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
1168; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
1169; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
1170; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
1171; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
1172; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
1173; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1174; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
1175; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1176; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
1177; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1178; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
1179; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
1180; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
1181; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1182; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1183; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1184; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
1185; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1186; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1187; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
1188; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1189; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1190; GCN-NEXT:    v_mov_b32_e32 v5, s9
1191; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1192; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
1193; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
1194; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
1195; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1196; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
1197; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
1198; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
1199; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
1200; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v3
1201; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
1202; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
1203; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
1204; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v5
1205; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1206; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v4
1207; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
1208; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
1209; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1]
1210; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1211; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
1212; GCN-NEXT:    v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1213; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1214; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
1215; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1216; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
1217; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1218; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1219; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v3, vcc
1220; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
1221; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1222; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
1223; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
1224; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1225; GCN-NEXT:    v_xor_b32_e32 v0, s2, v0
1226; GCN-NEXT:    v_xor_b32_e32 v1, s2, v1
1227; GCN-NEXT:    v_mov_b32_e32 v2, s2
1228; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1229; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1230; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1231; GCN-NEXT:    s_endpgm
1232;
1233; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1234; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1235; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1236; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1237; GCN-IR-NEXT:    s_ashr_i32 s4, s3, 31
1238; GCN-IR-NEXT:    s_mov_b32 s5, s4
1239; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1240; GCN-IR-NEXT:    s_sub_u32 s2, s2, s4
1241; GCN-IR-NEXT:    s_subb_u32 s3, s3, s4
1242; GCN-IR-NEXT:    s_flbit_i32_b32 s6, s2
1243; GCN-IR-NEXT:    s_add_i32 s6, s6, 32
1244; GCN-IR-NEXT:    s_flbit_i32_b32 s7, s3
1245; GCN-IR-NEXT:    s_min_u32 s8, s6, s7
1246; GCN-IR-NEXT:    s_add_u32 s10, s8, 0xffffffc5
1247; GCN-IR-NEXT:    s_addc_u32 s11, 0, -1
1248; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1249; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[14:15], s[10:11], 63
1250; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1251; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
1252; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[14:15], s[10:11], 63
1253; GCN-IR-NEXT:    s_xor_b64 s[16:17], s[12:13], -1
1254; GCN-IR-NEXT:    s_and_b64 s[14:15], s[16:17], s[14:15]
1255; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
1256; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1257; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1258; GCN-IR-NEXT:    s_add_u32 s12, s10, 1
1259; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1260; GCN-IR-NEXT:    s_addc_u32 s13, s11, 0
1261; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1262; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1263; GCN-IR-NEXT:    s_sub_i32 s9, 63, s10
1264; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1265; GCN-IR-NEXT:    s_lshl_b64 s[10:11], 24, s9
1266; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1267; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1268; GCN-IR-NEXT:    s_lshr_b64 s[14:15], 24, s12
1269; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
1270; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
1271; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1272; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1273; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1274; GCN-IR-NEXT:    s_mov_b32 s7, 0
1275; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1276; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1277; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
1278; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1279; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1280; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
1281; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
1282; GCN-IR-NEXT:    s_sub_u32 s6, s16, s14
1283; GCN-IR-NEXT:    s_subb_u32 s6, s17, s15
1284; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
1285; GCN-IR-NEXT:    s_mov_b32 s13, s12
1286; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
1287; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[2:3]
1288; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
1289; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1290; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
1291; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1292; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1293; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1294; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
1295; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
1296; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1297; GCN-IR-NEXT:    s_cbranch_vccz BB10_3
1298; GCN-IR-NEXT:  BB10_4: ; %Flow5
1299; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[10:11], 1
1300; GCN-IR-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
1301; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1302; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1303; GCN-IR-NEXT:    s_branch BB10_6
1304; GCN-IR-NEXT:  BB10_5:
1305; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1306; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[12:13]
1307; GCN-IR-NEXT:  BB10_6: ; %udiv-end
1308; GCN-IR-NEXT:    v_xor_b32_e32 v0, s4, v0
1309; GCN-IR-NEXT:    v_xor_b32_e32 v1, s5, v1
1310; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1311; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
1312; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1313; GCN-IR-NEXT:    s_mov_b32 s2, -1
1314; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1315; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1316; GCN-IR-NEXT:    s_endpgm
1317  %result = sdiv i64 24, %x
1318  store i64 %result, i64 addrspace(1)* %out
1319  ret void
1320}
1321
1322define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1323; GCN-LABEL: v_test_sdiv_k_num_i64:
1324; GCN:       ; %bb.0:
1325; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1326; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1327; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1328; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1329; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1330; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1331; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1332; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1333; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1334; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1335; GCN-NEXT:    v_mov_b32_e32 v13, 0
1336; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1337; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1338; GCN-NEXT:    v_mov_b32_e32 v12, 0
1339; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1340; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1341; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1342; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1343; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1344; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1345; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1346; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1347; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1348; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1349; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1350; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1351; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1352; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1353; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1354; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1355; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1356; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1357; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1358; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1359; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1360; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1361; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1362; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1363; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1364; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
1365; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1366; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
1367; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
1368; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
1369; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1370; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1371; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1372; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
1373; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
1374; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
1375; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
1376; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
1377; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
1378; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
1379; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
1380; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
1381; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
1382; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
1383; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
1384; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
1385; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1386; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1387; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
1388; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
1389; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1390; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
1391; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
1392; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1393; GCN-NEXT:    v_mul_hi_u32 v4, v4, 24
1394; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1395; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v13, v4, vcc
1396; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1397; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1398; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1399; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1400; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1401; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 24, v5
1402; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1403; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1404; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1405; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1406; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1407; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1408; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1409; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1410; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1411; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1412; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, v13, s[4:5]
1413; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1414; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1415; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, v13, s[4:5]
1416; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1417; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1418; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1419; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1420; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1421; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1422; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1423; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1424; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1425; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1426; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1427; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1428; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1429; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1430; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1431; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1432; GCN-NEXT:    s_setpc_b64 s[30:31]
1433;
1434; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1435; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1436; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1437; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1438; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1439; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1440; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1441; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1442; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1443; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1444; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1445; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1446; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1447; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1448; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1449; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1450; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1451; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1452; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1453; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1454; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, 24, 0, s[4:5]
1455; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1456; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1457; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1458; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1459; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1460; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1461; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1462; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1463; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1464; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1465; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1466; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1467; GCN-IR-NEXT:    v_lshl_b64 v[4:5], 24, v4
1468; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1469; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1470; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1471; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1472; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1473; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1474; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1475; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1476; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 58, v8
1477; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1478; GCN-IR-NEXT:    v_lshr_b64 v[10:11], 24, v10
1479; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1480; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1481; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1482; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1483; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1484; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1485; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1486; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1487; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1488; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1489; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1490; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1491; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1492; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1493; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1494; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1495; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1496; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1497; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1498; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1499; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1500; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1501; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1502; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1503; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1504; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1505; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1506; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1507; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1508; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1509; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1510; GCN-IR-NEXT:  BB11_5: ; %Flow3
1511; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1512; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1513; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1514; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1515; GCN-IR-NEXT:  BB11_6: ; %Flow4
1516; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1517; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1518; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1519; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1520; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1521; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1522  %result = sdiv i64 24, %x
1523  ret i64 %result
1524}
1525
1526define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1527; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1528; GCN:       ; %bb.0:
1529; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1530; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1531; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1532; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1533; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1534; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1535; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1536; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1537; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1538; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1539; GCN-NEXT:    v_mov_b32_e32 v13, 0
1540; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1541; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1542; GCN-NEXT:    v_mov_b32_e32 v12, 0
1543; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1544; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1545; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1546; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1547; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1548; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1549; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1550; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1551; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1552; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1553; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1554; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1555; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1556; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1557; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1558; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1559; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1560; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1561; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1562; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1563; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1564; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1565; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1566; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1567; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1568; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
1569; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1570; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
1571; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
1572; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
1573; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1574; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1575; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1576; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
1577; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
1578; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
1579; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
1580; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
1581; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
1582; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
1583; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
1584; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
1585; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
1586; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
1587; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
1588; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
1589; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1590; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1591; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
1592; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
1593; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1594; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
1595; GCN-NEXT:    v_lshrrev_b32_e32 v5, 17, v4
1596; GCN-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
1597; GCN-NEXT:    v_lshrrev_b32_e32 v3, 17, v3
1598; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
1599; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v13, v5, vcc
1600; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1601; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1602; GCN-NEXT:    s_mov_b32 s4, 0x8000
1603; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1604; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1605; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1606; GCN-NEXT:    v_sub_i32_e32 v5, vcc, s4, v5
1607; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1608; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1609; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1610; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1611; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1612; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1613; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1614; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1615; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1616; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1617; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, v13, s[4:5]
1618; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1619; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1620; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, v13, s[4:5]
1621; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1622; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1623; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1624; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1625; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1626; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1627; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1628; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1629; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1630; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1631; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1632; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1633; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1634; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1635; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1636; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1637; GCN-NEXT:    s_setpc_b64 s[30:31]
1638;
1639; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1640; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1641; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1642; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1643; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1644; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1645; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1646; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1647; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1648; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1649; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1650; GCN-IR-NEXT:    v_min_u32_e32 v6, v4, v5
1651; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1652; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v6
1653; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1654; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1655; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1656; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1657; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1658; GCN-IR-NEXT:    v_mov_b32_e32 v8, s8
1659; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1660; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1661; GCN-IR-NEXT:    v_cndmask_b32_e64 v8, v8, 0, s[4:5]
1662; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1663; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1664; GCN-IR-NEXT:    v_mov_b32_e32 v9, v7
1665; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1666; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1667; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1668; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1669; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1670; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1671; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1672; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1673; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1674; GCN-IR-NEXT:    v_lshl_b64 v[4:5], s[8:9], v4
1675; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1676; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1677; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1678; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1679; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1680; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1681; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1682; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1683; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1684; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1685; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1686; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v10
1687; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1688; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1689; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1690; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1691; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1692; GCN-IR-NEXT:    v_lshrrev_b32_e32 v8, 31, v5
1693; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v8
1694; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1695; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, v14, v10
1696; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v15, v11, vcc
1697; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1698; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v8
1699; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1700; GCN-IR-NEXT:    v_and_b32_e32 v8, 1, v12
1701; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1702; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v6
1703; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1704; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v7, vcc
1705; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[6:7]
1706; GCN-IR-NEXT:    v_mov_b32_e32 v6, v12
1707; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1708; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1709; GCN-IR-NEXT:    v_mov_b32_e32 v7, v13
1710; GCN-IR-NEXT:    v_mov_b32_e32 v13, v9
1711; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1712; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1713; GCN-IR-NEXT:    v_mov_b32_e32 v12, v8
1714; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1715; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1716; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1717; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1718; GCN-IR-NEXT:  BB12_5: ; %Flow3
1719; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1720; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1721; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v1
1722; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v0
1723; GCN-IR-NEXT:  BB12_6: ; %Flow4
1724; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1725; GCN-IR-NEXT:    v_xor_b32_e32 v0, v8, v2
1726; GCN-IR-NEXT:    v_xor_b32_e32 v1, v9, v3
1727; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1728; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1729; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1730  %result = sdiv i64 32768, %x
1731  ret i64 %result
1732}
1733
1734define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1735; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1736; GCN:       ; %bb.0:
1737; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1738; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1739; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1740; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1741; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1742; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1743; GCN-NEXT:    s_setpc_b64 s[30:31]
1744;
1745; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1746; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1747; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1748; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1749; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1750; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v2
1751; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1752; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v1, v2, vcc
1753; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v7
1754; GCN-IR-NEXT:    v_add_i32_e64 v0, s[4:5], 32, v0
1755; GCN-IR-NEXT:    v_ffbh_u32_e32 v1, v8
1756; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v1
1757; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 48, v0
1758; GCN-IR-NEXT:    v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1759; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1760; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1761; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1762; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1763; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1764; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1765; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1766; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1767; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1768; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1769; GCN-IR-NEXT:    s_cbranch_execz BB13_6
1770; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1771; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
1772; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
1773; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4]
1774; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v3
1775; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1776; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[7:8], v3
1777; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1778; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1779; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1780; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1781; GCN-IR-NEXT:    s_cbranch_execz BB13_5
1782; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1783; GCN-IR-NEXT:    v_lshr_b64 v[9:10], v[7:8], v9
1784; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1785; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1786; GCN-IR-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1787; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1788; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1789; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
1790; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1791; GCN-IR-NEXT:    v_lshl_b64 v[9:10], v[9:10], 1
1792; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v4
1793; GCN-IR-NEXT:    v_or_b32_e32 v0, v9, v0
1794; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1795; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, s12, v0
1796; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v10, vcc
1797; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1798; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
1799; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
1800; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1801; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
1802; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
1803; GCN-IR-NEXT:    v_and_b32_e32 v5, 1, v9
1804; GCN-IR-NEXT:    v_and_b32_e32 v9, 0x8000, v9
1805; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1806; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1807; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1808; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1809; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1810; GCN-IR-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v9
1811; GCN-IR-NEXT:    v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5]
1812; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1813; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1814; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1815; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
1816; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1817; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1818; GCN-IR-NEXT:  BB13_5: ; %Flow3
1819; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1820; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1821; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1822; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1823; GCN-IR-NEXT:  BB13_6: ; %Flow4
1824; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1825; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v2
1826; GCN-IR-NEXT:    v_xor_b32_e32 v3, v6, v1
1827; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1828; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
1829; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1830  %result = sdiv i64 %x, 32768
1831  ret i64 %result
1832}
1833
1834define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1835; GCN-LABEL: s_test_sdiv24_k_num_i64:
1836; GCN:       ; %bb.0:
1837; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1838; GCN-NEXT:    s_mov_b32 s7, 0xf000
1839; GCN-NEXT:    s_mov_b32 s6, -1
1840; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1841; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1842; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1843; GCN-NEXT:    s_mov_b32 s3, 0x41c00000
1844; GCN-NEXT:    s_mov_b32 s4, s0
1845; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1846; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1847; GCN-NEXT:    s_or_b32 s0, s0, 1
1848; GCN-NEXT:    v_mov_b32_e32 v3, s0
1849; GCN-NEXT:    s_mov_b32 s5, s1
1850; GCN-NEXT:    v_mul_f32_e32 v1, s3, v1
1851; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1852; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s3
1853; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1854; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1855; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1856; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1857; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1858; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1859; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1860; GCN-NEXT:    s_endpgm
1861;
1862; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1863; GCN-IR:       ; %bb.0:
1864; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1865; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1866; GCN-IR-NEXT:    s_mov_b32 s6, -1
1867; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1868; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1869; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1870; GCN-IR-NEXT:    s_mov_b32 s3, 0x41c00000
1871; GCN-IR-NEXT:    s_mov_b32 s4, s0
1872; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1873; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1874; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1875; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
1876; GCN-IR-NEXT:    s_mov_b32 s5, s1
1877; GCN-IR-NEXT:    v_mul_f32_e32 v1, s3, v1
1878; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1879; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s3
1880; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1881; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1882; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1883; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1884; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1885; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1886; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1887; GCN-IR-NEXT:    s_endpgm
1888  %x.shr = ashr i64 %x, 40
1889  %result = sdiv i64 24, %x.shr
1890  store i64 %result, i64 addrspace(1)* %out
1891  ret void
1892}
1893
1894define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1895; GCN-LABEL: s_test_sdiv24_k_den_i64:
1896; GCN:       ; %bb.0:
1897; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1898; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1899; GCN-NEXT:    s_mov_b32 s3, 0xf000
1900; GCN-NEXT:    s_mov_b32 s2, -1
1901; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1902; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1903; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
1904; GCN-NEXT:    s_mov_b32 s0, s4
1905; GCN-NEXT:    s_ashr_i32 s4, s6, 30
1906; GCN-NEXT:    s_or_b32 s4, s4, 1
1907; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1908; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1909; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
1910; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1911; GCN-NEXT:    v_mov_b32_e32 v2, s4
1912; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1913; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1914; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1915; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1916; GCN-NEXT:    s_mov_b32 s1, s5
1917; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1918; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1919; GCN-NEXT:    s_endpgm
1920;
1921; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1922; GCN-IR:       ; %bb.0:
1923; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1924; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
1925; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1926; GCN-IR-NEXT:    s_mov_b32 s2, -1
1927; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1928; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1929; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
1930; GCN-IR-NEXT:    s_mov_b32 s0, s4
1931; GCN-IR-NEXT:    s_ashr_i32 s4, s6, 30
1932; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
1933; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1934; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1935; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
1936; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1937; GCN-IR-NEXT:    v_mov_b32_e32 v2, s4
1938; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1939; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1940; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1941; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1942; GCN-IR-NEXT:    s_mov_b32 s1, s5
1943; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1944; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1945; GCN-IR-NEXT:    s_endpgm
1946  %x.shr = ashr i64 %x, 40
1947  %result = sdiv i64 %x.shr, 23423
1948  store i64 %result, i64 addrspace(1)* %out
1949  ret void
1950}
1951
1952define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
1953; GCN-LABEL: v_test_sdiv24_k_num_i64:
1954; GCN:       ; %bb.0:
1955; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1956; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1957; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1958; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1959; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1960; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1961; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1962; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1963; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1964; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1965; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1966; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1967; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1968; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1969; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1970; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1971; GCN-NEXT:    s_setpc_b64 s[30:31]
1972;
1973; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
1974; GCN-IR:       ; %bb.0:
1975; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1976; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1977; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1978; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1979; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1980; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
1981; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1982; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1983; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1984; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
1985; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
1986; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1987; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1988; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1989; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1990; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1991; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1992  %x.shr = ashr i64 %x, 40
1993  %result = sdiv i64 24, %x.shr
1994  ret i64 %result
1995}
1996
1997define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
1998; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
1999; GCN:       ; %bb.0:
2000; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2001; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2002; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2003; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2004; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2005; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
2006; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2007; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2008; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2009; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
2010; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2011; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2012; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2013; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2014; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2015; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2016; GCN-NEXT:    s_setpc_b64 s[30:31]
2017;
2018; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
2019; GCN-IR:       ; %bb.0:
2020; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2021; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2022; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2023; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2024; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2025; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2026; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2027; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2028; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2029; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2030; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2031; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2032; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2033; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2034; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2035; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2036; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2037  %x.shr = ashr i64 %x, 40
2038  %result = sdiv i64 32768, %x.shr
2039  ret i64 %result
2040}
2041
2042define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
2043; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
2044; GCN:       ; %bb.0:
2045; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2046; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2047; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2048; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2049; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2050; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
2051; GCN-NEXT:    s_setpc_b64 s[30:31]
2052;
2053; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
2054; GCN-IR:       ; %bb.0:
2055; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2056; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2057; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2058; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2059; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2060; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2061; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
2062; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2063; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
2064; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2065; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2066; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2067; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2068; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2069; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2070; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2071  %x.shr = ashr i64 %x, 40
2072  %result = sdiv i64 %x.shr, 32768
2073  ret i64 %result
2074}
2075