1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
5; GCN-LABEL: s_test_sdiv:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    s_mov_b32 s7, 0xf000
10; GCN-NEXT:    s_mov_b32 s6, -1
11; GCN-NEXT:    v_mov_b32_e32 v0, 0
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    s_ashr_i32 s0, s3, 31
14; GCN-NEXT:    v_mov_b32_e32 v1, 0
15; GCN-NEXT:    s_mov_b32 s4, s8
16; GCN-NEXT:    s_mov_b32 s5, s9
17; GCN-NEXT:    s_mov_b32 s1, s0
18; GCN-NEXT:    s_add_u32 s2, s2, s0
19; GCN-NEXT:    s_addc_u32 s3, s3, s0
20; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[0:1]
21; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s2
22; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s3
23; GCN-NEXT:    s_sub_u32 s14, 0, s2
24; GCN-NEXT:    v_mov_b32_e32 v4, s3
25; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
26; GCN-NEXT:    s_subb_u32 s15, 0, s3
27; GCN-NEXT:    s_ashr_i32 s8, s11, 31
28; GCN-NEXT:    v_rcp_f32_e32 v2, v2
29; GCN-NEXT:    s_mov_b32 s9, s8
30; GCN-NEXT:    s_add_u32 s10, s10, s8
31; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
32; GCN-NEXT:    s_addc_u32 s11, s11, s8
33; GCN-NEXT:    s_xor_b64 s[12:13], s[8:9], s[0:1]
34; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
35; GCN-NEXT:    s_xor_b64 s[8:9], s[10:11], s[8:9]
36; GCN-NEXT:    v_mov_b32_e32 v5, s13
37; GCN-NEXT:    v_trunc_f32_e32 v3, v3
38; GCN-NEXT:    v_mov_b32_e32 v6, s9
39; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
40; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
41; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
42; GCN-NEXT:    v_mul_lo_u32 v7, s14, v3
43; GCN-NEXT:    v_mul_lo_u32 v8, s15, v2
44; GCN-NEXT:    v_mul_hi_u32 v9, s14, v2
45; GCN-NEXT:    v_mul_lo_u32 v10, s14, v2
46; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
47; GCN-NEXT:    v_mul_hi_u32 v9, v2, v10
48; GCN-NEXT:    v_mul_hi_u32 v11, v3, v10
49; GCN-NEXT:    v_mul_lo_u32 v10, v3, v10
50; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
51; GCN-NEXT:    v_mul_hi_u32 v8, v2, v7
52; GCN-NEXT:    v_mul_lo_u32 v12, v2, v7
53; GCN-NEXT:    v_mul_hi_u32 v13, v3, v7
54; GCN-NEXT:    v_mul_lo_u32 v7, v3, v7
55; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
56; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v1, v8, vcc
57; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
58; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v11, vcc
59; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v0, vcc
60; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
61; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v1, v9, vcc
62; GCN-NEXT:    v_add_i32_e64 v2, s[0:1], v2, v7
63; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v3, v8, s[0:1]
64; GCN-NEXT:    v_mul_hi_u32 v9, s14, v2
65; GCN-NEXT:    v_mul_lo_u32 v10, s15, v2
66; GCN-NEXT:    v_mul_lo_u32 v11, s14, v2
67; GCN-NEXT:    v_mul_lo_u32 v12, s14, v7
68; GCN-NEXT:    v_mul_hi_u32 v13, v7, v11
69; GCN-NEXT:    v_mul_lo_u32 v14, v7, v11
70; GCN-NEXT:    v_mul_hi_u32 v11, v2, v11
71; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
72; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
73; GCN-NEXT:    v_mul_hi_u32 v10, v7, v9
74; GCN-NEXT:    v_mul_hi_u32 v12, v2, v9
75; GCN-NEXT:    v_mul_lo_u32 v15, v2, v9
76; GCN-NEXT:    v_mul_lo_u32 v7, v7, v9
77; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v15
78; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v1, v12, vcc
79; GCN-NEXT:    v_add_i32_e32 v9, vcc, v14, v9
80; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v13, vcc
81; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v10, v0, vcc
82; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
83; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
84; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v1, v10, vcc
85; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v8, s[0:1]
86; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
87; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
88; GCN-NEXT:    v_mul_hi_u32 v7, s8, v2
89; GCN-NEXT:    v_mul_hi_u32 v8, s9, v2
90; GCN-NEXT:    v_mul_lo_u32 v2, s9, v2
91; GCN-NEXT:    v_mul_hi_u32 v9, s8, v3
92; GCN-NEXT:    v_mul_lo_u32 v10, s8, v3
93; GCN-NEXT:    v_mul_hi_u32 v11, s9, v3
94; GCN-NEXT:    v_mul_lo_u32 v3, s9, v3
95; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
96; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v1, v9, vcc
97; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
98; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v9, v8, vcc
99; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v11, v0, vcc
100; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
101; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
102; GCN-NEXT:    v_mul_hi_u32 v1, s2, v2
103; GCN-NEXT:    v_mul_lo_u32 v3, s3, v2
104; GCN-NEXT:    v_mul_lo_u32 v7, s2, v2
105; GCN-NEXT:    v_mul_lo_u32 v8, s2, v0
106; GCN-NEXT:    v_add_i32_e32 v9, vcc, 2, v2
107; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v0, vcc
108; GCN-NEXT:    v_add_i32_e32 v11, vcc, 1, v2
109; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v0, vcc
110; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v8
111; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
112; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s9, v1
113; GCN-NEXT:    v_sub_i32_e32 v7, vcc, s8, v7
114; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
115; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v7
116; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v6, v1, vcc
117; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v7
118; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
119; GCN-NEXT:    v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1]
120; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
121; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
122; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
123; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
124; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
125; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
126; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
127; GCN-NEXT:    v_cndmask_b32_e32 v1, v7, v6, vcc
128; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v3
129; GCN-NEXT:    v_cndmask_b32_e32 v3, v8, v4, vcc
130; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
131; GCN-NEXT:    v_cndmask_b32_e32 v3, v12, v10, vcc
132; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v1
133; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
134; GCN-NEXT:    v_cndmask_b32_e32 v1, v11, v9, vcc
135; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v1, s[0:1]
136; GCN-NEXT:    v_xor_b32_e32 v2, s13, v0
137; GCN-NEXT:    v_xor_b32_e32 v0, s12, v1
138; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
139; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v5, vcc
140; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
141; GCN-NEXT:    s_endpgm
142  %result = sdiv i64 %x, %y
143  store i64 %result, i64 addrspace(1)* %out
144  ret void
145}
146
147define i64 @v_test_sdiv(i64 %x, i64 %y) {
148; GCN-LABEL: v_test_sdiv:
149; GCN:       ; %bb.0:
150; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
151; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
152; GCN-NEXT:    v_mov_b32_e32 v5, 0
153; GCN-NEXT:    v_mov_b32_e32 v6, 0
154; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
155; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
156; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
157; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
158; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
159; GCN-NEXT:    v_xor_b32_e32 v8, v7, v4
160; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
161; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
162; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
163; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
164; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
165; GCN-NEXT:    v_cvt_f32_u32_e32 v7, v3
166; GCN-NEXT:    v_sub_i32_e32 v9, vcc, 0, v2
167; GCN-NEXT:    v_subb_u32_e32 v10, vcc, 0, v3, vcc
168; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v7
169; GCN-NEXT:    v_rcp_f32_e32 v4, v4
170; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
171; GCN-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
172; GCN-NEXT:    v_trunc_f32_e32 v7, v7
173; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
174; GCN-NEXT:    v_cvt_u32_f32_e32 v7, v7
175; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
176; GCN-NEXT:    v_mul_lo_u32 v11, v9, v7
177; GCN-NEXT:    v_mul_lo_u32 v12, v10, v4
178; GCN-NEXT:    v_mul_hi_u32 v13, v9, v4
179; GCN-NEXT:    v_mul_lo_u32 v14, v9, v4
180; GCN-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
181; GCN-NEXT:    v_mul_hi_u32 v13, v4, v14
182; GCN-NEXT:    v_mul_hi_u32 v15, v7, v14
183; GCN-NEXT:    v_mul_lo_u32 v14, v7, v14
184; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
185; GCN-NEXT:    v_mul_hi_u32 v12, v4, v11
186; GCN-NEXT:    v_mul_lo_u32 v16, v4, v11
187; GCN-NEXT:    v_mul_hi_u32 v17, v7, v11
188; GCN-NEXT:    v_mul_lo_u32 v11, v7, v11
189; GCN-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
190; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v6, v12, vcc
191; GCN-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
192; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v12, v15, vcc
193; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v17, v5, vcc
194; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
195; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v6, v13, vcc
196; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v11
197; GCN-NEXT:    v_addc_u32_e64 v11, vcc, v7, v12, s[4:5]
198; GCN-NEXT:    v_mul_hi_u32 v13, v9, v4
199; GCN-NEXT:    v_mul_lo_u32 v10, v10, v4
200; GCN-NEXT:    v_mul_lo_u32 v14, v9, v4
201; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
202; GCN-NEXT:    v_mul_lo_u32 v9, v9, v11
203; GCN-NEXT:    v_mul_hi_u32 v12, v11, v14
204; GCN-NEXT:    v_mul_lo_u32 v15, v11, v14
205; GCN-NEXT:    v_mul_hi_u32 v14, v4, v14
206; GCN-NEXT:    v_add_i32_e32 v9, vcc, v13, v9
207; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
208; GCN-NEXT:    v_mul_hi_u32 v10, v11, v9
209; GCN-NEXT:    v_mul_hi_u32 v13, v4, v9
210; GCN-NEXT:    v_mul_lo_u32 v16, v4, v9
211; GCN-NEXT:    v_mul_lo_u32 v9, v11, v9
212; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v16
213; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v6, v13, vcc
214; GCN-NEXT:    v_add_i32_e32 v11, vcc, v15, v11
215; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v13, v12, vcc
216; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v10, v5, vcc
217; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
218; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v6, v10, vcc
219; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v7, v10, s[4:5]
220; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
221; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
222; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
223; GCN-NEXT:    v_mul_hi_u32 v10, v1, v4
224; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
225; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
226; GCN-NEXT:    v_mul_lo_u32 v12, v0, v7
227; GCN-NEXT:    v_mul_hi_u32 v13, v1, v7
228; GCN-NEXT:    v_mul_lo_u32 v7, v1, v7
229; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
230; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v6, v11, vcc
231; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
232; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v10, vcc
233; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v13, v5, vcc
234; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
235; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
236; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
237; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
238; GCN-NEXT:    v_mul_lo_u32 v9, v2, v4
239; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
240; GCN-NEXT:    v_add_i32_e32 v11, vcc, 2, v4
241; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v5, vcc
242; GCN-NEXT:    v_add_i32_e32 v13, vcc, 1, v4
243; GCN-NEXT:    v_addc_u32_e32 v14, vcc, 0, v5, vcc
244; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
245; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
246; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v6
247; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
248; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v3, vcc
249; GCN-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v2
250; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
251; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
252; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
253; GCN-NEXT:    v_subbrev_u32_e64 v6, vcc, 0, v7, s[4:5]
254; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v2
255; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
256; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
257; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
258; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v3
259; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
260; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
261; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
262; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v3
263; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v2, vcc
264; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
265; GCN-NEXT:    v_cndmask_b32_e32 v1, v14, v12, vcc
266; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
267; GCN-NEXT:    v_cndmask_b32_e64 v0, v5, v1, s[4:5]
268; GCN-NEXT:    v_cndmask_b32_e32 v1, v13, v11, vcc
269; GCN-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
270; GCN-NEXT:    v_xor_b32_e32 v2, v0, v8
271; GCN-NEXT:    v_xor_b32_e32 v0, v1, v8
272; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
273; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v8, vcc
274; GCN-NEXT:    s_setpc_b64 s[30:31]
275  %result = sdiv i64 %x, %y
276  ret i64 %result
277}
278
279define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
280; GCN-LABEL: s_test_sdiv24_64:
281; GCN:       ; %bb.0:
282; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
283; GCN-NEXT:    s_load_dword s9, s[0:1], 0xe
284; GCN-NEXT:    s_mov_b32 s3, 0xf000
285; GCN-NEXT:    s_mov_b32 s2, -1
286; GCN-NEXT:    s_waitcnt lgkmcnt(0)
287; GCN-NEXT:    s_mov_b32 s0, s4
288; GCN-NEXT:    s_mov_b32 s1, s5
289; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
290; GCN-NEXT:    s_ashr_i64 s[6:7], s[8:9], 40
291; GCN-NEXT:    s_xor_b32 s5, s4, s6
292; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
293; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
294; GCN-NEXT:    s_ashr_i32 s4, s5, 30
295; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
296; GCN-NEXT:    s_or_b32 s4, s4, 1
297; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
298; GCN-NEXT:    v_trunc_f32_e32 v2, v2
299; GCN-NEXT:    v_mov_b32_e32 v3, s4
300; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
301; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
302; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
303; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v2
304; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
305; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
306; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
307; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
308; GCN-NEXT:    s_endpgm
309  %1 = ashr i64 %x, 40
310  %2 = ashr i64 %y, 40
311  %result = sdiv i64 %1, %2
312  store i64 %result, i64 addrspace(1)* %out
313  ret void
314}
315
316define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
317; GCN-LABEL: v_test_sdiv24_64:
318; GCN:       ; %bb.0:
319; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
320; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
321; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
322; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v1
323; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v2
324; GCN-NEXT:    v_mul_f32_e32 v2, 0x4f800000, v2
325; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
326; GCN-NEXT:    v_mul_hi_u32 v3, v2, v1
327; GCN-NEXT:    v_mul_lo_u32 v4, v2, v1
328; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v4
329; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
330; GCN-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
331; GCN-NEXT:    v_mul_hi_u32 v3, v3, v2
332; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v2, v3
333; GCN-NEXT:    v_sub_i32_e64 v2, s[4:5], v2, v3
334; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
335; GCN-NEXT:    v_mul_hi_u32 v2, v2, v0
336; GCN-NEXT:    v_mul_lo_u32 v3, v2, v1
337; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v2
338; GCN-NEXT:    v_add_i32_e32 v5, vcc, -1, v2
339; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v3
340; GCN-NEXT:    v_sub_i32_e64 v0, s[4:5], v0, v3
341; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v1
342; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
343; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
344; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
345; GCN-NEXT:    v_mov_b32_e32 v1, 0
346; GCN-NEXT:    s_setpc_b64 s[30:31]
347  %1 = lshr i64 %x, 40
348  %2 = lshr i64 %y, 40
349  %result = sdiv i64 %1, %2
350  ret i64 %result
351}
352
353define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
354; GCN-LABEL: s_test_sdiv32_64:
355; GCN:       ; %bb.0:
356; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
357; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
358; GCN-NEXT:    s_mov_b32 s11, 0xf000
359; GCN-NEXT:    s_mov_b32 s10, -1
360; GCN-NEXT:    s_waitcnt lgkmcnt(0)
361; GCN-NEXT:    s_mov_b32 s8, s4
362; GCN-NEXT:    s_mov_b32 s9, s5
363; GCN-NEXT:    s_ashr_i32 s3, s2, 31
364; GCN-NEXT:    s_ashr_i32 s4, s7, 31
365; GCN-NEXT:    s_add_i32 s2, s2, s3
366; GCN-NEXT:    s_add_i32 s0, s7, s4
367; GCN-NEXT:    s_xor_b32 s5, s2, s3
368; GCN-NEXT:    s_xor_b32 s2, s0, s4
369; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s5
370; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
371; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
372; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
373; GCN-NEXT:    v_mul_hi_u32 v1, v0, s5
374; GCN-NEXT:    v_mul_lo_u32 v2, v0, s5
375; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
376; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
377; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
378; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
379; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
380; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
381; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
382; GCN-NEXT:    v_mul_hi_u32 v0, v0, s2
383; GCN-NEXT:    v_mul_lo_u32 v1, v0, s5
384; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
385; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
386; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s2, v1
387; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
388; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
389; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
390; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
391; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
392; GCN-NEXT:    s_xor_b32 s0, s4, s3
393; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
394; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
395; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
396; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
397; GCN-NEXT:    s_endpgm
398  %1 = ashr i64 %x, 32
399  %2 = ashr i64 %y, 32
400  %result = sdiv i64 %1, %2
401  store i64 %result, i64 addrspace(1)* %out
402  ret void
403}
404
405define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
406; GCN-LABEL: s_test_sdiv31_64:
407; GCN:       ; %bb.0:
408; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
409; GCN-NEXT:    s_load_dword s3, s[0:1], 0xe
410; GCN-NEXT:    s_mov_b32 s11, 0xf000
411; GCN-NEXT:    s_mov_b32 s10, -1
412; GCN-NEXT:    s_waitcnt lgkmcnt(0)
413; GCN-NEXT:    s_mov_b32 s8, s4
414; GCN-NEXT:    s_mov_b32 s9, s5
415; GCN-NEXT:    s_ashr_i64 s[0:1], s[6:7], 33
416; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
417; GCN-NEXT:    s_ashr_i32 s3, s2, 31
418; GCN-NEXT:    s_ashr_i32 s4, s0, 31
419; GCN-NEXT:    s_add_i32 s1, s2, s3
420; GCN-NEXT:    s_add_i32 s0, s0, s4
421; GCN-NEXT:    s_xor_b32 s5, s1, s3
422; GCN-NEXT:    s_xor_b32 s2, s0, s4
423; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s5
424; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
425; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
426; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
427; GCN-NEXT:    v_mul_hi_u32 v1, v0, s5
428; GCN-NEXT:    v_mul_lo_u32 v2, v0, s5
429; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
430; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
431; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
432; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
433; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
434; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
435; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
436; GCN-NEXT:    v_mul_hi_u32 v0, v0, s2
437; GCN-NEXT:    v_mul_lo_u32 v1, v0, s5
438; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
439; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
440; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s2, v1
441; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
442; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
443; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
444; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
445; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
446; GCN-NEXT:    s_xor_b32 s0, s4, s3
447; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
448; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
449; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
450; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
451; GCN-NEXT:    s_endpgm
452  %1 = ashr i64 %x, 33
453  %2 = ashr i64 %y, 33
454  %result = sdiv i64 %1, %2
455  store i64 %result, i64 addrspace(1)* %out
456  ret void
457}
458
459define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
460; GCN-LABEL: s_test_sdiv23_64:
461; GCN:       ; %bb.0:
462; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
463; GCN-NEXT:    s_load_dword s9, s[0:1], 0xe
464; GCN-NEXT:    s_mov_b32 s3, 0xf000
465; GCN-NEXT:    s_mov_b32 s2, -1
466; GCN-NEXT:    s_waitcnt lgkmcnt(0)
467; GCN-NEXT:    s_mov_b32 s0, s4
468; GCN-NEXT:    s_mov_b32 s1, s5
469; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
470; GCN-NEXT:    s_ashr_i64 s[6:7], s[8:9], 41
471; GCN-NEXT:    s_xor_b32 s5, s4, s6
472; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
473; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
474; GCN-NEXT:    s_ashr_i32 s4, s5, 30
475; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
476; GCN-NEXT:    s_or_b32 s4, s4, 1
477; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
478; GCN-NEXT:    v_trunc_f32_e32 v2, v2
479; GCN-NEXT:    v_mov_b32_e32 v3, s4
480; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
481; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
482; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
483; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v2
484; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
485; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
486; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
487; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
488; GCN-NEXT:    s_endpgm
489  %1 = ashr i64 %x, 41
490  %2 = ashr i64 %y, 41
491  %result = sdiv i64 %1, %2
492  store i64 %result, i64 addrspace(1)* %out
493  ret void
494}
495
496define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
497; GCN-LABEL: s_test_sdiv25_64:
498; GCN:       ; %bb.0:
499; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
500; GCN-NEXT:    s_load_dword s3, s[0:1], 0xe
501; GCN-NEXT:    s_mov_b32 s11, 0xf000
502; GCN-NEXT:    s_mov_b32 s10, -1
503; GCN-NEXT:    s_waitcnt lgkmcnt(0)
504; GCN-NEXT:    s_mov_b32 s8, s4
505; GCN-NEXT:    s_mov_b32 s9, s5
506; GCN-NEXT:    s_ashr_i64 s[0:1], s[6:7], 39
507; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
508; GCN-NEXT:    s_ashr_i32 s3, s2, 31
509; GCN-NEXT:    s_ashr_i32 s4, s0, 31
510; GCN-NEXT:    s_add_i32 s1, s2, s3
511; GCN-NEXT:    s_add_i32 s0, s0, s4
512; GCN-NEXT:    s_xor_b32 s5, s1, s3
513; GCN-NEXT:    s_xor_b32 s2, s0, s4
514; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s5
515; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
516; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
517; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
518; GCN-NEXT:    v_mul_hi_u32 v1, v0, s5
519; GCN-NEXT:    v_mul_lo_u32 v2, v0, s5
520; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
521; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
522; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
523; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
524; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
525; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
526; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
527; GCN-NEXT:    v_mul_hi_u32 v0, v0, s2
528; GCN-NEXT:    v_mul_lo_u32 v1, v0, s5
529; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
530; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
531; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s2, v1
532; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
533; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s5, v1
534; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
535; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
536; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
537; GCN-NEXT:    s_xor_b32 s0, s4, s3
538; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
539; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
540; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
541; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
542; GCN-NEXT:    s_endpgm
543  %1 = ashr i64 %x, 39
544  %2 = ashr i64 %y, 39
545  %result = sdiv i64 %1, %2
546  store i64 %result, i64 addrspace(1)* %out
547  ret void
548}
549
550define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
551; GCN-LABEL: s_test_sdiv24_v2i64:
552; GCN:       ; %bb.0:
553; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
554; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
555; GCN-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x11
556; GCN-NEXT:    s_mov_b32 s7, 0xf000
557; GCN-NEXT:    s_mov_b32 s6, -1
558; GCN-NEXT:    s_waitcnt lgkmcnt(0)
559; GCN-NEXT:    s_ashr_i64 s[0:1], s[8:9], 40
560; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 40
561; GCN-NEXT:    s_ashr_i64 s[8:9], s[12:13], 40
562; GCN-NEXT:    s_ashr_i64 s[10:11], s[14:15], 40
563; GCN-NEXT:    s_xor_b32 s1, s2, s10
564; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
565; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s10
566; GCN-NEXT:    s_xor_b32 s2, s0, s8
567; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s0
568; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s8
569; GCN-NEXT:    s_ashr_i32 s0, s1, 30
570; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
571; GCN-NEXT:    s_ashr_i32 s1, s2, 30
572; GCN-NEXT:    v_rcp_iflag_f32_e32 v5, v3
573; GCN-NEXT:    s_or_b32 s0, s0, 1
574; GCN-NEXT:    v_mul_f32_e32 v4, v0, v4
575; GCN-NEXT:    s_or_b32 s1, s1, 1
576; GCN-NEXT:    v_mul_f32_e32 v5, v2, v5
577; GCN-NEXT:    v_trunc_f32_e32 v4, v4
578; GCN-NEXT:    v_mov_b32_e32 v6, s0
579; GCN-NEXT:    v_trunc_f32_e32 v5, v5
580; GCN-NEXT:    v_mov_b32_e32 v7, s1
581; GCN-NEXT:    v_mad_f32 v0, -v4, v1, v0
582; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
583; GCN-NEXT:    v_mad_f32 v2, -v5, v3, v2
584; GCN-NEXT:    v_cvt_i32_f32_e32 v5, v5
585; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, |v1|
586; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
587; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v3|
588; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v7, vcc
589; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
590; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
591; GCN-NEXT:    v_bfe_i32 v2, v0, 0, 24
592; GCN-NEXT:    v_bfe_i32 v0, v1, 0, 24
593; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
594; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
595; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
596; GCN-NEXT:    s_endpgm
597  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
598  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
599  %result = sdiv <2 x i64> %1, %2
600  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
601  ret void
602}
603
604define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
605; GCN-LABEL: s_test_sdiv24_48:
606; GCN:       ; %bb.0:
607; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
608; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
609; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
610; GCN-NEXT:    s_load_dword s8, s[0:1], 0xd
611; GCN-NEXT:    s_load_dword s9, s[0:1], 0xe
612; GCN-NEXT:    s_mov_b32 s7, 0xf000
613; GCN-NEXT:    s_mov_b32 s6, -1
614; GCN-NEXT:    s_waitcnt lgkmcnt(0)
615; GCN-NEXT:    s_sext_i32_i16 s0, s3
616; GCN-NEXT:    s_sext_i32_i16 s1, s9
617; GCN-NEXT:    v_mov_b32_e32 v0, s8
618; GCN-NEXT:    v_mov_b32_e32 v1, s2
619; GCN-NEXT:    v_alignbit_b32 v0, s1, v0, 24
620; GCN-NEXT:    v_alignbit_b32 v1, s0, v1, 24
621; GCN-NEXT:    v_xor_b32_e32 v2, v1, v0
622; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
623; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
624; GCN-NEXT:    v_ashrrev_i32_e32 v2, 30, v2
625; GCN-NEXT:    v_rcp_iflag_f32_e32 v3, v0
626; GCN-NEXT:    v_or_b32_e32 v2, 1, v2
627; GCN-NEXT:    v_mul_f32_e32 v3, v1, v3
628; GCN-NEXT:    v_trunc_f32_e32 v3, v3
629; GCN-NEXT:    v_mad_f32 v1, -v3, v0, v1
630; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v3
631; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
632; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
633; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
634; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
635; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
636; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
637; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
638; GCN-NEXT:    s_endpgm
639  %1 = ashr i48 %x, 24
640  %2 = ashr i48 %y, 24
641  %result = sdiv i48 %1, %2
642  store i48 %result, i48 addrspace(1)* %out
643  ret void
644}
645
646define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
647; GCN-LABEL: s_test_sdiv_k_num_i64:
648; GCN:       ; %bb.0:
649; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
650; GCN-NEXT:    s_mov_b32 s7, 0xf000
651; GCN-NEXT:    s_mov_b32 s6, -1
652; GCN-NEXT:    v_mov_b32_e32 v0, 0
653; GCN-NEXT:    s_waitcnt lgkmcnt(0)
654; GCN-NEXT:    s_ashr_i32 s2, s11, 31
655; GCN-NEXT:    v_mov_b32_e32 v1, 0
656; GCN-NEXT:    s_mov_b32 s4, s8
657; GCN-NEXT:    s_mov_b32 s5, s9
658; GCN-NEXT:    s_mov_b32 s3, s2
659; GCN-NEXT:    s_add_u32 s0, s10, s2
660; GCN-NEXT:    v_mov_b32_e32 v2, s2
661; GCN-NEXT:    s_addc_u32 s1, s11, s2
662; GCN-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
663; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s8
664; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s9
665; GCN-NEXT:    s_sub_u32 s3, 0, s8
666; GCN-NEXT:    v_mov_b32_e32 v5, s9
667; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
668; GCN-NEXT:    s_subb_u32 s10, 0, s9
669; GCN-NEXT:    v_rcp_f32_e32 v3, v3
670; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
671; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
672; GCN-NEXT:    v_trunc_f32_e32 v4, v4
673; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
674; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
675; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
676; GCN-NEXT:    v_mul_lo_u32 v6, s3, v4
677; GCN-NEXT:    v_mul_lo_u32 v7, s10, v3
678; GCN-NEXT:    v_mul_hi_u32 v8, s3, v3
679; GCN-NEXT:    v_mul_lo_u32 v9, s3, v3
680; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
681; GCN-NEXT:    v_mul_hi_u32 v8, v3, v9
682; GCN-NEXT:    v_mul_hi_u32 v10, v4, v9
683; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
684; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
685; GCN-NEXT:    v_mul_hi_u32 v7, v3, v6
686; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
687; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
688; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
689; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
690; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v7, vcc
691; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
692; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v10, vcc
693; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v0, vcc
694; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
695; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v8, vcc
696; GCN-NEXT:    v_add_i32_e64 v3, s[0:1], v3, v6
697; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v4, v7, s[0:1]
698; GCN-NEXT:    v_mul_hi_u32 v8, s3, v3
699; GCN-NEXT:    v_mul_lo_u32 v9, s10, v3
700; GCN-NEXT:    v_mul_lo_u32 v10, s3, v3
701; GCN-NEXT:    v_mul_lo_u32 v11, s3, v6
702; GCN-NEXT:    v_mul_hi_u32 v12, v6, v10
703; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
704; GCN-NEXT:    v_mul_hi_u32 v10, v3, v10
705; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
706; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
707; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
708; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
709; GCN-NEXT:    v_mul_lo_u32 v14, v3, v8
710; GCN-NEXT:    v_mul_lo_u32 v6, v6, v8
711; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v14
712; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v1, v11, vcc
713; GCN-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
714; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v12, vcc
715; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v0, vcc
716; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
717; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
718; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v9, vcc
719; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v7, s[0:1]
720; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
721; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
722; GCN-NEXT:    v_mul_hi_u32 v6, 24, v3
723; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
724; GCN-NEXT:    v_mul_hi_u32 v7, 24, v4
725; GCN-NEXT:    v_mul_lo_u32 v8, v4, 24
726; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
727; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
728; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
729; GCN-NEXT:    v_add_i32_e32 v6, vcc, 0, v6
730; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
731; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
732; GCN-NEXT:    v_mul_hi_u32 v3, s8, v1
733; GCN-NEXT:    v_mul_lo_u32 v4, s9, v1
734; GCN-NEXT:    v_mul_lo_u32 v6, s8, v1
735; GCN-NEXT:    v_mul_lo_u32 v7, s8, v0
736; GCN-NEXT:    v_add_i32_e32 v8, vcc, 2, v1
737; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v0, vcc
738; GCN-NEXT:    v_add_i32_e32 v10, vcc, 1, v1
739; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v0, vcc
740; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
741; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
742; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
743; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 24, v6
744; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
745; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v6
746; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
747; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v6
748; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
749; GCN-NEXT:    v_subbrev_u32_e64 v4, vcc, 0, v4, s[0:1]
750; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
751; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
752; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
753; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
754; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
755; GCN-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
756; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
757; GCN-NEXT:    v_cndmask_b32_e32 v3, v7, v6, vcc
758; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v4
759; GCN-NEXT:    v_cndmask_b32_e32 v4, v12, v5, vcc
760; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
761; GCN-NEXT:    v_cndmask_b32_e32 v4, v11, v9, vcc
762; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
763; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
764; GCN-NEXT:    v_cndmask_b32_e32 v3, v10, v8, vcc
765; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
766; GCN-NEXT:    v_xor_b32_e32 v3, s2, v0
767; GCN-NEXT:    v_xor_b32_e32 v0, s2, v1
768; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
769; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
770; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
771; GCN-NEXT:    s_endpgm
772  %result = sdiv i64 24, %x
773  store i64 %result, i64 addrspace(1)* %out
774  ret void
775}
776
777define i64 @v_test_sdiv_k_num_i64(i64 %x) {
778; GCN-LABEL: v_test_sdiv_k_num_i64:
779; GCN:       ; %bb.0:
780; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
781; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
782; GCN-NEXT:    v_mov_b32_e32 v3, 0
783; GCN-NEXT:    v_mov_b32_e32 v4, 0
784; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
785; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
786; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
787; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
788; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v0
789; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v1
790; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v0
791; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v1, vcc
792; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
793; GCN-NEXT:    v_rcp_f32_e32 v5, v5
794; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
795; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
796; GCN-NEXT:    v_trunc_f32_e32 v6, v6
797; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
798; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
799; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
800; GCN-NEXT:    v_mul_lo_u32 v9, v7, v6
801; GCN-NEXT:    v_mul_lo_u32 v10, v8, v5
802; GCN-NEXT:    v_mul_hi_u32 v11, v7, v5
803; GCN-NEXT:    v_mul_lo_u32 v12, v7, v5
804; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
805; GCN-NEXT:    v_mul_hi_u32 v11, v5, v12
806; GCN-NEXT:    v_mul_hi_u32 v13, v6, v12
807; GCN-NEXT:    v_mul_lo_u32 v12, v6, v12
808; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
809; GCN-NEXT:    v_mul_hi_u32 v10, v5, v9
810; GCN-NEXT:    v_mul_lo_u32 v14, v5, v9
811; GCN-NEXT:    v_mul_hi_u32 v15, v6, v9
812; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
813; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
814; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v4, v10, vcc
815; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
816; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v10, v13, vcc
817; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v3, vcc
818; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
819; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v4, v11, vcc
820; GCN-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
821; GCN-NEXT:    v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
822; GCN-NEXT:    v_mul_hi_u32 v11, v7, v5
823; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
824; GCN-NEXT:    v_mul_lo_u32 v12, v7, v5
825; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
826; GCN-NEXT:    v_mul_lo_u32 v7, v7, v9
827; GCN-NEXT:    v_mul_hi_u32 v10, v9, v12
828; GCN-NEXT:    v_mul_lo_u32 v13, v9, v12
829; GCN-NEXT:    v_mul_hi_u32 v12, v5, v12
830; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
831; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
832; GCN-NEXT:    v_mul_hi_u32 v8, v9, v7
833; GCN-NEXT:    v_mul_hi_u32 v11, v5, v7
834; GCN-NEXT:    v_mul_lo_u32 v14, v5, v7
835; GCN-NEXT:    v_mul_lo_u32 v7, v9, v7
836; GCN-NEXT:    v_add_i32_e32 v9, vcc, v12, v14
837; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v4, v11, vcc
838; GCN-NEXT:    v_add_i32_e32 v9, vcc, v13, v9
839; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v10, vcc
840; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v3, vcc
841; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
842; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v4, v8, vcc
843; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
844; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
845; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
846; GCN-NEXT:    v_mul_hi_u32 v7, 24, v5
847; GCN-NEXT:    v_mul_hi_u32 v5, 0, v5
848; GCN-NEXT:    v_mul_hi_u32 v8, 24, v6
849; GCN-NEXT:    v_mul_lo_u32 v9, v6, 24
850; GCN-NEXT:    v_mul_hi_u32 v6, 0, v6
851; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
852; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
853; GCN-NEXT:    v_add_i32_e32 v7, vcc, 0, v7
854; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
855; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
856; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
857; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
858; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
859; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
860; GCN-NEXT:    v_add_i32_e32 v9, vcc, 2, v4
861; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v3, vcc
862; GCN-NEXT:    v_add_i32_e32 v11, vcc, 1, v4
863; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v3, vcc
864; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
865; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
866; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v5
867; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 24, v7
868; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
869; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v7, v0
870; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
871; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
872; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
873; GCN-NEXT:    v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5]
874; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v8, v0
875; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
876; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
877; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
878; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v1
879; GCN-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
880; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
881; GCN-NEXT:    v_cndmask_b32_e32 v5, v8, v7, vcc
882; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v1
883; GCN-NEXT:    v_cndmask_b32_e32 v0, v13, v0, vcc
884; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
885; GCN-NEXT:    v_cndmask_b32_e32 v0, v12, v10, vcc
886; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
887; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[4:5]
888; GCN-NEXT:    v_cndmask_b32_e32 v1, v11, v9, vcc
889; GCN-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
890; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
891; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
892; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
893; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
894; GCN-NEXT:    s_setpc_b64 s[30:31]
895  %result = sdiv i64 24, %x
896  ret i64 %result
897}
898
899define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
900; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
901; GCN:       ; %bb.0:
902; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
903; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
904; GCN-NEXT:    v_mov_b32_e32 v3, 0
905; GCN-NEXT:    v_mov_b32_e32 v4, 0
906; GCN-NEXT:    s_mov_b32 s6, 0x8000
907; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
908; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
909; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
910; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
911; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v0
912; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v1
913; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v0
914; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v1, vcc
915; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
916; GCN-NEXT:    v_rcp_f32_e32 v5, v5
917; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
918; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
919; GCN-NEXT:    v_trunc_f32_e32 v6, v6
920; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
921; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
922; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
923; GCN-NEXT:    v_mul_lo_u32 v9, v7, v6
924; GCN-NEXT:    v_mul_lo_u32 v10, v8, v5
925; GCN-NEXT:    v_mul_hi_u32 v11, v7, v5
926; GCN-NEXT:    v_mul_lo_u32 v12, v7, v5
927; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
928; GCN-NEXT:    v_mul_hi_u32 v11, v5, v12
929; GCN-NEXT:    v_mul_hi_u32 v13, v6, v12
930; GCN-NEXT:    v_mul_lo_u32 v12, v6, v12
931; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
932; GCN-NEXT:    v_mul_hi_u32 v10, v5, v9
933; GCN-NEXT:    v_mul_lo_u32 v14, v5, v9
934; GCN-NEXT:    v_mul_hi_u32 v15, v6, v9
935; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
936; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
937; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v4, v10, vcc
938; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
939; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v10, v13, vcc
940; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v3, vcc
941; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
942; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v4, v11, vcc
943; GCN-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
944; GCN-NEXT:    v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
945; GCN-NEXT:    v_mul_hi_u32 v11, v7, v5
946; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
947; GCN-NEXT:    v_mul_lo_u32 v12, v7, v5
948; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
949; GCN-NEXT:    v_mul_lo_u32 v7, v7, v9
950; GCN-NEXT:    v_mul_hi_u32 v10, v9, v12
951; GCN-NEXT:    v_mul_lo_u32 v13, v9, v12
952; GCN-NEXT:    v_mul_hi_u32 v12, v5, v12
953; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
954; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
955; GCN-NEXT:    v_mul_hi_u32 v8, v9, v7
956; GCN-NEXT:    v_mul_hi_u32 v11, v5, v7
957; GCN-NEXT:    v_mul_lo_u32 v14, v5, v7
958; GCN-NEXT:    v_mul_lo_u32 v7, v9, v7
959; GCN-NEXT:    v_add_i32_e32 v9, vcc, v12, v14
960; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v4, v11, vcc
961; GCN-NEXT:    v_add_i32_e32 v9, vcc, v13, v9
962; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v10, vcc
963; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v3, vcc
964; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
965; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v4, v8, vcc
966; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
967; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
968; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
969; GCN-NEXT:    v_mul_hi_u32 v7, s6, v5
970; GCN-NEXT:    v_mul_hi_u32 v5, 0, v5
971; GCN-NEXT:    v_mul_hi_u32 v8, s6, v6
972; GCN-NEXT:    v_lshlrev_b32_e32 v9, 15, v6
973; GCN-NEXT:    v_mul_hi_u32 v6, 0, v6
974; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
975; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
976; GCN-NEXT:    v_add_i32_e32 v7, vcc, 0, v7
977; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
978; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
979; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
980; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
981; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
982; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
983; GCN-NEXT:    v_add_i32_e32 v9, vcc, 2, v4
984; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v3, vcc
985; GCN-NEXT:    v_add_i32_e32 v11, vcc, 1, v4
986; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v3, vcc
987; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
988; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
989; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v5
990; GCN-NEXT:    v_sub_i32_e32 v7, vcc, s6, v7
991; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
992; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v7, v0
993; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
994; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
995; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
996; GCN-NEXT:    v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5]
997; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v8, v0
998; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
999; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
1000; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1001; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v1
1002; GCN-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
1003; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
1004; GCN-NEXT:    v_cndmask_b32_e32 v5, v8, v7, vcc
1005; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v1
1006; GCN-NEXT:    v_cndmask_b32_e32 v0, v13, v0, vcc
1007; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1008; GCN-NEXT:    v_cndmask_b32_e32 v0, v12, v10, vcc
1009; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
1010; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[4:5]
1011; GCN-NEXT:    v_cndmask_b32_e32 v1, v11, v9, vcc
1012; GCN-NEXT:    v_cndmask_b32_e64 v1, v4, v1, s[4:5]
1013; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1014; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1015; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1016; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1017; GCN-NEXT:    s_setpc_b64 s[30:31]
1018  %result = sdiv i64 32768, %x
1019  ret i64 %result
1020}
1021
1022define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1023; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1024; GCN:       ; %bb.0:
1025; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1026; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1027; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1028; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1029; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1030; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1031; GCN-NEXT:    s_setpc_b64 s[30:31]
1032  %result = sdiv i64 %x, 32768
1033  ret i64 %result
1034}
1035
1036define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1037; GCN-LABEL: s_test_sdiv24_k_num_i64:
1038; GCN:       ; %bb.0:
1039; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1040; GCN-NEXT:    s_mov_b32 s7, 0xf000
1041; GCN-NEXT:    s_mov_b32 s6, -1
1042; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1043; GCN-NEXT:    s_mov_b32 s2, 0x41c00000
1044; GCN-NEXT:    s_mov_b32 s4, s0
1045; GCN-NEXT:    s_mov_b32 s5, s1
1046; GCN-NEXT:    s_ashr_i64 s[0:1], s[2:3], 40
1047; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
1048; GCN-NEXT:    s_ashr_i32 s0, s0, 30
1049; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1050; GCN-NEXT:    s_or_b32 s0, s0, 1
1051; GCN-NEXT:    v_mul_f32_e32 v1, s2, v1
1052; GCN-NEXT:    v_mov_b32_e32 v2, s0
1053; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1054; GCN-NEXT:    v_mad_f32 v3, -v1, v0, s2
1055; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v0|
1056; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1057; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1058; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1059; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1060; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1061; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1062; GCN-NEXT:    s_endpgm
1063  %x.shr = ashr i64 %x, 40
1064  %result = sdiv i64 24, %x.shr
1065  store i64 %result, i64 addrspace(1)* %out
1066  ret void
1067}
1068
1069define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1070; GCN-LABEL: s_test_sdiv24_k_den_i64:
1071; GCN:       ; %bb.0:
1072; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1073; GCN-NEXT:    s_mov_b32 s7, 0xf000
1074; GCN-NEXT:    s_mov_b32 s6, -1
1075; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1076; GCN-NEXT:    s_mov_b32 s2, 0x46b6fe00
1077; GCN-NEXT:    s_mov_b32 s4, s0
1078; GCN-NEXT:    s_mov_b32 s5, s1
1079; GCN-NEXT:    s_ashr_i64 s[0:1], s[2:3], 40
1080; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
1081; GCN-NEXT:    s_ashr_i32 s0, s0, 30
1082; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1083; GCN-NEXT:    s_or_b32 s0, s0, 1
1084; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1085; GCN-NEXT:    v_mov_b32_e32 v2, s0
1086; GCN-NEXT:    v_mad_f32 v0, -v1, s2, v0
1087; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s2
1088; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1089; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1090; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1091; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1092; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1093; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1094; GCN-NEXT:    s_endpgm
1095  %x.shr = ashr i64 %x, 40
1096  %result = sdiv i64 %x.shr, 23423
1097  store i64 %result, i64 addrspace(1)* %out
1098  ret void
1099}
1100
1101define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
1102; GCN-LABEL: v_test_sdiv24_k_num_i64:
1103; GCN:       ; %bb.0:
1104; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1105; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1106; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1107; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1108; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1109; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1110; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1111; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1112; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1113; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1114; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1115; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1116; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v2
1117; GCN-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
1118; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1119; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1120; GCN-NEXT:    s_setpc_b64 s[30:31]
1121  %x.shr = ashr i64 %x, 40
1122  %result = sdiv i64 24, %x.shr
1123  ret i64 %result
1124}
1125
1126define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
1127; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
1128; GCN:       ; %bb.0:
1129; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1130; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1131; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1132; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1133; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1134; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1135; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1136; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1137; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1138; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1139; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1140; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1141; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v2
1142; GCN-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
1143; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1144; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1145; GCN-NEXT:    s_setpc_b64 s[30:31]
1146  %x.shr = ashr i64 %x, 40
1147  %result = sdiv i64 32768, %x.shr
1148  ret i64 %result
1149}
1150
1151define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
1152; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
1153; GCN:       ; %bb.0:
1154; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1155; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1156; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
1157; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1158; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1159; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1160; GCN-NEXT:    s_setpc_b64 s[30:31]
1161  %x.shr = ashr i64 %x, 40
1162  %result = sdiv i64 %x.shr, 32768
1163  ret i64 %result
1164}
1165