1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_sdiv:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    s_mov_b32 s7, 0xf000
10; GCN-NEXT:    s_mov_b32 s6, -1
11; GCN-NEXT:    s_waitcnt lgkmcnt(0)
12; GCN-NEXT:    s_ashr_i32 s8, s3, 31
13; GCN-NEXT:    s_add_u32 s2, s2, s8
14; GCN-NEXT:    s_mov_b32 s9, s8
15; GCN-NEXT:    s_addc_u32 s3, s3, s8
16; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
17; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s10
18; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s11
19; GCN-NEXT:    s_sub_u32 s4, 0, s10
20; GCN-NEXT:    s_subb_u32 s5, 0, s11
21; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
22; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
23; GCN-NEXT:    v_rcp_f32_e32 v0, v0
24; GCN-NEXT:    v_mov_b32_e32 v1, 0
25; GCN-NEXT:    s_waitcnt lgkmcnt(0)
26; GCN-NEXT:    s_ashr_i32 s12, s3, 31
27; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
28; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
29; GCN-NEXT:    v_trunc_f32_e32 v2, v2
30; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
31; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
32; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
33; GCN-NEXT:    s_add_u32 s2, s2, s12
34; GCN-NEXT:    s_mov_b32 s13, s12
35; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
36; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
37; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
38; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
39; GCN-NEXT:    s_addc_u32 s3, s3, s12
40; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
41; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
42; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
43; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
44; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
45; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
46; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
48; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
49; GCN-NEXT:    v_mul_hi_u32 v8, v2, v3
50; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
51; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
52; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
53; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
54; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
55; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
56; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
57; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
58; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
59; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
60; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
61; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
62; GCN-NEXT:    s_mov_b32 s5, s1
63; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
64; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
65; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
66; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
67; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
68; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
69; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
70; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
71; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
72; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
73; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
74; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
75; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
76; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
77; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
78; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
79; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
80; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
81; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
82; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
83; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
84; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
85; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
86; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
87; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
88; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
89; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
90; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
91; GCN-NEXT:    s_mov_b32 s4, s0
92; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
93; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
94; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
95; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
96; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
97; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
98; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
99; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
100; GCN-NEXT:    v_mov_b32_e32 v5, s11
101; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
102; GCN-NEXT:    v_mul_lo_u32 v3, s10, v0
103; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
104; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
105; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
106; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
107; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
108; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
109; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
110; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
111; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
113; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
114; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
115; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
116; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
117; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
118; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
119; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
120; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
121; GCN-NEXT:    v_mov_b32_e32 v6, s3
122; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
123; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
124; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
125; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
126; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
127; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
128; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
129; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
130; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
131; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
132; GCN-NEXT:    s_xor_b64 s[0:1], s[12:13], s[8:9]
133; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
134; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
135; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
136; GCN-NEXT:    v_mov_b32_e32 v2, s1
137; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
138; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
139; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
140; GCN-NEXT:    s_endpgm
141;
142; GCN-IR-LABEL: s_test_sdiv:
143; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
144; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
145; GCN-IR-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
146; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
147; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
148; GCN-IR-NEXT:    s_mov_b32 s1, s0
149; GCN-IR-NEXT:    s_ashr_i32 s2, s9, 31
150; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[0:1], s[6:7]
151; GCN-IR-NEXT:    s_mov_b32 s3, s2
152; GCN-IR-NEXT:    s_sub_u32 s12, s6, s0
153; GCN-IR-NEXT:    s_subb_u32 s13, s7, s0
154; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[8:9]
155; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
156; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
157; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
158; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[12:13], 0
159; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
160; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[14:15]
161; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
162; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
163; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
164; GCN-IR-NEXT:    s_min_u32 s14, s10, s11
165; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s12
166; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
167; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s13
168; GCN-IR-NEXT:    s_min_u32 s18, s10, s11
169; GCN-IR-NEXT:    s_sub_u32 s10, s14, s18
170; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
171; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[10:11], 63
172; GCN-IR-NEXT:    s_mov_b32 s15, 0
173; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[20:21]
174; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[10:11], 63
175; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[16:17], -1
176; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
177; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
178; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
179; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
180; GCN-IR-NEXT:    s_add_u32 s16, s10, 1
181; GCN-IR-NEXT:    s_addc_u32 s17, s11, 0
182; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[20:21], s[16:17], 0
183; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
184; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[20:21]
185; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], s10
186; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
187; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
188; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[12:13], s16
189; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
190; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
191; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
192; GCN-IR-NEXT:    s_add_u32 s12, s8, s18
193; GCN-IR-NEXT:    s_mov_b32 s19, s15
194; GCN-IR-NEXT:    s_addc_u32 s13, s9, s15
195; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
196; GCN-IR-NEXT:    s_mov_b32 s9, 0
197; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
198; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
199; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
200; GCN-IR-NEXT:    s_lshr_b32 s8, s11, 31
201; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
202; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
203; GCN-IR-NEXT:    s_or_b64 s[10:11], s[14:15], s[10:11]
204; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
205; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
206; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
207; GCN-IR-NEXT:    s_mov_b32 s15, s14
208; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
209; GCN-IR-NEXT:    s_and_b64 s[14:15], s[14:15], s[6:7]
210; GCN-IR-NEXT:    s_sub_u32 s16, s16, s14
211; GCN-IR-NEXT:    s_subb_u32 s17, s17, s15
212; GCN-IR-NEXT:    s_add_u32 s12, s12, 1
213; GCN-IR-NEXT:    s_addc_u32 s13, s13, 0
214; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[12:13], 0
215; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
216; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
217; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
218; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
219; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[10:11], 1
220; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
221; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
222; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
223; GCN-IR-NEXT:    s_branch .LBB0_6
224; GCN-IR-NEXT:  .LBB0_5:
225; GCN-IR-NEXT:    v_mov_b32_e32 v0, s13
226; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
227; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
228; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
229; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
230; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
231; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
232; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
233; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
234; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
235; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
236; GCN-IR-NEXT:    s_mov_b32 s6, -1
237; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
238; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
239; GCN-IR-NEXT:    s_endpgm
240  %result = sdiv i64 %x, %y
241  store i64 %result, i64 addrspace(1)* %out
242  ret void
243}
244
245define i64 @v_test_sdiv(i64 %x, i64 %y) {
246; GCN-LABEL: v_test_sdiv:
247; GCN:       ; %bb.0:
248; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
249; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
250; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
251; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
252; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
253; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
254; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
255; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
256; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
257; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
258; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
259; GCN-NEXT:    v_rcp_f32_e32 v5, v5
260; GCN-NEXT:    v_mov_b32_e32 v14, 0
261; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
262; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
263; GCN-NEXT:    v_trunc_f32_e32 v6, v6
264; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
265; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
266; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
267; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
268; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
269; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
270; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
271; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
272; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
273; GCN-NEXT:    v_mul_lo_u32 v11, v5, v9
274; GCN-NEXT:    v_mul_hi_u32 v12, v5, v10
275; GCN-NEXT:    v_mul_hi_u32 v13, v5, v9
276; GCN-NEXT:    v_mul_hi_u32 v15, v6, v9
277; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
278; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
279; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
280; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
281; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
282; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
283; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v10, vcc
284; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v14, vcc
285; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
286; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
287; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
288; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v10, vcc
289; GCN-NEXT:    v_mul_lo_u32 v9, v7, v6
290; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
291; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
292; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
293; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
294; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
295; GCN-NEXT:    v_mul_lo_u32 v11, v5, v8
296; GCN-NEXT:    v_mul_hi_u32 v12, v5, v7
297; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
298; GCN-NEXT:    v_mul_hi_u32 v10, v6, v7
299; GCN-NEXT:    v_mul_lo_u32 v7, v6, v7
300; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
301; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
302; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
303; GCN-NEXT:    v_mul_lo_u32 v8, v6, v8
304; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
305; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v10, vcc
306; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v14, vcc
307; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
308; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
309; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
310; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
311; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
312; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
313; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
314; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
315; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
316; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
317; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
318; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
319; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
320; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
321; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
322; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
323; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
324; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
325; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
326; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
327; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
328; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
329; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
330; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
331; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
332; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
333; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
334; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
335; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
336; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
337; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
338; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
339; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
340; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
341; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
342; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
343; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
344; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
345; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
346; GCN-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
347; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 2, v5
348; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
349; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
350; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
351; GCN-NEXT:    v_add_i32_e64 v12, s[4:5], 1, v5
352; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
353; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
354; GCN-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
355; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
356; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
357; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
358; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
359; GCN-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
360; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
361; GCN-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
362; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
363; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
364; GCN-NEXT:    v_xor_b32_e32 v2, v7, v4
365; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
366; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
367; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
368; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
369; GCN-NEXT:    s_setpc_b64 s[30:31]
370;
371; GCN-IR-LABEL: v_test_sdiv:
372; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
373; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
374; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
375; GCN-IR-NEXT:    v_xor_b32_e32 v0, v4, v0
376; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
377; GCN-IR-NEXT:    v_xor_b32_e32 v1, v4, v1
378; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v0, v4
379; GCN-IR-NEXT:    v_subb_u32_e32 v12, vcc, v1, v4, vcc
380; GCN-IR-NEXT:    v_xor_b32_e32 v1, v5, v2
381; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v3
382; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
383; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v0, v5, vcc
384; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
385; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[11:12]
386; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v2
387; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
388; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
389; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v3
390; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v7
391; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v11
392; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
393; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v12
394; GCN-IR-NEXT:    v_min_u32_e32 v13, v7, v8
395; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v13
396; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
397; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
398; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
399; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
400; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
401; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
402; GCN-IR-NEXT:    v_mov_b32_e32 v6, v4
403; GCN-IR-NEXT:    v_mov_b32_e32 v1, v5
404; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v12, 0, s[6:7]
405; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
406; GCN-IR-NEXT:    v_mov_b32_e32 v16, v17
407; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v11, 0, s[6:7]
408; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
409; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
410; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
411; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
412; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
413; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
414; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[14:15]
415; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[11:12], v7
416; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
417; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
418; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
419; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
420; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
421; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
422; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v2
423; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v3, vcc
424; GCN-IR-NEXT:    v_not_b32_e32 v0, v0
425; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[11:12], v14
426; GCN-IR-NEXT:    v_not_b32_e32 v9, v17
427; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v0, v13
428; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v16, vcc
429; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
430; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
431; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
432; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
433; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
434; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
435; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
436; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v8
437; GCN-IR-NEXT:    v_or_b32_e32 v0, v14, v0
438; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v0
439; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
440; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
441; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
442; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v11
443; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
444; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
445; GCN-IR-NEXT:    v_and_b32_e32 v16, v13, v3
446; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v2
447; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v12, vcc
448; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[11:12]
449; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v0, v13
450; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
451; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v16, s[4:5]
452; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
453; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
454; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
455; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
456; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
457; GCN-IR-NEXT:  ; %bb.4: ; %Flow
458; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
459; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
460; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
461; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[7:8], 1
462; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v3
463; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v2
464; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
465; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
466; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v4
467; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v6
468; GCN-IR-NEXT:    v_xor_b32_e32 v3, v9, v0
469; GCN-IR-NEXT:    v_xor_b32_e32 v2, v10, v1
470; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
471; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
472; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
473  %result = sdiv i64 %x, %y
474  ret i64 %result
475}
476
477define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
478; GCN-LABEL: s_test_sdiv24_64:
479; GCN:       ; %bb.0:
480; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
481; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
482; GCN-NEXT:    s_mov_b32 s3, 0xf000
483; GCN-NEXT:    s_mov_b32 s2, -1
484; GCN-NEXT:    s_waitcnt lgkmcnt(0)
485; GCN-NEXT:    s_mov_b32 s0, s4
486; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
487; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
488; GCN-NEXT:    s_mov_b32 s1, s5
489; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
490; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
491; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
492; GCN-NEXT:    s_xor_b32 s4, s4, s8
493; GCN-NEXT:    s_ashr_i32 s4, s4, 30
494; GCN-NEXT:    s_or_b32 s4, s4, 1
495; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
496; GCN-NEXT:    v_trunc_f32_e32 v2, v2
497; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
498; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
499; GCN-NEXT:    v_mov_b32_e32 v3, s4
500; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
501; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
502; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
503; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
504; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
505; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
506; GCN-NEXT:    s_endpgm
507;
508; GCN-IR-LABEL: s_test_sdiv24_64:
509; GCN-IR:       ; %bb.0:
510; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
511; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
512; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
513; GCN-IR-NEXT:    s_mov_b32 s2, -1
514; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
515; GCN-IR-NEXT:    s_mov_b32 s0, s4
516; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
517; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
518; GCN-IR-NEXT:    s_mov_b32 s1, s5
519; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
520; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
521; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
522; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
523; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
524; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
525; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
526; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
527; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
528; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
529; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
530; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
531; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
532; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
533; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
534; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
535; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
536; GCN-IR-NEXT:    s_endpgm
537  %1 = ashr i64 %x, 40
538  %2 = ashr i64 %y, 40
539  %result = sdiv i64 %1, %2
540  store i64 %result, i64 addrspace(1)* %out
541  ret void
542}
543
544define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
545; GCN-LABEL: v_test_sdiv24_64:
546; GCN:       ; %bb.0:
547; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
548; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
549; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
550; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
551; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
552; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
553; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
554; GCN-NEXT:    v_trunc_f32_e32 v2, v2
555; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
556; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
557; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
558; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
559; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
560; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
561; GCN-NEXT:    s_setpc_b64 s[30:31]
562;
563; GCN-IR-LABEL: v_test_sdiv24_64:
564; GCN-IR:       ; %bb.0:
565; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
566; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
567; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, v0
568; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
569; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v1
570; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
571; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
572; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
573; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
574; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
575; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
576; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
577; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
578; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
579; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
580  %1 = lshr i64 %x, 40
581  %2 = lshr i64 %y, 40
582  %result = sdiv i64 %1, %2
583  ret i64 %result
584}
585
586define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
587; GCN-LABEL: s_test_sdiv32_64:
588; GCN:       ; %bb.0:
589; GCN-NEXT:    s_load_dword s8, s[0:1], 0xe
590; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
591; GCN-NEXT:    s_mov_b32 s7, 0xf000
592; GCN-NEXT:    s_mov_b32 s6, -1
593; GCN-NEXT:    s_waitcnt lgkmcnt(0)
594; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
595; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
596; GCN-NEXT:    s_mov_b32 s4, s0
597; GCN-NEXT:    s_xor_b32 s0, s3, s8
598; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
599; GCN-NEXT:    s_ashr_i32 s0, s0, 30
600; GCN-NEXT:    s_or_b32 s0, s0, 1
601; GCN-NEXT:    v_mov_b32_e32 v3, s0
602; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
603; GCN-NEXT:    v_trunc_f32_e32 v2, v2
604; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
605; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
606; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
607; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
608; GCN-NEXT:    s_mov_b32 s5, s1
609; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
610; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
611; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
612; GCN-NEXT:    s_endpgm
613;
614; GCN-IR-LABEL: s_test_sdiv32_64:
615; GCN-IR:       ; %bb.0:
616; GCN-IR-NEXT:    s_load_dword s8, s[0:1], 0xe
617; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
618; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
619; GCN-IR-NEXT:    s_mov_b32 s6, -1
620; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
621; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
622; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
623; GCN-IR-NEXT:    s_mov_b32 s4, s0
624; GCN-IR-NEXT:    s_xor_b32 s0, s3, s8
625; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
626; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
627; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
628; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
629; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
630; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
631; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
632; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
633; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
634; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
635; GCN-IR-NEXT:    s_mov_b32 s5, s1
636; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
637; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
638; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
639; GCN-IR-NEXT:    s_endpgm
640  %1 = ashr i64 %x, 32
641  %2 = ashr i64 %y, 32
642  %result = sdiv i64 %1, %2
643  store i64 %result, i64 addrspace(1)* %out
644  ret void
645}
646
647define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
648; GCN-LABEL: s_test_sdiv31_64:
649; GCN:       ; %bb.0:
650; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
651; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
652; GCN-NEXT:    s_mov_b32 s3, 0xf000
653; GCN-NEXT:    s_mov_b32 s2, -1
654; GCN-NEXT:    s_waitcnt lgkmcnt(0)
655; GCN-NEXT:    s_mov_b32 s0, s4
656; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
657; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
658; GCN-NEXT:    s_mov_b32 s1, s5
659; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
660; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
661; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
662; GCN-NEXT:    s_xor_b32 s4, s4, s8
663; GCN-NEXT:    s_ashr_i32 s4, s4, 30
664; GCN-NEXT:    s_or_b32 s4, s4, 1
665; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
666; GCN-NEXT:    v_trunc_f32_e32 v2, v2
667; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
668; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
669; GCN-NEXT:    v_mov_b32_e32 v3, s4
670; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
671; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
672; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
673; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
674; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
675; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
676; GCN-NEXT:    s_endpgm
677;
678; GCN-IR-LABEL: s_test_sdiv31_64:
679; GCN-IR:       ; %bb.0:
680; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
681; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
682; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
683; GCN-IR-NEXT:    s_mov_b32 s2, -1
684; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
685; GCN-IR-NEXT:    s_mov_b32 s0, s4
686; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
687; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
688; GCN-IR-NEXT:    s_mov_b32 s1, s5
689; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
690; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
691; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
692; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
693; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
694; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
695; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
696; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
697; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
698; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
699; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
700; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
701; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
702; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
703; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
704; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
705; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
706; GCN-IR-NEXT:    s_endpgm
707  %1 = ashr i64 %x, 33
708  %2 = ashr i64 %y, 33
709  %result = sdiv i64 %1, %2
710  store i64 %result, i64 addrspace(1)* %out
711  ret void
712}
713
714define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
715; GCN-LABEL: s_test_sdiv23_64:
716; GCN:       ; %bb.0:
717; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
718; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
719; GCN-NEXT:    s_mov_b32 s3, 0xf000
720; GCN-NEXT:    s_mov_b32 s2, -1
721; GCN-NEXT:    s_waitcnt lgkmcnt(0)
722; GCN-NEXT:    s_mov_b32 s0, s4
723; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
724; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
725; GCN-NEXT:    s_mov_b32 s1, s5
726; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
727; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
728; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
729; GCN-NEXT:    s_xor_b32 s4, s4, s8
730; GCN-NEXT:    s_ashr_i32 s4, s4, 30
731; GCN-NEXT:    s_or_b32 s4, s4, 1
732; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
733; GCN-NEXT:    v_trunc_f32_e32 v2, v2
734; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
735; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
736; GCN-NEXT:    v_mov_b32_e32 v3, s4
737; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
738; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
739; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
740; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
741; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
742; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
743; GCN-NEXT:    s_endpgm
744;
745; GCN-IR-LABEL: s_test_sdiv23_64:
746; GCN-IR:       ; %bb.0:
747; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
748; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
749; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
750; GCN-IR-NEXT:    s_mov_b32 s2, -1
751; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
752; GCN-IR-NEXT:    s_mov_b32 s0, s4
753; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
754; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
755; GCN-IR-NEXT:    s_mov_b32 s1, s5
756; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
757; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
758; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
759; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
760; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
761; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
762; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
763; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
764; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
765; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
766; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
767; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
768; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
769; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
770; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
771; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
772; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
773; GCN-IR-NEXT:    s_endpgm
774  %1 = ashr i64 %x, 41
775  %2 = ashr i64 %y, 41
776  %result = sdiv i64 %1, %2
777  store i64 %result, i64 addrspace(1)* %out
778  ret void
779}
780
781define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
782; GCN-LABEL: s_test_sdiv25_64:
783; GCN:       ; %bb.0:
784; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
785; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
786; GCN-NEXT:    s_mov_b32 s3, 0xf000
787; GCN-NEXT:    s_mov_b32 s2, -1
788; GCN-NEXT:    s_waitcnt lgkmcnt(0)
789; GCN-NEXT:    s_mov_b32 s0, s4
790; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
791; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
792; GCN-NEXT:    s_mov_b32 s1, s5
793; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
794; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
795; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
796; GCN-NEXT:    s_xor_b32 s4, s4, s8
797; GCN-NEXT:    s_ashr_i32 s4, s4, 30
798; GCN-NEXT:    s_or_b32 s4, s4, 1
799; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
800; GCN-NEXT:    v_trunc_f32_e32 v2, v2
801; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
802; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
803; GCN-NEXT:    v_mov_b32_e32 v3, s4
804; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
805; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
806; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
807; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
808; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
809; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
810; GCN-NEXT:    s_endpgm
811;
812; GCN-IR-LABEL: s_test_sdiv25_64:
813; GCN-IR:       ; %bb.0:
814; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
815; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
816; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
817; GCN-IR-NEXT:    s_mov_b32 s2, -1
818; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
819; GCN-IR-NEXT:    s_mov_b32 s0, s4
820; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
821; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
822; GCN-IR-NEXT:    s_mov_b32 s1, s5
823; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
824; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
825; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
826; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
827; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
828; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
829; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
830; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
831; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
832; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
833; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
834; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
835; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
836; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
837; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
838; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
839; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
840; GCN-IR-NEXT:    s_endpgm
841  %1 = ashr i64 %x, 39
842  %2 = ashr i64 %y, 39
843  %result = sdiv i64 %1, %2
844  store i64 %result, i64 addrspace(1)* %out
845  ret void
846}
847
848define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
849; GCN-LABEL: s_test_sdiv24_v2i64:
850; GCN:       ; %bb.0:
851; GCN-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
852; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
853; GCN-NEXT:    s_mov_b32 s3, 0xf000
854; GCN-NEXT:    s_mov_b32 s2, -1
855; GCN-NEXT:    s_waitcnt lgkmcnt(0)
856; GCN-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
857; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
858; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
859; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
860; GCN-NEXT:    s_xor_b32 s4, s4, s8
861; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
862; GCN-NEXT:    s_ashr_i32 s4, s4, 30
863; GCN-NEXT:    s_or_b32 s4, s4, 1
864; GCN-NEXT:    v_mov_b32_e32 v3, s4
865; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
866; GCN-NEXT:    v_trunc_f32_e32 v2, v2
867; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
868; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
869; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
870; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
871; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
872; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
873; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s10
874; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
875; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s6
876; GCN-NEXT:    s_xor_b32 s4, s6, s10
877; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
878; GCN-NEXT:    s_ashr_i32 s4, s4, 30
879; GCN-NEXT:    s_or_b32 s4, s4, 1
880; GCN-NEXT:    v_mov_b32_e32 v5, s4
881; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
882; GCN-NEXT:    v_trunc_f32_e32 v4, v4
883; GCN-NEXT:    v_mad_f32 v3, -v4, v2, v3
884; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
885; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
886; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
887; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
888; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
889; GCN-NEXT:    v_bfe_i32 v2, v2, 0, 24
890; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
891; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
892; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
893; GCN-NEXT:    s_endpgm
894;
895; GCN-IR-LABEL: s_test_sdiv24_v2i64:
896; GCN-IR:       ; %bb.0:
897; GCN-IR-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
898; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
899; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
900; GCN-IR-NEXT:    s_mov_b32 s2, -1
901; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
902; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
903; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
904; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
905; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
906; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
907; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
908; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
909; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
910; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
911; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
912; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
913; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
914; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
915; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
916; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
917; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
918; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
919; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v2, s10
920; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
921; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, s6
922; GCN-IR-NEXT:    s_xor_b32 s4, s6, s10
923; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v2
924; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
925; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
926; GCN-IR-NEXT:    v_mov_b32_e32 v5, s4
927; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
928; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
929; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v2, v3
930; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
931; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
932; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
933; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
934; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
935; GCN-IR-NEXT:    v_bfe_i32 v2, v2, 0, 24
936; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
937; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
938; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
939; GCN-IR-NEXT:    s_endpgm
940  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
941  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
942  %result = sdiv <2 x i64> %1, %2
943  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
944  ret void
945}
946
947define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
948; GCN-LABEL: s_test_sdiv24_48:
949; GCN:       ; %bb.0:
950; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
951; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
952; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
953; GCN-NEXT:    s_load_dword s8, s[0:1], 0xe
954; GCN-NEXT:    s_load_dword s0, s[0:1], 0xd
955; GCN-NEXT:    s_mov_b32 s7, 0xf000
956; GCN-NEXT:    s_waitcnt lgkmcnt(0)
957; GCN-NEXT:    v_mov_b32_e32 v2, s2
958; GCN-NEXT:    s_sext_i32_i16 s1, s3
959; GCN-NEXT:    s_sext_i32_i16 s3, s8
960; GCN-NEXT:    v_mov_b32_e32 v0, s0
961; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
962; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
963; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
964; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
965; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
966; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
967; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
968; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
969; GCN-NEXT:    s_mov_b32 s6, -1
970; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
971; GCN-NEXT:    v_trunc_f32_e32 v2, v2
972; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
973; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
974; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
975; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
976; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
977; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
978; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
979; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
980; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
981; GCN-NEXT:    s_endpgm
982;
983; GCN-IR-LABEL: s_test_sdiv24_48:
984; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
985; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
986; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
987; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
988; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
989; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
990; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
991; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
992; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
993; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[2:3], 24
994; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
995; GCN-IR-NEXT:    s_mov_b32 s3, s2
996; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 24
997; GCN-IR-NEXT:    s_ashr_i32 s4, s5, 31
998; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[6:7]
999; GCN-IR-NEXT:    s_mov_b32 s5, s4
1000; GCN-IR-NEXT:    s_sub_u32 s12, s6, s2
1001; GCN-IR-NEXT:    s_subb_u32 s13, s7, s2
1002; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], s[8:9]
1003; GCN-IR-NEXT:    s_sub_u32 s6, s6, s4
1004; GCN-IR-NEXT:    s_subb_u32 s7, s7, s4
1005; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1006; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[12:13], 0
1007; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1008; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[14:15]
1009; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1010; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1011; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1012; GCN-IR-NEXT:    s_min_u32 s14, s10, s11
1013; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s12
1014; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1015; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s13
1016; GCN-IR-NEXT:    s_min_u32 s18, s10, s11
1017; GCN-IR-NEXT:    s_sub_u32 s10, s14, s18
1018; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
1019; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[10:11], 63
1020; GCN-IR-NEXT:    s_mov_b32 s15, 0
1021; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[20:21]
1022; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[10:11], 63
1023; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[16:17], -1
1024; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
1025; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1026; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_5
1027; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1028; GCN-IR-NEXT:    s_add_u32 s16, s10, 1
1029; GCN-IR-NEXT:    s_addc_u32 s17, s11, 0
1030; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[20:21], s[16:17], 0
1031; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
1032; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[20:21]
1033; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], s10
1034; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_4
1035; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1036; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[12:13], s16
1037; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
1038; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
1039; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
1040; GCN-IR-NEXT:    s_add_u32 s12, s8, s18
1041; GCN-IR-NEXT:    s_mov_b32 s19, s15
1042; GCN-IR-NEXT:    s_addc_u32 s13, s9, s15
1043; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1044; GCN-IR-NEXT:    s_mov_b32 s9, 0
1045; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1046; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1047; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1048; GCN-IR-NEXT:    s_lshr_b32 s8, s11, 31
1049; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1050; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1051; GCN-IR-NEXT:    s_or_b64 s[10:11], s[14:15], s[10:11]
1052; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
1053; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
1054; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1055; GCN-IR-NEXT:    s_mov_b32 s15, s14
1056; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1057; GCN-IR-NEXT:    s_and_b64 s[14:15], s[14:15], s[6:7]
1058; GCN-IR-NEXT:    s_sub_u32 s16, s16, s14
1059; GCN-IR-NEXT:    s_subb_u32 s17, s17, s15
1060; GCN-IR-NEXT:    s_add_u32 s12, s12, 1
1061; GCN-IR-NEXT:    s_addc_u32 s13, s13, 0
1062; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[12:13], 0
1063; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1064; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1065; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_3
1066; GCN-IR-NEXT:  .LBB9_4: ; %Flow3
1067; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[10:11], 1
1068; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1069; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1070; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1071; GCN-IR-NEXT:    s_branch .LBB9_6
1072; GCN-IR-NEXT:  .LBB9_5:
1073; GCN-IR-NEXT:    v_mov_b32_e32 v0, s13
1074; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1075; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1076; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1077; GCN-IR-NEXT:  .LBB9_6: ; %udiv-end
1078; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1079; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1080; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1081; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1082; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1083; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1084; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1085; GCN-IR-NEXT:    s_mov_b32 s2, -1
1086; GCN-IR-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
1087; GCN-IR-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1088; GCN-IR-NEXT:    s_endpgm
1089  %1 = ashr i48 %x, 24
1090  %2 = ashr i48 %y, 24
1091  %result = sdiv i48 %1, %2
1092  store i48 %result, i48 addrspace(1)* %out
1093  ret void
1094}
1095
1096define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1097; GCN-LABEL: s_test_sdiv_k_num_i64:
1098; GCN:       ; %bb.0:
1099; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1100; GCN-NEXT:    s_mov_b32 s7, 0xf000
1101; GCN-NEXT:    s_mov_b32 s6, -1
1102; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1103; GCN-NEXT:    s_ashr_i32 s8, s3, 31
1104; GCN-NEXT:    s_add_u32 s2, s2, s8
1105; GCN-NEXT:    s_mov_b32 s9, s8
1106; GCN-NEXT:    s_addc_u32 s3, s3, s8
1107; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
1108; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1109; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
1110; GCN-NEXT:    s_sub_u32 s4, 0, s2
1111; GCN-NEXT:    s_subb_u32 s5, 0, s3
1112; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1113; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1114; GCN-NEXT:    v_mov_b32_e32 v1, 0
1115; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1116; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
1117; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1118; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
1119; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1120; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1121; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
1122; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
1123; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
1124; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
1125; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1126; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1127; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
1128; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1129; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
1130; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1131; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
1132; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
1133; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1134; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
1135; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1136; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1137; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
1138; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
1139; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1140; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
1141; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1142; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
1143; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
1144; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
1145; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
1146; GCN-NEXT:    s_mov_b32 s5, s1
1147; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1148; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
1149; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1150; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
1151; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
1152; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
1153; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
1154; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
1155; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
1156; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1157; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1158; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1159; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1160; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
1161; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
1162; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1163; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1164; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1165; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1166; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1167; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1168; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1169; GCN-NEXT:    v_mov_b32_e32 v4, s3
1170; GCN-NEXT:    s_mov_b32 s4, s0
1171; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1172; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
1173; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0
1174; GCN-NEXT:    v_mul_hi_u32 v2, s2, v0
1175; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1176; GCN-NEXT:    v_mul_lo_u32 v2, s2, v0
1177; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
1178; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1179; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
1180; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v2
1181; GCN-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
1182; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v3
1183; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1184; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v4
1185; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
1186; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v3
1187; GCN-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
1188; GCN-NEXT:    v_add_i32_e64 v4, s[0:1], 2, v0
1189; GCN-NEXT:    v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
1190; GCN-NEXT:    v_add_i32_e64 v6, s[0:1], 1, v0
1191; GCN-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
1192; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1193; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
1194; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
1195; GCN-NEXT:    v_cndmask_b32_e64 v3, v7, v5, s[0:1]
1196; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1197; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
1198; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
1199; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
1200; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
1201; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1202; GCN-NEXT:    v_cndmask_b32_e64 v2, v6, v4, s[0:1]
1203; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1204; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
1205; GCN-NEXT:    v_xor_b32_e32 v0, s8, v0
1206; GCN-NEXT:    v_xor_b32_e32 v1, s8, v1
1207; GCN-NEXT:    v_mov_b32_e32 v2, s8
1208; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
1209; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1210; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1211; GCN-NEXT:    s_endpgm
1212;
1213; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1214; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1215; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1216; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1217; GCN-IR-NEXT:    s_ashr_i32 s4, s3, 31
1218; GCN-IR-NEXT:    s_mov_b32 s5, s4
1219; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1220; GCN-IR-NEXT:    s_sub_u32 s2, s2, s4
1221; GCN-IR-NEXT:    s_subb_u32 s3, s3, s4
1222; GCN-IR-NEXT:    s_flbit_i32_b32 s6, s2
1223; GCN-IR-NEXT:    s_add_i32 s6, s6, 32
1224; GCN-IR-NEXT:    s_flbit_i32_b32 s7, s3
1225; GCN-IR-NEXT:    s_min_u32 s10, s6, s7
1226; GCN-IR-NEXT:    s_add_u32 s8, s10, 0xffffffc5
1227; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1228; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1229; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[14:15], s[8:9], 63
1230; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1231; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
1232; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[14:15], s[8:9], 63
1233; GCN-IR-NEXT:    s_xor_b64 s[16:17], s[12:13], -1
1234; GCN-IR-NEXT:    s_and_b64 s[14:15], s[16:17], s[14:15]
1235; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
1236; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_5
1237; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1238; GCN-IR-NEXT:    s_add_u32 s12, s8, 1
1239; GCN-IR-NEXT:    s_addc_u32 s13, s9, 0
1240; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[12:13], 0
1241; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
1242; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[14:15]
1243; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s8
1244; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_4
1245; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1246; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s12
1247; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
1248; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
1249; GCN-IR-NEXT:    s_sub_u32 s10, 58, s10
1250; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
1251; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1252; GCN-IR-NEXT:    s_mov_b32 s7, 0
1253; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1254; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1255; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1256; GCN-IR-NEXT:    s_lshr_b32 s6, s9, 31
1257; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1258; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[6:7]
1259; GCN-IR-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
1260; GCN-IR-NEXT:    s_sub_u32 s6, s16, s12
1261; GCN-IR-NEXT:    s_subb_u32 s6, s17, s13
1262; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
1263; GCN-IR-NEXT:    s_mov_b32 s15, s14
1264; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
1265; GCN-IR-NEXT:    s_and_b64 s[14:15], s[14:15], s[2:3]
1266; GCN-IR-NEXT:    s_sub_u32 s12, s12, s14
1267; GCN-IR-NEXT:    s_subb_u32 s13, s13, s15
1268; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1269; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1270; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
1271; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
1272; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1273; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_3
1274; GCN-IR-NEXT:  .LBB10_4: ; %Flow5
1275; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[8:9], 1
1276; GCN-IR-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
1277; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1278; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1279; GCN-IR-NEXT:    s_branch .LBB10_6
1280; GCN-IR-NEXT:  .LBB10_5:
1281; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1282; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[12:13]
1283; GCN-IR-NEXT:  .LBB10_6: ; %udiv-end
1284; GCN-IR-NEXT:    v_xor_b32_e32 v0, s4, v0
1285; GCN-IR-NEXT:    v_xor_b32_e32 v1, s5, v1
1286; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1287; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
1288; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1289; GCN-IR-NEXT:    s_mov_b32 s2, -1
1290; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1291; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1292; GCN-IR-NEXT:    s_endpgm
1293  %result = sdiv i64 24, %x
1294  store i64 %result, i64 addrspace(1)* %out
1295  ret void
1296}
1297
1298define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1299; GCN-LABEL: v_test_sdiv_k_num_i64:
1300; GCN:       ; %bb.0:
1301; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1302; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1303; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1304; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1305; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1306; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1307; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1308; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1309; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1310; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1311; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1312; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1313; GCN-NEXT:    v_mov_b32_e32 v12, 0
1314; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1315; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1316; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1317; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1318; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1319; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1320; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1321; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1322; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1323; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1324; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1325; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1326; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
1327; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
1328; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
1329; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
1330; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1331; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1332; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1333; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1334; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1335; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
1336; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
1337; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
1338; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1339; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1340; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1341; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1342; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1343; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1344; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1345; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1346; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1347; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1348; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1349; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1350; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1351; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1352; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1353; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1354; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1355; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1356; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1357; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1358; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1359; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1360; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1361; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
1362; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1363; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
1364; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
1365; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1366; GCN-NEXT:    v_mul_hi_u32 v4, v4, 24
1367; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1368; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1369; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1370; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1371; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1372; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1373; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1374; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 24, v5
1375; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1376; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1377; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1378; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1379; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1380; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1381; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1382; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1383; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1384; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1385; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1386; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1387; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1388; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1389; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1390; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1391; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1392; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1393; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1394; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1395; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1396; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1397; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1398; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1399; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1400; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1401; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1402; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1403; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1404; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1405; GCN-NEXT:    s_setpc_b64 s[30:31]
1406;
1407; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1408; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1409; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1410; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1411; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1412; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1413; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1414; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1415; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1416; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1417; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1418; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1419; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1420; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1421; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1422; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1423; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1424; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1425; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1426; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1427; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, 24, 0, s[4:5]
1428; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1429; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1430; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1431; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1432; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1433; GCN-IR-NEXT:    s_cbranch_execz .LBB11_6
1434; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1435; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1436; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1437; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1438; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[10:11]
1439; GCN-IR-NEXT:    v_lshl_b64 v[4:5], 24, v4
1440; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1441; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1442; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1443; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1444; GCN-IR-NEXT:    s_cbranch_execz .LBB11_5
1445; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1446; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1447; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1448; GCN-IR-NEXT:    v_lshr_b64 v[10:11], 24, v10
1449; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 58, v8
1450; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1451; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1452; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1453; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1454; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1455; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1456; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1457; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1458; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1459; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1460; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1461; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1462; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1463; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1464; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1465; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v8
1466; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1467; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1468; GCN-IR-NEXT:    v_and_b32_e32 v13, v12, v1
1469; GCN-IR-NEXT:    v_and_b32_e32 v12, v12, v0
1470; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
1471; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
1472; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v12
1473; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
1474; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1475; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1476; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1477; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1478; GCN-IR-NEXT:    s_cbranch_execnz .LBB11_3
1479; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1480; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1481; GCN-IR-NEXT:  .LBB11_5: ; %Flow3
1482; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1483; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1484; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1485; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1486; GCN-IR-NEXT:  .LBB11_6: ; %Flow4
1487; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1488; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1489; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1490; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1491; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1492; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1493  %result = sdiv i64 24, %x
1494  ret i64 %result
1495}
1496
1497define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1498; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1499; GCN:       ; %bb.0:
1500; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1501; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1502; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1503; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1504; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1505; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1506; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1507; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1508; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1509; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1510; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1511; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1512; GCN-NEXT:    v_mov_b32_e32 v12, 0
1513; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1514; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1515; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1516; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1517; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1518; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1519; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1520; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1521; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1522; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1523; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1524; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1525; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
1526; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
1527; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
1528; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
1529; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1530; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1531; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1532; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1533; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1534; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
1535; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
1536; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
1537; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1538; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1539; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1540; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1541; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1542; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1543; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1544; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1545; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1546; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1547; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1548; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1549; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1550; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1551; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1552; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1553; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1554; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1555; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1556; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1557; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1558; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1559; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1560; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
1561; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1562; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v4, v6, vcc
1563; GCN-NEXT:    v_lshrrev_b32_e32 v3, 17, v3
1564; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1565; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1566; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1567; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1568; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1569; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0x8000, v5
1570; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1571; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1572; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1573; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1574; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1575; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1576; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1577; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1578; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1579; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1580; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1581; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1582; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1583; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1584; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1585; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1586; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1587; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1588; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1589; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1590; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1591; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1592; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1593; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1594; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1595; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1596; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1597; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1598; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1599; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1600; GCN-NEXT:    s_setpc_b64 s[30:31]
1601;
1602; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1603; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1604; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1605; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1606; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1607; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1608; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1609; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1610; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1611; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1612; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1613; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1614; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1615; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1616; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1617; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1618; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1619; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1620; GCN-IR-NEXT:    v_mov_b32_e32 v6, s8
1621; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1622; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1623; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1624; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[4:5]
1625; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1626; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1627; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1628; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1629; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1630; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1631; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1632; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1633; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1634; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1635; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[10:11]
1636; GCN-IR-NEXT:    v_lshl_b64 v[4:5], s[8:9], v4
1637; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1638; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1639; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1640; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1641; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1642; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1643; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1644; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1645; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1646; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v10
1647; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1648; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1649; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1650; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1651; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1652; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1653; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1654; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1655; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1656; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1657; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1658; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1659; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1660; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1661; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1662; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1663; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v8
1664; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1665; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1666; GCN-IR-NEXT:    v_and_b32_e32 v13, v12, v1
1667; GCN-IR-NEXT:    v_and_b32_e32 v12, v12, v0
1668; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
1669; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
1670; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v12
1671; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
1672; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1673; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1674; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1675; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1676; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1677; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1678; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1679; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1680; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1681; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1682; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1683; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1684; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1685; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1686; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1687; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1688; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1689; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1690; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1691  %result = sdiv i64 32768, %x
1692  ret i64 %result
1693}
1694
1695define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1696; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1697; GCN:       ; %bb.0:
1698; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1699; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1700; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1701; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1702; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1703; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1704; GCN-NEXT:    s_setpc_b64 s[30:31]
1705;
1706; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1707; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1708; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1709; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1710; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1711; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1712; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v2
1713; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v1, v2, vcc
1714; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v7
1715; GCN-IR-NEXT:    v_add_i32_e64 v0, s[4:5], 32, v0
1716; GCN-IR-NEXT:    v_ffbh_u32_e32 v1, v8
1717; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v1
1718; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 48, v0
1719; GCN-IR-NEXT:    v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1720; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1721; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1722; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1723; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1724; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1725; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1726; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1727; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1728; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1729; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1730; GCN-IR-NEXT:    s_cbranch_execz .LBB13_6
1731; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1732; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
1733; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
1734; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v3
1735; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[9:10]
1736; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[7:8], v3
1737; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1738; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1739; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1740; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1741; GCN-IR-NEXT:    s_cbranch_execz .LBB13_5
1742; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1743; GCN-IR-NEXT:    v_lshr_b64 v[9:10], v[7:8], v9
1744; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1745; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1746; GCN-IR-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1747; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1748; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1749; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1750; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1751; GCN-IR-NEXT:  .LBB13_3: ; %udiv-do-while
1752; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1753; GCN-IR-NEXT:    v_lshl_b64 v[9:10], v[9:10], 1
1754; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v4
1755; GCN-IR-NEXT:    v_or_b32_e32 v0, v9, v0
1756; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, s12, v0
1757; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v10, vcc
1758; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v7
1759; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1760; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
1761; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
1762; GCN-IR-NEXT:    v_and_b32_e32 v5, 1, v9
1763; GCN-IR-NEXT:    v_and_b32_e32 v9, 0x8000, v9
1764; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1765; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1766; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1767; GCN-IR-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v9
1768; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1769; GCN-IR-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5]
1770; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1771; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1772; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1773; GCN-IR-NEXT:    s_cbranch_execnz .LBB13_3
1774; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1775; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1776; GCN-IR-NEXT:  .LBB13_5: ; %Flow3
1777; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1778; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1779; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1780; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1781; GCN-IR-NEXT:  .LBB13_6: ; %Flow4
1782; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1783; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v2
1784; GCN-IR-NEXT:    v_xor_b32_e32 v3, v6, v1
1785; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1786; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
1787; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1788  %result = sdiv i64 %x, 32768
1789  ret i64 %result
1790}
1791
1792define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1793; GCN-LABEL: s_test_sdiv24_k_num_i64:
1794; GCN:       ; %bb.0:
1795; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1796; GCN-NEXT:    s_mov_b32 s7, 0xf000
1797; GCN-NEXT:    s_mov_b32 s6, -1
1798; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1799; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1800; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1801; GCN-NEXT:    s_mov_b32 s3, 0x41c00000
1802; GCN-NEXT:    s_mov_b32 s4, s0
1803; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1804; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1805; GCN-NEXT:    s_or_b32 s0, s0, 1
1806; GCN-NEXT:    v_mov_b32_e32 v3, s0
1807; GCN-NEXT:    s_mov_b32 s5, s1
1808; GCN-NEXT:    v_mul_f32_e32 v1, s3, v1
1809; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1810; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s3
1811; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1812; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1813; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1814; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1815; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1816; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1817; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1818; GCN-NEXT:    s_endpgm
1819;
1820; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1821; GCN-IR:       ; %bb.0:
1822; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1823; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1824; GCN-IR-NEXT:    s_mov_b32 s6, -1
1825; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1826; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1827; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1828; GCN-IR-NEXT:    s_mov_b32 s3, 0x41c00000
1829; GCN-IR-NEXT:    s_mov_b32 s4, s0
1830; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1831; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1832; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1833; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
1834; GCN-IR-NEXT:    s_mov_b32 s5, s1
1835; GCN-IR-NEXT:    v_mul_f32_e32 v1, s3, v1
1836; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1837; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s3
1838; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1839; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1840; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1841; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1842; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1843; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1844; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1845; GCN-IR-NEXT:    s_endpgm
1846  %x.shr = ashr i64 %x, 40
1847  %result = sdiv i64 24, %x.shr
1848  store i64 %result, i64 addrspace(1)* %out
1849  ret void
1850}
1851
1852define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1853; GCN-LABEL: s_test_sdiv24_k_den_i64:
1854; GCN:       ; %bb.0:
1855; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1856; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1857; GCN-NEXT:    s_mov_b32 s7, 0xf000
1858; GCN-NEXT:    s_mov_b32 s6, -1
1859; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1860; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1861; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1862; GCN-NEXT:    s_mov_b32 s4, s0
1863; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1864; GCN-NEXT:    s_or_b32 s0, s0, 1
1865; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1866; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1867; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
1868; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1869; GCN-NEXT:    v_mov_b32_e32 v2, s0
1870; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1871; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1872; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1873; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1874; GCN-NEXT:    s_mov_b32 s5, s1
1875; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1876; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1877; GCN-NEXT:    s_endpgm
1878;
1879; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1880; GCN-IR:       ; %bb.0:
1881; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1882; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
1883; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1884; GCN-IR-NEXT:    s_mov_b32 s6, -1
1885; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1886; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1887; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1888; GCN-IR-NEXT:    s_mov_b32 s4, s0
1889; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1890; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1891; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1892; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1893; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
1894; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1895; GCN-IR-NEXT:    v_mov_b32_e32 v2, s0
1896; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1897; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1898; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1899; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1900; GCN-IR-NEXT:    s_mov_b32 s5, s1
1901; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1902; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1903; GCN-IR-NEXT:    s_endpgm
1904  %x.shr = ashr i64 %x, 40
1905  %result = sdiv i64 %x.shr, 23423
1906  store i64 %result, i64 addrspace(1)* %out
1907  ret void
1908}
1909
1910define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
1911; GCN-LABEL: v_test_sdiv24_k_num_i64:
1912; GCN:       ; %bb.0:
1913; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1914; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1915; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1916; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1917; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1918; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1919; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1920; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1921; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1922; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1923; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1924; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1925; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1926; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1927; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1928; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1929; GCN-NEXT:    s_setpc_b64 s[30:31]
1930;
1931; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
1932; GCN-IR:       ; %bb.0:
1933; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1934; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1935; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1936; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1937; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1938; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
1939; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1940; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1941; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1942; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
1943; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
1944; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1945; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1946; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1947; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1948; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1949; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1950  %x.shr = ashr i64 %x, 40
1951  %result = sdiv i64 24, %x.shr
1952  ret i64 %result
1953}
1954
1955define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
1956; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
1957; GCN:       ; %bb.0:
1958; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1959; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1960; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1961; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1962; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1963; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1964; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1965; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1966; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1967; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1968; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1969; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1970; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1971; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1972; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1973; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1974; GCN-NEXT:    s_setpc_b64 s[30:31]
1975;
1976; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
1977; GCN-IR:       ; %bb.0:
1978; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1979; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1980; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1981; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1982; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1983; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
1984; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1985; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1986; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1987; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
1988; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
1989; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1990; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1991; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1992; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1993; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1994; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1995  %x.shr = ashr i64 %x, 40
1996  %result = sdiv i64 32768, %x.shr
1997  ret i64 %result
1998}
1999
2000define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
2001; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
2002; GCN:       ; %bb.0:
2003; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2004; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2005; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2006; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2007; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2008; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
2009; GCN-NEXT:    s_setpc_b64 s[30:31]
2010;
2011; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
2012; GCN-IR:       ; %bb.0:
2013; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2014; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2015; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2016; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2017; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2018; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2019; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
2020; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2021; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
2022; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2023; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2024; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2025; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2026; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2027; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2028; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2029  %x.shr = ashr i64 %x, 40
2030  %result = sdiv i64 %x.shr, 32768
2031  ret i64 %result
2032}
2033