1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_sdiv:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    v_mov_b32_e32 v7, 0
10; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    s_ashr_i32 s12, s3, 31
15; GCN-NEXT:    s_add_u32 s2, s2, s12
16; GCN-NEXT:    s_mov_b32 s13, s12
17; GCN-NEXT:    s_addc_u32 s3, s3, s12
18; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
19; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
20; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
21; GCN-NEXT:    s_sub_u32 s4, 0, s2
22; GCN-NEXT:    s_subb_u32 s5, 0, s3
23; GCN-NEXT:    s_ashr_i32 s14, s11, 31
24; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
25; GCN-NEXT:    v_rcp_f32_e32 v0, v0
26; GCN-NEXT:    v_mov_b32_e32 v1, 0
27; GCN-NEXT:    s_mov_b32 s15, s14
28; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
29; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
30; GCN-NEXT:    v_trunc_f32_e32 v2, v2
31; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
32; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
33; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
34; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
35; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
36; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
37; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
38; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
39; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
40; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
41; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
42; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
43; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
44; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
45; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
47; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
48; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
49; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
50; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
51; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
52; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
53; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
54; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
55; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
56; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
57; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
58; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
59; GCN-NEXT:    s_mov_b32 s5, s9
60; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
61; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
62; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
63; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
64; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
65; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
66; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
67; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
68; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
69; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
70; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
71; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
72; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
73; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
74; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
75; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
76; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
77; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
78; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
79; GCN-NEXT:    s_add_u32 s0, s10, s14
80; GCN-NEXT:    s_addc_u32 s1, s11, s14
81; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
82; GCN-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
83; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
84; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
85; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
86; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
87; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
88; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
89; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
90; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
91; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
92; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
93; GCN-NEXT:    s_mov_b32 s4, s8
94; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
95; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
96; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
97; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
98; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
99; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
100; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
101; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
102; GCN-NEXT:    v_mov_b32_e32 v5, s3
103; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
104; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
105; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
106; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
107; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
108; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
109; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
110; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
111; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
112; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
113; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
114; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
115; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
116; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
117; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
118; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
119; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
120; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
121; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
122; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
123; GCN-NEXT:    v_mov_b32_e32 v6, s11
124; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
125; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
126; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
127; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
128; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
129; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
130; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
131; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
132; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
133; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
134; GCN-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
135; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
136; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
137; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
138; GCN-NEXT:    v_mov_b32_e32 v2, s1
139; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
140; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
141; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
142; GCN-NEXT:    s_endpgm
143;
144; GCN-IR-LABEL: s_test_sdiv:
145; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
146; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
147; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
148; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
149; GCN-IR-NEXT:    s_ashr_i32 s2, s7, 31
150; GCN-IR-NEXT:    s_mov_b32 s3, s2
151; GCN-IR-NEXT:    s_ashr_i32 s8, s1, 31
152; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[6:7]
153; GCN-IR-NEXT:    s_sub_u32 s10, s6, s2
154; GCN-IR-NEXT:    s_mov_b32 s9, s8
155; GCN-IR-NEXT:    s_subb_u32 s11, s7, s2
156; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[8:9], s[0:1]
157; GCN-IR-NEXT:    s_sub_u32 s6, s0, s8
158; GCN-IR-NEXT:    s_flbit_i32_b32 s14, s6
159; GCN-IR-NEXT:    s_subb_u32 s7, s1, s8
160; GCN-IR-NEXT:    s_add_i32 s14, s14, 32
161; GCN-IR-NEXT:    s_flbit_i32_b32 s15, s7
162; GCN-IR-NEXT:    v_mov_b32_e32 v1, s14
163; GCN-IR-NEXT:    s_flbit_i32_b32 s14, s10
164; GCN-IR-NEXT:    v_mov_b32_e32 v0, s15
165; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
166; GCN-IR-NEXT:    s_add_i32 s14, s14, 32
167; GCN-IR-NEXT:    s_flbit_i32_b32 s15, s11
168; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
169; GCN-IR-NEXT:    v_mov_b32_e32 v0, s15
170; GCN-IR-NEXT:    v_mov_b32_e32 v1, s14
171; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s11, 0
172; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
173; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
174; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[14:15], 0, 0, vcc
175; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
176; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
177; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
178; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], s[12:13]
179; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
180; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[0:1]
181; GCN-IR-NEXT:    s_xor_b64 s[12:13], s[0:1], -1
182; GCN-IR-NEXT:    s_and_b64 s[12:13], s[12:13], vcc
183; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
184; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
185; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
186; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
187; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
188; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
189; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
190; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[10:11], v0
191; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
192; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
193; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
194; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
195; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[10:11], v4
196; GCN-IR-NEXT:    s_add_u32 s10, s6, -1
197; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
198; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
199; GCN-IR-NEXT:    s_addc_u32 s11, s7, -1
200; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
201; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
202; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
203; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
204; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
205; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
206; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
207; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
208; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
209; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
210; GCN-IR-NEXT:    v_mov_b32_e32 v2, s11
211; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s10, v6
212; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
213; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
214; GCN-IR-NEXT:    v_and_b32_e32 v10, s6, v8
215; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
216; GCN-IR-NEXT:    v_and_b32_e32 v11, s7, v8
217; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
218; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
219; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
220; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
221; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
222; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
223; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
224; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
225; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
226; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
227; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
228; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
229; GCN-IR-NEXT:    s_branch BB0_6
230; GCN-IR-NEXT:  BB0_4:
231; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
232; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[0:1]
233; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
234; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]
235; GCN-IR-NEXT:    s_branch BB0_7
236; GCN-IR-NEXT:  BB0_5:
237; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
238; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
239; GCN-IR-NEXT:  BB0_6: ; %Flow6
240; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
241; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
242; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
243; GCN-IR-NEXT:  BB0_7: ; %udiv-end
244; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[8:9], s[2:3]
245; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
246; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
247; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
248; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
249; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
250; GCN-IR-NEXT:    s_mov_b32 s6, -1
251; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
252; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
253; GCN-IR-NEXT:    s_endpgm
254  %result = sdiv i64 %x, %y
255  store i64 %result, i64 addrspace(1)* %out
256  ret void
257}
258
259define i64 @v_test_sdiv(i64 %x, i64 %y) {
260; GCN-LABEL: v_test_sdiv:
261; GCN:       ; %bb.0:
262; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
263; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
264; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
265; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
266; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
267; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
268; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
269; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
270; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
271; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
272; GCN-NEXT:    v_mov_b32_e32 v15, 0
273; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
274; GCN-NEXT:    v_rcp_f32_e32 v5, v5
275; GCN-NEXT:    v_mov_b32_e32 v14, 0
276; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
277; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
278; GCN-NEXT:    v_trunc_f32_e32 v6, v6
279; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
280; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
281; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
282; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
283; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
284; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
285; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
286; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
287; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
288; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
289; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
290; GCN-NEXT:    v_mul_hi_u32 v13, v5, v10
291; GCN-NEXT:    v_mul_hi_u32 v16, v6, v9
292; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
293; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
294; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
295; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
296; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v11, vcc
297; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
298; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v10, vcc
299; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v16, v14, vcc
300; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
301; GCN-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
302; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v11, vcc
303; GCN-NEXT:    v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
304; GCN-NEXT:    v_mul_lo_u32 v11, v7, v9
305; GCN-NEXT:    v_mul_hi_u32 v12, v7, v5
306; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
307; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
308; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
309; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
310; GCN-NEXT:    v_mul_lo_u32 v13, v5, v8
311; GCN-NEXT:    v_mul_hi_u32 v16, v5, v7
312; GCN-NEXT:    v_mul_hi_u32 v17, v5, v8
313; GCN-NEXT:    v_mul_hi_u32 v12, v9, v7
314; GCN-NEXT:    v_mul_lo_u32 v7, v9, v7
315; GCN-NEXT:    v_add_i32_e32 v13, vcc, v16, v13
316; GCN-NEXT:    v_mul_hi_u32 v11, v9, v8
317; GCN-NEXT:    v_addc_u32_e32 v16, vcc, v15, v17, vcc
318; GCN-NEXT:    v_mul_lo_u32 v8, v9, v8
319; GCN-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
320; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v16, v12, vcc
321; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v14, vcc
322; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
323; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v15, v9, vcc
324; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
325; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
326; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
327; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
328; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
329; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
330; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
331; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
332; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
333; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
334; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
335; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
336; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
337; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v15, v10, vcc
338; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
339; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
340; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
341; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
342; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
343; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
344; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
345; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
346; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v8, vcc
347; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
348; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
349; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
350; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
351; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
352; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
353; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
354; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
355; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
356; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
357; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
358; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
359; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
360; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
361; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
362; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
363; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
364; GCN-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
365; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 2, v5
366; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
367; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
368; GCN-NEXT:    v_add_i32_e64 v12, s[4:5], 1, v5
369; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
370; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
371; GCN-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
372; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
373; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
374; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
375; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
376; GCN-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
377; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
378; GCN-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
379; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
380; GCN-NEXT:    v_xor_b32_e32 v2, v7, v4
381; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
382; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
383; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
384; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
385; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
386; GCN-NEXT:    s_setpc_b64 s[30:31]
387;
388; GCN-IR-LABEL: v_test_sdiv:
389; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
390; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
391; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
392; GCN-IR-NEXT:    v_xor_b32_e32 v0, v4, v0
393; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
394; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v0, v4
395; GCN-IR-NEXT:    v_xor_b32_e32 v1, v4, v1
396; GCN-IR-NEXT:    v_subb_u32_e32 v10, vcc, v1, v4, vcc
397; GCN-IR-NEXT:    v_xor_b32_e32 v1, v5, v2
398; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
399; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v3
400; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v0, v5, vcc
401; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
402; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[9:10]
403; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v2
404; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
405; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
406; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v3
407; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
408; GCN-IR-NEXT:    v_cndmask_b32_e32 v13, v7, v0, vcc
409; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v9
410; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
411; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v10
412; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
413; GCN-IR-NEXT:    v_cndmask_b32_e32 v14, v7, v0, vcc
414; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v13, v14
415; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
416; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
417; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
418; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
419; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
420; GCN-IR-NEXT:    v_mov_b32_e32 v18, 0
421; GCN-IR-NEXT:    v_mov_b32_e32 v6, v4
422; GCN-IR-NEXT:    v_mov_b32_e32 v1, v5
423; GCN-IR-NEXT:    v_cndmask_b32_e64 v12, v10, 0, s[6:7]
424; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
425; GCN-IR-NEXT:    v_mov_b32_e32 v15, v18
426; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v9, 0, s[6:7]
427; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
428; GCN-IR-NEXT:    s_cbranch_execz BB1_6
429; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
430; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v7
431; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v8, vcc
432; GCN-IR-NEXT:    v_sub_i32_e64 v0, s[4:5], 63, v7
433; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[16:17], v[7:8]
434; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
435; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[9:10], v0
436; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
437; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
438; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
439; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
440; GCN-IR-NEXT:    s_cbranch_execz BB1_5
441; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
442; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, -1, v2
443; GCN-IR-NEXT:    v_lshr_b64 v[16:17], v[9:10], v16
444; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, -1, v3, vcc
445; GCN-IR-NEXT:    v_not_b32_e32 v10, v13
446; GCN-IR-NEXT:    v_not_b32_e32 v11, v18
447; GCN-IR-NEXT:    v_add_i32_e32 v13, vcc, v10, v14
448; GCN-IR-NEXT:    v_mov_b32_e32 v18, 0
449; GCN-IR-NEXT:    v_addc_u32_e32 v14, vcc, v11, v15, vcc
450; GCN-IR-NEXT:    v_mov_b32_e32 v19, 0
451; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
452; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
453; GCN-IR-NEXT:    v_lshl_b64 v[16:17], v[16:17], 1
454; GCN-IR-NEXT:    v_lshrrev_b32_e32 v10, 31, v8
455; GCN-IR-NEXT:    v_or_b32_e32 v10, v16, v10
456; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
457; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v0, v10
458; GCN-IR-NEXT:    v_subb_u32_e32 v11, vcc, v9, v17, vcc
459; GCN-IR-NEXT:    v_or_b32_e32 v7, v18, v7
460; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, 1, v13
461; GCN-IR-NEXT:    v_ashrrev_i32_e32 v15, 31, v11
462; GCN-IR-NEXT:    v_or_b32_e32 v8, v19, v8
463; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, 0, v14, vcc
464; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[18:19], v[13:14]
465; GCN-IR-NEXT:    v_mov_b32_e32 v13, v18
466; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
467; GCN-IR-NEXT:    v_and_b32_e32 v11, 1, v15
468; GCN-IR-NEXT:    v_and_b32_e32 v20, v15, v3
469; GCN-IR-NEXT:    v_and_b32_e32 v15, v15, v2
470; GCN-IR-NEXT:    v_sub_i32_e64 v16, s[4:5], v10, v15
471; GCN-IR-NEXT:    v_mov_b32_e32 v14, v19
472; GCN-IR-NEXT:    v_mov_b32_e32 v19, v12
473; GCN-IR-NEXT:    v_subb_u32_e64 v17, s[4:5], v17, v20, s[4:5]
474; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
475; GCN-IR-NEXT:    v_mov_b32_e32 v18, v11
476; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
477; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
478; GCN-IR-NEXT:  ; %bb.4: ; %Flow
479; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
480; GCN-IR-NEXT:  BB1_5: ; %Flow3
481; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
482; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[7:8], 1
483; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v3
484; GCN-IR-NEXT:    v_or_b32_e32 v0, v11, v2
485; GCN-IR-NEXT:  BB1_6: ; %Flow4
486; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
487; GCN-IR-NEXT:    v_xor_b32_e32 v2, v5, v4
488; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
489; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v6
490; GCN-IR-NEXT:    v_xor_b32_e32 v3, v12, v1
491; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
492; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
493; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
494  %result = sdiv i64 %x, %y
495  ret i64 %result
496}
497
498define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
499; GCN-LABEL: s_test_sdiv24_64:
500; GCN:       ; %bb.0:
501; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
502; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
503; GCN-NEXT:    s_mov_b32 s3, 0xf000
504; GCN-NEXT:    s_mov_b32 s2, -1
505; GCN-NEXT:    s_waitcnt lgkmcnt(0)
506; GCN-NEXT:    s_mov_b32 s0, s4
507; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
508; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
509; GCN-NEXT:    s_mov_b32 s1, s5
510; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
511; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
512; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
513; GCN-NEXT:    s_xor_b32 s4, s4, s8
514; GCN-NEXT:    s_ashr_i32 s4, s4, 30
515; GCN-NEXT:    s_or_b32 s4, s4, 1
516; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
517; GCN-NEXT:    v_trunc_f32_e32 v2, v2
518; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
519; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
520; GCN-NEXT:    v_mov_b32_e32 v3, s4
521; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
522; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
523; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
524; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
525; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
526; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
527; GCN-NEXT:    s_endpgm
528;
529; GCN-IR-LABEL: s_test_sdiv24_64:
530; GCN-IR:       ; %bb.0:
531; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
532; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
533; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
534; GCN-IR-NEXT:    s_mov_b32 s2, -1
535; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
536; GCN-IR-NEXT:    s_mov_b32 s0, s4
537; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
538; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
539; GCN-IR-NEXT:    s_mov_b32 s1, s5
540; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
541; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
542; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
543; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
544; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
545; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
546; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
547; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
548; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
549; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
550; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
551; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
552; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
553; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
554; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
555; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
556; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
557; GCN-IR-NEXT:    s_endpgm
558  %1 = ashr i64 %x, 40
559  %2 = ashr i64 %y, 40
560  %result = sdiv i64 %1, %2
561  store i64 %result, i64 addrspace(1)* %out
562  ret void
563}
564
565define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
566; GCN-LABEL: v_test_sdiv24_64:
567; GCN:       ; %bb.0:
568; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
569; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
570; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
571; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
572; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
573; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
574; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
575; GCN-NEXT:    v_trunc_f32_e32 v2, v2
576; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
577; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
578; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
579; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
580; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
581; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
582; GCN-NEXT:    s_setpc_b64 s[30:31]
583;
584; GCN-IR-LABEL: v_test_sdiv24_64:
585; GCN-IR:       ; %bb.0:
586; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
587; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
588; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, v0
589; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
590; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v1
591; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
592; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
593; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
594; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
595; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
596; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
597; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
598; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
599; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
600; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
601  %1 = lshr i64 %x, 40
602  %2 = lshr i64 %y, 40
603  %result = sdiv i64 %1, %2
604  ret i64 %result
605}
606
607define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
608; GCN-LABEL: s_test_sdiv32_64:
609; GCN:       ; %bb.0:
610; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
611; GCN-NEXT:    s_waitcnt lgkmcnt(0)
612; GCN-NEXT:    s_load_dword s6, s[0:1], 0xe
613; GCN-NEXT:    s_mov_b32 s3, 0xf000
614; GCN-NEXT:    s_mov_b32 s2, -1
615; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
616; GCN-NEXT:    s_waitcnt lgkmcnt(0)
617; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
618; GCN-NEXT:    s_mov_b32 s0, s4
619; GCN-NEXT:    s_xor_b32 s4, s7, s6
620; GCN-NEXT:    s_ashr_i32 s4, s4, 30
621; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
622; GCN-NEXT:    s_or_b32 s4, s4, 1
623; GCN-NEXT:    v_mov_b32_e32 v3, s4
624; GCN-NEXT:    s_mov_b32 s1, s5
625; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
626; GCN-NEXT:    v_trunc_f32_e32 v2, v2
627; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
628; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
629; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
630; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
631; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
632; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
633; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
634; GCN-NEXT:    s_endpgm
635;
636; GCN-IR-LABEL: s_test_sdiv32_64:
637; GCN-IR:       ; %bb.0:
638; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
639; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
640; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xe
641; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
642; GCN-IR-NEXT:    s_mov_b32 s2, -1
643; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
644; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
645; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
646; GCN-IR-NEXT:    s_mov_b32 s0, s4
647; GCN-IR-NEXT:    s_xor_b32 s4, s7, s6
648; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
649; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
650; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
651; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
652; GCN-IR-NEXT:    s_mov_b32 s1, s5
653; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
654; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
655; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
656; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
657; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
658; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
659; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
660; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
661; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
662; GCN-IR-NEXT:    s_endpgm
663  %1 = ashr i64 %x, 32
664  %2 = ashr i64 %y, 32
665  %result = sdiv i64 %1, %2
666  store i64 %result, i64 addrspace(1)* %out
667  ret void
668}
669
670define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
671; GCN-LABEL: s_test_sdiv31_64:
672; GCN:       ; %bb.0:
673; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
674; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
675; GCN-NEXT:    s_mov_b32 s3, 0xf000
676; GCN-NEXT:    s_mov_b32 s2, -1
677; GCN-NEXT:    s_waitcnt lgkmcnt(0)
678; GCN-NEXT:    s_mov_b32 s0, s4
679; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
680; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
681; GCN-NEXT:    s_mov_b32 s1, s5
682; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
683; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
684; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
685; GCN-NEXT:    s_xor_b32 s4, s4, s8
686; GCN-NEXT:    s_ashr_i32 s4, s4, 30
687; GCN-NEXT:    s_or_b32 s4, s4, 1
688; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
689; GCN-NEXT:    v_trunc_f32_e32 v2, v2
690; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
691; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
692; GCN-NEXT:    v_mov_b32_e32 v3, s4
693; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
694; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
695; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
696; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
697; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
698; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
699; GCN-NEXT:    s_endpgm
700;
701; GCN-IR-LABEL: s_test_sdiv31_64:
702; GCN-IR:       ; %bb.0:
703; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
704; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
705; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
706; GCN-IR-NEXT:    s_mov_b32 s2, -1
707; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
708; GCN-IR-NEXT:    s_mov_b32 s0, s4
709; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
710; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
711; GCN-IR-NEXT:    s_mov_b32 s1, s5
712; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
713; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
714; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
715; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
716; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
717; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
718; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
719; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
720; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
721; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
722; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
723; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
724; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
725; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
726; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
727; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
728; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
729; GCN-IR-NEXT:    s_endpgm
730  %1 = ashr i64 %x, 33
731  %2 = ashr i64 %y, 33
732  %result = sdiv i64 %1, %2
733  store i64 %result, i64 addrspace(1)* %out
734  ret void
735}
736
737define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
738; GCN-LABEL: s_test_sdiv23_64:
739; GCN:       ; %bb.0:
740; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
741; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
742; GCN-NEXT:    s_mov_b32 s3, 0xf000
743; GCN-NEXT:    s_mov_b32 s2, -1
744; GCN-NEXT:    s_waitcnt lgkmcnt(0)
745; GCN-NEXT:    s_mov_b32 s0, s4
746; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
747; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
748; GCN-NEXT:    s_mov_b32 s1, s5
749; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
750; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
751; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
752; GCN-NEXT:    s_xor_b32 s4, s4, s8
753; GCN-NEXT:    s_ashr_i32 s4, s4, 30
754; GCN-NEXT:    s_or_b32 s4, s4, 1
755; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
756; GCN-NEXT:    v_trunc_f32_e32 v2, v2
757; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
758; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
759; GCN-NEXT:    v_mov_b32_e32 v3, s4
760; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
761; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
762; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
763; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
764; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
765; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
766; GCN-NEXT:    s_endpgm
767;
768; GCN-IR-LABEL: s_test_sdiv23_64:
769; GCN-IR:       ; %bb.0:
770; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
771; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
772; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
773; GCN-IR-NEXT:    s_mov_b32 s2, -1
774; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
775; GCN-IR-NEXT:    s_mov_b32 s0, s4
776; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
777; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
778; GCN-IR-NEXT:    s_mov_b32 s1, s5
779; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
780; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
781; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
782; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
783; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
784; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
785; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
786; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
787; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
788; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
789; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
790; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
791; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
792; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
793; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
794; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
795; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
796; GCN-IR-NEXT:    s_endpgm
797  %1 = ashr i64 %x, 41
798  %2 = ashr i64 %y, 41
799  %result = sdiv i64 %1, %2
800  store i64 %result, i64 addrspace(1)* %out
801  ret void
802}
803
804define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
805; GCN-LABEL: s_test_sdiv25_64:
806; GCN:       ; %bb.0:
807; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
808; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
809; GCN-NEXT:    s_mov_b32 s3, 0xf000
810; GCN-NEXT:    s_mov_b32 s2, -1
811; GCN-NEXT:    s_waitcnt lgkmcnt(0)
812; GCN-NEXT:    s_mov_b32 s0, s4
813; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
814; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
815; GCN-NEXT:    s_mov_b32 s1, s5
816; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
817; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
818; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
819; GCN-NEXT:    s_xor_b32 s4, s4, s8
820; GCN-NEXT:    s_ashr_i32 s4, s4, 30
821; GCN-NEXT:    s_or_b32 s4, s4, 1
822; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
823; GCN-NEXT:    v_trunc_f32_e32 v2, v2
824; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
825; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
826; GCN-NEXT:    v_mov_b32_e32 v3, s4
827; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
828; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
829; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
830; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
831; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
832; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
833; GCN-NEXT:    s_endpgm
834;
835; GCN-IR-LABEL: s_test_sdiv25_64:
836; GCN-IR:       ; %bb.0:
837; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
838; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
839; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
840; GCN-IR-NEXT:    s_mov_b32 s2, -1
841; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
842; GCN-IR-NEXT:    s_mov_b32 s0, s4
843; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
844; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
845; GCN-IR-NEXT:    s_mov_b32 s1, s5
846; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
847; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
848; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
849; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
850; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
851; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
852; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
853; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
854; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
855; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
856; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
857; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
858; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
859; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
860; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
861; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
862; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
863; GCN-IR-NEXT:    s_endpgm
864  %1 = ashr i64 %x, 39
865  %2 = ashr i64 %y, 39
866  %result = sdiv i64 %1, %2
867  store i64 %result, i64 addrspace(1)* %out
868  ret void
869}
870
871define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
872; GCN-LABEL: s_test_sdiv24_v2i64:
873; GCN:       ; %bb.0:
874; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
875; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
876; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
877; GCN-NEXT:    s_mov_b32 s7, 0xf000
878; GCN-NEXT:    s_mov_b32 s6, -1
879; GCN-NEXT:    s_waitcnt lgkmcnt(0)
880; GCN-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
881; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
882; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
883; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s8
884; GCN-NEXT:    s_xor_b32 s0, s8, s0
885; GCN-NEXT:    s_ashr_i32 s0, s0, 30
886; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
887; GCN-NEXT:    s_or_b32 s0, s0, 1
888; GCN-NEXT:    v_mov_b32_e32 v3, s0
889; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
890; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
891; GCN-NEXT:    v_trunc_f32_e32 v2, v2
892; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
893; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
894; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
895; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
896; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
897; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
898; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s2
899; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s10
900; GCN-NEXT:    s_xor_b32 s0, s10, s2
901; GCN-NEXT:    s_ashr_i32 s0, s0, 30
902; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
903; GCN-NEXT:    s_or_b32 s0, s0, 1
904; GCN-NEXT:    v_mov_b32_e32 v5, s0
905; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
906; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
907; GCN-NEXT:    v_trunc_f32_e32 v4, v4
908; GCN-NEXT:    v_mad_f32 v3, -v4, v2, v3
909; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
910; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
911; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
912; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
913; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
914; GCN-NEXT:    v_bfe_i32 v2, v2, 0, 24
915; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
916; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
917; GCN-NEXT:    s_endpgm
918;
919; GCN-IR-LABEL: s_test_sdiv24_v2i64:
920; GCN-IR:       ; %bb.0:
921; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
922; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
923; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
924; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
925; GCN-IR-NEXT:    s_mov_b32 s6, -1
926; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
927; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
928; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
929; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
930; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s8
931; GCN-IR-NEXT:    s_xor_b32 s0, s8, s0
932; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
933; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
934; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
935; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
936; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
937; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
938; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
939; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
940; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
941; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
942; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
943; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
944; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
945; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v2, s2
946; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, s10
947; GCN-IR-NEXT:    s_xor_b32 s0, s10, s2
948; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
949; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v2
950; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
951; GCN-IR-NEXT:    v_mov_b32_e32 v5, s0
952; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
953; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
954; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
955; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v2, v3
956; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
957; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
958; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
959; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
960; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
961; GCN-IR-NEXT:    v_bfe_i32 v2, v2, 0, 24
962; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
963; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
964; GCN-IR-NEXT:    s_endpgm
965  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
966  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
967  %result = sdiv <2 x i64> %1, %2
968  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
969  ret void
970}
971
972define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
973; GCN-LABEL: s_test_sdiv24_48:
974; GCN:       ; %bb.0:
975; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
976; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
977; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
978; GCN-NEXT:    s_load_dword s8, s[0:1], 0xd
979; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
980; GCN-NEXT:    s_mov_b32 s7, 0xf000
981; GCN-NEXT:    s_waitcnt lgkmcnt(0)
982; GCN-NEXT:    v_mov_b32_e32 v2, s2
983; GCN-NEXT:    s_sext_i32_i16 s1, s3
984; GCN-NEXT:    v_mov_b32_e32 v0, s8
985; GCN-NEXT:    s_sext_i32_i16 s0, s0
986; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
987; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
988; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
989; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
990; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
991; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
992; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
993; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
994; GCN-NEXT:    s_mov_b32 s6, -1
995; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
996; GCN-NEXT:    v_trunc_f32_e32 v2, v2
997; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
998; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
999; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1000; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1001; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1002; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1003; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1004; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1005; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1006; GCN-NEXT:    s_endpgm
1007;
1008; GCN-IR-LABEL: s_test_sdiv24_48:
1009; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1010; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1011; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1012; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1013; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
1014; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
1015; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1016; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1017; GCN-IR-NEXT:    s_sext_i32_i16 s7, s0
1018; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[2:3], 24
1019; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1020; GCN-IR-NEXT:    s_mov_b32 s3, s2
1021; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[6:7], 24
1022; GCN-IR-NEXT:    s_ashr_i32 s6, s7, 31
1023; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
1024; GCN-IR-NEXT:    s_sub_u32 s10, s0, s2
1025; GCN-IR-NEXT:    s_mov_b32 s7, s6
1026; GCN-IR-NEXT:    s_subb_u32 s11, s1, s2
1027; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[6:7], s[8:9]
1028; GCN-IR-NEXT:    s_sub_u32 s8, s0, s6
1029; GCN-IR-NEXT:    s_flbit_i32_b32 s14, s8
1030; GCN-IR-NEXT:    s_subb_u32 s9, s1, s6
1031; GCN-IR-NEXT:    s_add_i32 s14, s14, 32
1032; GCN-IR-NEXT:    s_flbit_i32_b32 s15, s9
1033; GCN-IR-NEXT:    v_mov_b32_e32 v1, s14
1034; GCN-IR-NEXT:    s_flbit_i32_b32 s14, s10
1035; GCN-IR-NEXT:    v_mov_b32_e32 v0, s15
1036; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s9, 0
1037; GCN-IR-NEXT:    s_add_i32 s14, s14, 32
1038; GCN-IR-NEXT:    s_flbit_i32_b32 s15, s11
1039; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1040; GCN-IR-NEXT:    v_mov_b32_e32 v0, s15
1041; GCN-IR-NEXT:    v_mov_b32_e32 v1, s14
1042; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s11, 0
1043; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1044; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
1045; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[14:15], 0, 0, vcc
1046; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[8:9], 0
1047; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
1048; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1049; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], s[12:13]
1050; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
1051; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[0:1]
1052; GCN-IR-NEXT:    s_xor_b64 s[12:13], s[0:1], -1
1053; GCN-IR-NEXT:    s_and_b64 s[12:13], s[12:13], vcc
1054; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1055; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1056; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1057; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1058; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
1059; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
1060; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1061; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[10:11], v0
1062; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
1063; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1064; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1065; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
1066; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[10:11], v4
1067; GCN-IR-NEXT:    s_add_u32 s10, s8, -1
1068; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
1069; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1070; GCN-IR-NEXT:    s_addc_u32 s11, s9, -1
1071; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
1072; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1073; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1074; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1075; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1076; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1077; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1078; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1079; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1080; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1081; GCN-IR-NEXT:    v_mov_b32_e32 v2, s11
1082; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s10, v6
1083; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
1084; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1085; GCN-IR-NEXT:    v_and_b32_e32 v10, s8, v8
1086; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1087; GCN-IR-NEXT:    v_and_b32_e32 v11, s9, v8
1088; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1089; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1090; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1091; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1092; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1093; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1094; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1095; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1096; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1097; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1098; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1099; GCN-IR-NEXT:    s_cbranch_vccz BB9_3
1100; GCN-IR-NEXT:    s_branch BB9_6
1101; GCN-IR-NEXT:  BB9_4:
1102; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
1103; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[0:1]
1104; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1105; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]
1106; GCN-IR-NEXT:    s_branch BB9_7
1107; GCN-IR-NEXT:  BB9_5:
1108; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1109; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1110; GCN-IR-NEXT:  BB9_6: ; %Flow3
1111; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1112; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1113; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1114; GCN-IR-NEXT:  BB9_7: ; %udiv-end
1115; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[6:7], s[2:3]
1116; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1117; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1118; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1119; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1120; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1121; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1122; GCN-IR-NEXT:    s_mov_b32 s6, -1
1123; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1124; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1125; GCN-IR-NEXT:    s_endpgm
1126  %1 = ashr i48 %x, 24
1127  %2 = ashr i48 %y, 24
1128  %result = sdiv i48 %1, %2
1129  store i48 %result, i48 addrspace(1)* %out
1130  ret void
1131}
1132
1133define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1134; GCN-LABEL: s_test_sdiv_k_num_i64:
1135; GCN:       ; %bb.0:
1136; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1137; GCN-NEXT:    v_mov_b32_e32 v2, 0
1138; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1139; GCN-NEXT:    s_ashr_i32 s2, s7, 31
1140; GCN-NEXT:    s_add_u32 s0, s6, s2
1141; GCN-NEXT:    s_addc_u32 s1, s7, s2
1142; GCN-NEXT:    s_mov_b32 s3, s2
1143; GCN-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
1144; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1145; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1146; GCN-NEXT:    s_sub_u32 s3, 0, s8
1147; GCN-NEXT:    s_subb_u32 s10, 0, s9
1148; GCN-NEXT:    s_mov_b32 s7, 0xf000
1149; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1150; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1151; GCN-NEXT:    v_mov_b32_e32 v1, 0
1152; GCN-NEXT:    s_mov_b32 s6, -1
1153; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1154; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1155; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1156; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1157; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1158; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1159; GCN-NEXT:    v_mul_hi_u32 v5, s3, v0
1160; GCN-NEXT:    v_mul_lo_u32 v4, s3, v3
1161; GCN-NEXT:    v_mul_lo_u32 v7, s10, v0
1162; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
1163; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1164; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1165; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1166; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1167; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1168; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1169; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1170; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1171; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1172; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
1173; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1174; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
1175; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1176; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
1177; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1178; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
1179; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1180; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
1181; GCN-NEXT:    v_mul_lo_u32 v6, s3, v4
1182; GCN-NEXT:    v_mul_hi_u32 v7, s3, v0
1183; GCN-NEXT:    v_mul_lo_u32 v8, s10, v0
1184; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1185; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
1186; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
1187; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
1188; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
1189; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
1190; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
1191; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1192; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
1193; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1194; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
1195; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1196; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
1197; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
1198; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
1199; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1200; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
1201; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1202; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
1203; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1204; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1205; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1206; GCN-NEXT:    v_mul_hi_u32 v0, 24, v0
1207; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
1208; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1209; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1210; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v5, vcc
1211; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
1212; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1213; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
1214; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
1215; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
1216; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
1217; GCN-NEXT:    v_mov_b32_e32 v5, s9
1218; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1219; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
1220; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1221; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
1222; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
1223; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
1224; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v3
1225; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
1226; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
1227; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
1228; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v5
1229; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1230; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v4
1231; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
1232; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
1233; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
1234; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
1235; GCN-NEXT:    v_subb_u32_e32 v2, vcc, 0, v2, vcc
1236; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
1237; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
1238; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1239; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
1240; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1241; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
1242; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1243; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
1244; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
1245; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
1246; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
1247; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1248; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1249; GCN-NEXT:    v_xor_b32_e32 v0, s2, v0
1250; GCN-NEXT:    v_xor_b32_e32 v1, s2, v1
1251; GCN-NEXT:    v_mov_b32_e32 v2, s2
1252; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1253; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1254; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1255; GCN-NEXT:    s_endpgm
1256;
1257; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1258; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1259; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1260; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1261; GCN-IR-NEXT:    s_ashr_i32 s2, s7, 31
1262; GCN-IR-NEXT:    s_mov_b32 s3, s2
1263; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[6:7]
1264; GCN-IR-NEXT:    s_sub_u32 s6, s0, s2
1265; GCN-IR-NEXT:    s_subb_u32 s7, s1, s2
1266; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s6
1267; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
1268; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s7
1269; GCN-IR-NEXT:    v_mov_b32_e32 v0, s9
1270; GCN-IR-NEXT:    v_mov_b32_e32 v1, s8
1271; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
1272; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1273; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc5, v2
1274; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[8:9], 0, -1, vcc
1275; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
1276; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1277; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
1278; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[0:1]
1279; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[0:1], -1
1280; GCN-IR-NEXT:    s_and_b64 s[8:9], s[8:9], vcc
1281; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[8:9]
1282; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1283; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1284; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1285; GCN-IR-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
1286; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
1287; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1288; GCN-IR-NEXT:    v_lshl_b64 v[0:1], 24, v0
1289; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
1290; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1291; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1292; GCN-IR-NEXT:    s_add_u32 s8, s6, -1
1293; GCN-IR-NEXT:    v_lshr_b64 v[6:7], 24, v3
1294; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 58, v2
1295; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1296; GCN-IR-NEXT:    s_addc_u32 s9, s7, -1
1297; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[0:1], 0, 0, vcc
1298; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1299; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1300; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1301; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1302; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1303; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1304; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1305; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1306; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1307; GCN-IR-NEXT:    v_mov_b32_e32 v2, s9
1308; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s8, v6
1309; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
1310; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1311; GCN-IR-NEXT:    v_and_b32_e32 v10, s6, v8
1312; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1313; GCN-IR-NEXT:    v_and_b32_e32 v11, s7, v8
1314; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1315; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1316; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1317; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1318; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1319; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1320; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1321; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1322; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1323; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1324; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1325; GCN-IR-NEXT:    s_cbranch_vccz BB10_3
1326; GCN-IR-NEXT:    s_branch BB10_6
1327; GCN-IR-NEXT:  BB10_4:
1328; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1329; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[0:1]
1330; GCN-IR-NEXT:    s_branch BB10_7
1331; GCN-IR-NEXT:  BB10_5:
1332; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1333; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1334; GCN-IR-NEXT:  BB10_6: ; %Flow5
1335; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1336; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1337; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1338; GCN-IR-NEXT:  BB10_7: ; %udiv-end
1339; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1340; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1341; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1342; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1343; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1344; GCN-IR-NEXT:    s_mov_b32 s6, -1
1345; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1346; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1347; GCN-IR-NEXT:    s_endpgm
1348  %result = sdiv i64 24, %x
1349  store i64 %result, i64 addrspace(1)* %out
1350  ret void
1351}
1352
1353define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1354; GCN-LABEL: v_test_sdiv_k_num_i64:
1355; GCN:       ; %bb.0:
1356; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1357; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1358; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1359; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1360; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1361; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1362; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1363; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1364; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1365; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1366; GCN-NEXT:    v_mov_b32_e32 v13, 0
1367; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1368; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1369; GCN-NEXT:    v_mov_b32_e32 v12, 0
1370; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1371; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1372; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1373; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1374; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1375; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1376; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1377; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1378; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1379; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1380; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1381; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1382; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1383; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1384; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1385; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1386; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1387; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1388; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1389; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1390; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1391; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1392; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1393; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1394; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1395; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
1396; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1397; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
1398; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
1399; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
1400; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1401; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1402; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1403; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
1404; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
1405; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
1406; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
1407; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
1408; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
1409; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
1410; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
1411; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
1412; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
1413; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
1414; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
1415; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
1416; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1417; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1418; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
1419; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
1420; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1421; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
1422; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
1423; GCN-NEXT:    v_mul_hi_u32 v3, 24, v3
1424; GCN-NEXT:    v_mul_hi_u32 v6, 24, v4
1425; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
1426; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1427; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v13, v6, vcc
1428; GCN-NEXT:    v_add_i32_e32 v3, vcc, 0, v3
1429; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
1430; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
1431; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
1432; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1433; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
1434; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1435; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1436; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1437; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
1438; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 24, v6
1439; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
1440; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
1441; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
1442; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
1443; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
1444; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
1445; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1446; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
1447; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
1448; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
1449; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
1450; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
1451; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
1452; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
1453; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1454; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
1455; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
1456; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
1457; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
1458; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1459; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
1460; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
1461; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1462; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
1463; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
1464; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1465; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1466; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1467; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1468; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1469; GCN-NEXT:    s_setpc_b64 s[30:31]
1470;
1471; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1472; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1473; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1474; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1475; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1476; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1477; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1478; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1479; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1480; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1481; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1482; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1483; GCN-IR-NEXT:    v_cndmask_b32_e32 v10, v5, v4, vcc
1484; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1485; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v10
1486; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1487; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1488; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1489; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1490; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1491; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1492; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, 24, 0, s[4:5]
1493; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1494; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1495; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1496; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1497; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1498; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1499; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1500; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1501; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1502; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5]
1503; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1504; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1505; GCN-IR-NEXT:    v_lshl_b64 v[4:5], 24, v4
1506; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1507; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1508; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1509; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1510; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1511; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1512; GCN-IR-NEXT:    v_lshr_b64 v[12:13], 24, v8
1513; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, -1, v0
1514; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, -1, v1, vcc
1515; GCN-IR-NEXT:    v_sub_i32_e32 v10, vcc, 58, v10
1516; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
1517; GCN-IR-NEXT:    v_subb_u32_e32 v11, vcc, 0, v11, vcc
1518; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
1519; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1520; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1521; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
1522; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1523; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v6
1524; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1525; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v8, v12
1526; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v9, v13, vcc
1527; GCN-IR-NEXT:    v_or_b32_e32 v4, v14, v4
1528; GCN-IR-NEXT:    v_ashrrev_i32_e32 v14, 31, v6
1529; GCN-IR-NEXT:    v_and_b32_e32 v17, v14, v0
1530; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v14
1531; GCN-IR-NEXT:    v_and_b32_e32 v16, v14, v1
1532; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v10
1533; GCN-IR-NEXT:    v_or_b32_e32 v5, v15, v5
1534; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
1535; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11]
1536; GCN-IR-NEXT:    v_mov_b32_e32 v10, v14
1537; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1538; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v17
1539; GCN-IR-NEXT:    v_mov_b32_e32 v11, v15
1540; GCN-IR-NEXT:    v_mov_b32_e32 v15, v7
1541; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5]
1542; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1543; GCN-IR-NEXT:    v_mov_b32_e32 v14, v6
1544; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1545; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1546; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1547; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1548; GCN-IR-NEXT:  BB11_5: ; %Flow3
1549; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1550; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1551; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1552; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1553; GCN-IR-NEXT:  BB11_6: ; %Flow4
1554; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1555; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1556; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1557; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1558; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1559; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1560  %result = sdiv i64 24, %x
1561  ret i64 %result
1562}
1563
1564define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1565; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1566; GCN:       ; %bb.0:
1567; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1568; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1569; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1570; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1571; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1572; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1573; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1574; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1575; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1576; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1577; GCN-NEXT:    v_mov_b32_e32 v13, 0
1578; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1579; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1580; GCN-NEXT:    v_mov_b32_e32 v12, 0
1581; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1582; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1583; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1584; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1585; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1586; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1587; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1588; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1589; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1590; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1591; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1592; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1593; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1594; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1595; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1596; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1597; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1598; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1599; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1600; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1601; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1602; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1603; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1604; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1605; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1606; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
1607; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1608; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
1609; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
1610; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
1611; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1612; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1613; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1614; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
1615; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
1616; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
1617; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
1618; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
1619; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
1620; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
1621; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
1622; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
1623; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
1624; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
1625; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
1626; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
1627; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1628; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1629; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
1630; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
1631; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1632; GCN-NEXT:    s_mov_b32 s4, 0x8000
1633; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
1634; GCN-NEXT:    v_mul_hi_u32 v3, s4, v3
1635; GCN-NEXT:    v_mul_hi_u32 v5, s4, v4
1636; GCN-NEXT:    v_lshlrev_b32_e32 v6, 15, v4
1637; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
1638; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1639; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v13, v5, vcc
1640; GCN-NEXT:    v_add_i32_e32 v3, vcc, 0, v3
1641; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
1642; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
1643; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
1644; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1645; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
1646; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1647; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1648; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1649; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
1650; GCN-NEXT:    v_sub_i32_e32 v6, vcc, s4, v6
1651; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
1652; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
1653; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
1654; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
1655; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
1656; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
1657; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1658; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
1659; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
1660; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
1661; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
1662; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
1663; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
1664; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
1665; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1666; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
1667; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
1668; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
1669; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
1670; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1671; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
1672; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
1673; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1674; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
1675; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
1676; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1677; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1678; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1679; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1680; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1681; GCN-NEXT:    s_setpc_b64 s[30:31]
1682;
1683; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1684; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1685; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1686; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1687; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1688; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1689; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1690; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1691; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1692; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1693; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1694; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1695; GCN-IR-NEXT:    v_cndmask_b32_e32 v10, v5, v4, vcc
1696; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1697; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v10
1698; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1699; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1700; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1701; GCN-IR-NEXT:    s_mov_b32 s8, 0x8000
1702; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1703; GCN-IR-NEXT:    v_mov_b32_e32 v6, s8
1704; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1705; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1706; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[4:5]
1707; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1708; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1709; GCN-IR-NEXT:    s_mov_b32 s9, 0
1710; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1711; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1712; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1713; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1714; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1715; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1716; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1717; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5]
1718; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1719; GCN-IR-NEXT:    v_lshl_b64 v[4:5], s[8:9], v4
1720; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1721; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1722; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1723; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1724; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1725; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1726; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1727; GCN-IR-NEXT:    s_mov_b32 s5, 0
1728; GCN-IR-NEXT:    s_mov_b32 s4, 0x8000
1729; GCN-IR-NEXT:    v_lshr_b64 v[12:13], s[4:5], v8
1730; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, -1, v0
1731; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, -1, v1, vcc
1732; GCN-IR-NEXT:    v_sub_i32_e32 v10, vcc, 47, v10
1733; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
1734; GCN-IR-NEXT:    v_subb_u32_e32 v11, vcc, 0, v11, vcc
1735; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
1736; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1737; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1738; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
1739; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1740; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v6
1741; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1742; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v8, v12
1743; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v9, v13, vcc
1744; GCN-IR-NEXT:    v_or_b32_e32 v4, v14, v4
1745; GCN-IR-NEXT:    v_ashrrev_i32_e32 v14, 31, v6
1746; GCN-IR-NEXT:    v_and_b32_e32 v17, v14, v0
1747; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v14
1748; GCN-IR-NEXT:    v_and_b32_e32 v16, v14, v1
1749; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v10
1750; GCN-IR-NEXT:    v_or_b32_e32 v5, v15, v5
1751; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
1752; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11]
1753; GCN-IR-NEXT:    v_mov_b32_e32 v10, v14
1754; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1755; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v17
1756; GCN-IR-NEXT:    v_mov_b32_e32 v11, v15
1757; GCN-IR-NEXT:    v_mov_b32_e32 v15, v7
1758; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5]
1759; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1760; GCN-IR-NEXT:    v_mov_b32_e32 v14, v6
1761; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1762; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1763; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1764; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1765; GCN-IR-NEXT:  BB12_5: ; %Flow3
1766; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1767; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1768; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1769; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1770; GCN-IR-NEXT:  BB12_6: ; %Flow4
1771; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1772; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1773; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1774; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1775; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1776; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1777  %result = sdiv i64 32768, %x
1778  ret i64 %result
1779}
1780
1781define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1782; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1783; GCN:       ; %bb.0:
1784; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1785; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1786; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1787; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1788; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1789; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1790; GCN-NEXT:    s_setpc_b64 s[30:31]
1791;
1792; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1793; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1794; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1795; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1796; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1797; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v2
1798; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v7
1799; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1800; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v1, v2, vcc
1801; GCN-IR-NEXT:    v_add_i32_e64 v0, s[4:5], 32, v0
1802; GCN-IR-NEXT:    v_ffbh_u32_e32 v1, v8
1803; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
1804; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v1, v0, s[4:5]
1805; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 48, v0
1806; GCN-IR-NEXT:    v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1807; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1808; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1809; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1810; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1811; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1812; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1813; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1814; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1815; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1816; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1817; GCN-IR-NEXT:    s_cbranch_execz BB13_6
1818; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1819; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
1820; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
1821; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4]
1822; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v3
1823; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1824; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[7:8], v3
1825; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1826; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1827; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1828; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1829; GCN-IR-NEXT:    s_cbranch_execz BB13_5
1830; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1831; GCN-IR-NEXT:    v_lshr_b64 v[9:10], v[7:8], v9
1832; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1833; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1834; GCN-IR-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1835; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1836; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1837; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
1838; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1839; GCN-IR-NEXT:    v_lshl_b64 v[9:10], v[9:10], 1
1840; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v4
1841; GCN-IR-NEXT:    v_or_b32_e32 v0, v9, v0
1842; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1843; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, s12, v0
1844; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v10, vcc
1845; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1846; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
1847; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
1848; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1849; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
1850; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
1851; GCN-IR-NEXT:    v_and_b32_e32 v5, 1, v9
1852; GCN-IR-NEXT:    v_and_b32_e32 v9, 0x8000, v9
1853; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1854; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1855; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1856; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1857; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1858; GCN-IR-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v9
1859; GCN-IR-NEXT:    v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5]
1860; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1861; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1862; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1863; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
1864; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1865; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1866; GCN-IR-NEXT:  BB13_5: ; %Flow3
1867; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1868; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1869; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1870; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1871; GCN-IR-NEXT:  BB13_6: ; %Flow4
1872; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1873; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v2
1874; GCN-IR-NEXT:    v_xor_b32_e32 v3, v6, v1
1875; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1876; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
1877; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1878  %result = sdiv i64 %x, 32768
1879  ret i64 %result
1880}
1881
1882define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1883; GCN-LABEL: s_test_sdiv24_k_num_i64:
1884; GCN:       ; %bb.0:
1885; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1886; GCN-NEXT:    s_mov_b32 s7, 0xf000
1887; GCN-NEXT:    s_mov_b32 s6, -1
1888; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1889; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1890; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1891; GCN-NEXT:    s_mov_b32 s3, 0x41c00000
1892; GCN-NEXT:    s_mov_b32 s4, s0
1893; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1894; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1895; GCN-NEXT:    s_or_b32 s0, s0, 1
1896; GCN-NEXT:    v_mov_b32_e32 v3, s0
1897; GCN-NEXT:    s_mov_b32 s5, s1
1898; GCN-NEXT:    v_mul_f32_e32 v1, s3, v1
1899; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1900; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s3
1901; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1902; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1903; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1904; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1905; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1906; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1907; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1908; GCN-NEXT:    s_endpgm
1909;
1910; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1911; GCN-IR:       ; %bb.0:
1912; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1913; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1914; GCN-IR-NEXT:    s_mov_b32 s6, -1
1915; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1916; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1917; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1918; GCN-IR-NEXT:    s_mov_b32 s3, 0x41c00000
1919; GCN-IR-NEXT:    s_mov_b32 s4, s0
1920; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1921; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1922; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1923; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
1924; GCN-IR-NEXT:    s_mov_b32 s5, s1
1925; GCN-IR-NEXT:    v_mul_f32_e32 v1, s3, v1
1926; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1927; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s3
1928; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1929; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1930; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1931; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1932; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1933; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1934; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1935; GCN-IR-NEXT:    s_endpgm
1936  %x.shr = ashr i64 %x, 40
1937  %result = sdiv i64 24, %x.shr
1938  store i64 %result, i64 addrspace(1)* %out
1939  ret void
1940}
1941
1942define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1943; GCN-LABEL: s_test_sdiv24_k_den_i64:
1944; GCN:       ; %bb.0:
1945; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1946; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1947; GCN-NEXT:    s_mov_b32 s3, 0xf000
1948; GCN-NEXT:    s_mov_b32 s2, -1
1949; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1950; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1951; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
1952; GCN-NEXT:    s_mov_b32 s0, s4
1953; GCN-NEXT:    s_ashr_i32 s4, s6, 30
1954; GCN-NEXT:    s_or_b32 s4, s4, 1
1955; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1956; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1957; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
1958; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1959; GCN-NEXT:    v_mov_b32_e32 v2, s4
1960; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1961; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1962; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1963; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1964; GCN-NEXT:    s_mov_b32 s1, s5
1965; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1966; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1967; GCN-NEXT:    s_endpgm
1968;
1969; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1970; GCN-IR:       ; %bb.0:
1971; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1972; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
1973; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1974; GCN-IR-NEXT:    s_mov_b32 s2, -1
1975; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1976; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1977; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
1978; GCN-IR-NEXT:    s_mov_b32 s0, s4
1979; GCN-IR-NEXT:    s_ashr_i32 s4, s6, 30
1980; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
1981; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1982; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1983; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
1984; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1985; GCN-IR-NEXT:    v_mov_b32_e32 v2, s4
1986; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1987; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1988; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1989; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1990; GCN-IR-NEXT:    s_mov_b32 s1, s5
1991; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1992; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1993; GCN-IR-NEXT:    s_endpgm
1994  %x.shr = ashr i64 %x, 40
1995  %result = sdiv i64 %x.shr, 23423
1996  store i64 %result, i64 addrspace(1)* %out
1997  ret void
1998}
1999
2000define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
2001; GCN-LABEL: v_test_sdiv24_k_num_i64:
2002; GCN:       ; %bb.0:
2003; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2004; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2005; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2006; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2007; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2008; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
2009; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2010; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2011; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2012; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
2013; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2014; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2015; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2016; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2017; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2018; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2019; GCN-NEXT:    s_setpc_b64 s[30:31]
2020;
2021; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
2022; GCN-IR:       ; %bb.0:
2023; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2024; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2025; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2026; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2027; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2028; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2029; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2030; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2031; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2032; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2033; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2034; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2035; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2036; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2037; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2038; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2039; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2040  %x.shr = ashr i64 %x, 40
2041  %result = sdiv i64 24, %x.shr
2042  ret i64 %result
2043}
2044
2045define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
2046; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
2047; GCN:       ; %bb.0:
2048; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2049; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2050; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2051; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2052; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2053; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
2054; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2055; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2056; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2057; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
2058; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2059; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2060; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2061; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2062; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2063; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2064; GCN-NEXT:    s_setpc_b64 s[30:31]
2065;
2066; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
2067; GCN-IR:       ; %bb.0:
2068; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2069; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2070; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2071; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2072; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2073; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2074; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2075; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2076; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2077; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2078; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2079; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2080; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2081; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2082; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2083; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2084; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2085  %x.shr = ashr i64 %x, 40
2086  %result = sdiv i64 32768, %x.shr
2087  ret i64 %result
2088}
2089
2090define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
2091; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
2092; GCN:       ; %bb.0:
2093; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2094; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2095; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2096; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2097; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2098; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
2099; GCN-NEXT:    s_setpc_b64 s[30:31]
2100;
2101; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
2102; GCN-IR:       ; %bb.0:
2103; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2104; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2105; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2106; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2107; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2108; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2109; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
2110; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2111; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
2112; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2113; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2114; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2115; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2116; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2117; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2118; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2119  %x.shr = ashr i64 %x, 40
2120  %result = sdiv i64 %x.shr, 32768
2121  ret i64 %result
2122}
2123