1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_sdiv:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    s_mov_b32 s7, 0xf000
10; GCN-NEXT:    s_mov_b32 s6, -1
11; GCN-NEXT:    s_waitcnt lgkmcnt(0)
12; GCN-NEXT:    s_ashr_i32 s8, s3, 31
13; GCN-NEXT:    s_add_u32 s2, s2, s8
14; GCN-NEXT:    s_mov_b32 s9, s8
15; GCN-NEXT:    s_addc_u32 s3, s3, s8
16; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
17; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s10
18; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s11
19; GCN-NEXT:    s_sub_u32 s4, 0, s10
20; GCN-NEXT:    s_subb_u32 s5, 0, s11
21; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
22; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
23; GCN-NEXT:    v_rcp_f32_e32 v0, v0
24; GCN-NEXT:    v_mov_b32_e32 v1, 0
25; GCN-NEXT:    s_waitcnt lgkmcnt(0)
26; GCN-NEXT:    s_ashr_i32 s12, s3, 31
27; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
28; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
29; GCN-NEXT:    v_trunc_f32_e32 v2, v2
30; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
31; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
32; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
33; GCN-NEXT:    s_add_u32 s2, s2, s12
34; GCN-NEXT:    s_mov_b32 s13, s12
35; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
36; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
37; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
38; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
39; GCN-NEXT:    s_addc_u32 s3, s3, s12
40; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
41; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
42; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
43; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
44; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
45; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
46; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
48; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
49; GCN-NEXT:    v_mul_hi_u32 v8, v2, v3
50; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
51; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
52; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
53; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
54; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
55; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
56; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
57; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
58; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
59; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
60; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
61; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
62; GCN-NEXT:    s_mov_b32 s5, s1
63; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
64; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
65; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
66; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
67; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
68; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
69; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
70; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
71; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
72; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
73; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
74; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
75; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
76; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
77; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
78; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
79; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
80; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
81; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
82; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
83; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
84; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
85; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
86; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
87; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
88; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
89; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
90; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
91; GCN-NEXT:    s_mov_b32 s4, s0
92; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
93; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
94; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
95; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
96; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
97; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
98; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
99; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
100; GCN-NEXT:    v_mov_b32_e32 v5, s11
101; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
102; GCN-NEXT:    v_mul_lo_u32 v3, s10, v0
103; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
104; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
105; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
106; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
107; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
108; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
109; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
110; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
111; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
113; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
114; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
115; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
116; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
117; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
118; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
119; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
120; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
121; GCN-NEXT:    v_mov_b32_e32 v6, s3
122; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
123; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
124; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
125; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
126; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
127; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
128; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
129; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
130; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
131; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
132; GCN-NEXT:    s_xor_b64 s[0:1], s[12:13], s[8:9]
133; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
134; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
135; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
136; GCN-NEXT:    v_mov_b32_e32 v2, s1
137; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
138; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
139; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
140; GCN-NEXT:    s_endpgm
141;
142; GCN-IR-LABEL: s_test_sdiv:
143; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
144; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
145; GCN-IR-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
146; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
147; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
148; GCN-IR-NEXT:    s_mov_b32 s1, s0
149; GCN-IR-NEXT:    s_ashr_i32 s2, s9, 31
150; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[0:1], s[6:7]
151; GCN-IR-NEXT:    s_mov_b32 s3, s2
152; GCN-IR-NEXT:    s_sub_u32 s10, s6, s0
153; GCN-IR-NEXT:    s_subb_u32 s11, s7, s0
154; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[8:9]
155; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
156; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
157; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
158; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
159; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
160; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
161; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
162; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
163; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
164; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
165; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
166; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
167; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
168; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
169; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
170; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
171; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
172; GCN-IR-NEXT:    s_mov_b32 s15, 0
173; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
174; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
175; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
176; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
177; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
178; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
179; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
180; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
181; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
182; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
183; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
184; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
185; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
186; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
187; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
188; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
189; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
190; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
191; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
192; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
193; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
194; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
195; GCN-IR-NEXT:    s_mov_b32 s17, s15
196; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
197; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
198; GCN-IR-NEXT:    s_mov_b32 s9, 0
199; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
200; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
201; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
202; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
203; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
204; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
205; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
206; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
207; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
208; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
209; GCN-IR-NEXT:    s_mov_b32 s15, s14
210; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
211; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
212; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
213; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
214; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
215; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
216; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
217; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
218; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
219; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
220; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
221; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
222; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
223; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
224; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
225; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
226; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
227; GCN-IR-NEXT:    s_branch .LBB0_6
228; GCN-IR-NEXT:  .LBB0_5:
229; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
230; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
231; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
232; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
233; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
234; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
235; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
236; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
237; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
238; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
239; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
240; GCN-IR-NEXT:    s_mov_b32 s6, -1
241; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
242; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
243; GCN-IR-NEXT:    s_endpgm
244  %result = sdiv i64 %x, %y
245  store i64 %result, i64 addrspace(1)* %out
246  ret void
247}
248
249define i64 @v_test_sdiv(i64 %x, i64 %y) {
250; GCN-LABEL: v_test_sdiv:
251; GCN:       ; %bb.0:
252; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
253; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
254; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
255; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
256; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
257; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
258; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
259; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
260; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
261; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
262; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
263; GCN-NEXT:    v_rcp_f32_e32 v5, v5
264; GCN-NEXT:    v_mov_b32_e32 v14, 0
265; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
266; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
267; GCN-NEXT:    v_trunc_f32_e32 v6, v6
268; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
269; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
270; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
271; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
272; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
273; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
274; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
275; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
276; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
277; GCN-NEXT:    v_mul_lo_u32 v11, v5, v9
278; GCN-NEXT:    v_mul_hi_u32 v12, v5, v10
279; GCN-NEXT:    v_mul_hi_u32 v13, v5, v9
280; GCN-NEXT:    v_mul_hi_u32 v15, v6, v9
281; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
282; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
283; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
284; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
285; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
286; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
287; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v10, vcc
288; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v14, vcc
289; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
290; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
291; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
292; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v10, vcc
293; GCN-NEXT:    v_mul_lo_u32 v9, v7, v6
294; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
295; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
296; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
297; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
298; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
299; GCN-NEXT:    v_mul_lo_u32 v11, v5, v8
300; GCN-NEXT:    v_mul_hi_u32 v12, v5, v7
301; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
302; GCN-NEXT:    v_mul_hi_u32 v10, v6, v7
303; GCN-NEXT:    v_mul_lo_u32 v7, v6, v7
304; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
305; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
306; GCN-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
307; GCN-NEXT:    v_mul_lo_u32 v8, v6, v8
308; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
309; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v10, vcc
310; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v14, vcc
311; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
312; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
313; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
314; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
315; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
316; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
317; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
318; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
319; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
320; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
321; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
322; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
323; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
324; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
325; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
326; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
327; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
328; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
329; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
330; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
331; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
332; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
333; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
334; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
335; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
336; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
337; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
338; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
339; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
340; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
341; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
342; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
343; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
344; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
345; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
346; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
347; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
348; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
349; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
350; GCN-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
351; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 2, v5
352; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
353; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
354; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
355; GCN-NEXT:    v_add_i32_e64 v12, s[4:5], 1, v5
356; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
357; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
358; GCN-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
359; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
360; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
361; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
362; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
363; GCN-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
364; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
365; GCN-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
366; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
367; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
368; GCN-NEXT:    v_xor_b32_e32 v2, v7, v4
369; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
370; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
371; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
372; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
373; GCN-NEXT:    s_setpc_b64 s[30:31]
374;
375; GCN-IR-LABEL: v_test_sdiv:
376; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
377; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
378; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
379; GCN-IR-NEXT:    v_xor_b32_e32 v0, v4, v0
380; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
381; GCN-IR-NEXT:    v_xor_b32_e32 v1, v4, v1
382; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v0, v4
383; GCN-IR-NEXT:    v_subb_u32_e32 v12, vcc, v1, v4, vcc
384; GCN-IR-NEXT:    v_xor_b32_e32 v1, v5, v2
385; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v3
386; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
387; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v0, v5, vcc
388; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
389; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[11:12]
390; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v2
391; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
392; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
393; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v3
394; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v7
395; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v11
396; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
397; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v12
398; GCN-IR-NEXT:    v_min_u32_e32 v13, v7, v8
399; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v13
400; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
401; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
402; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
403; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
404; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
405; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
406; GCN-IR-NEXT:    v_mov_b32_e32 v6, v4
407; GCN-IR-NEXT:    v_mov_b32_e32 v1, v5
408; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v12, 0, s[6:7]
409; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
410; GCN-IR-NEXT:    v_mov_b32_e32 v16, v17
411; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v11, 0, s[6:7]
412; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
413; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
414; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
415; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
416; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
417; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
418; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
419; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[11:12], v7
420; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
421; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
422; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
423; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
424; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
425; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
426; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
427; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v2
428; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v3, vcc
429; GCN-IR-NEXT:    v_not_b32_e32 v0, v0
430; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[11:12], v14
431; GCN-IR-NEXT:    v_not_b32_e32 v9, v17
432; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v0, v13
433; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v16, vcc
434; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
435; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
436; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
437; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
438; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
439; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
440; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v8
441; GCN-IR-NEXT:    v_or_b32_e32 v0, v14, v0
442; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
443; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v0
444; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
445; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
446; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v11
447; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
448; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
449; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v12, vcc
450; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
451; GCN-IR-NEXT:    v_and_b32_e32 v20, v13, v3
452; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v2
453; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
454; GCN-IR-NEXT:    v_mov_b32_e32 v11, v16
455; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v0, v13
456; GCN-IR-NEXT:    v_mov_b32_e32 v12, v17
457; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
458; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
459; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
460; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
461; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
462; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
463; GCN-IR-NEXT:  ; %bb.4: ; %Flow
464; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
465; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
466; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
467; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[7:8], 1
468; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v3
469; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v2
470; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
471; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
472; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v4
473; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v6
474; GCN-IR-NEXT:    v_xor_b32_e32 v3, v9, v0
475; GCN-IR-NEXT:    v_xor_b32_e32 v2, v10, v1
476; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v3, v0
477; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
478; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
479  %result = sdiv i64 %x, %y
480  ret i64 %result
481}
482
483define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
484; GCN-LABEL: s_test_sdiv24_64:
485; GCN:       ; %bb.0:
486; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
487; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
488; GCN-NEXT:    s_mov_b32 s3, 0xf000
489; GCN-NEXT:    s_mov_b32 s2, -1
490; GCN-NEXT:    s_waitcnt lgkmcnt(0)
491; GCN-NEXT:    s_mov_b32 s0, s4
492; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
493; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
494; GCN-NEXT:    s_mov_b32 s1, s5
495; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
496; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
497; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
498; GCN-NEXT:    s_xor_b32 s4, s4, s8
499; GCN-NEXT:    s_ashr_i32 s4, s4, 30
500; GCN-NEXT:    s_or_b32 s4, s4, 1
501; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
502; GCN-NEXT:    v_trunc_f32_e32 v2, v2
503; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
504; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
505; GCN-NEXT:    v_mov_b32_e32 v3, s4
506; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
507; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
508; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
509; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
510; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
511; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
512; GCN-NEXT:    s_endpgm
513;
514; GCN-IR-LABEL: s_test_sdiv24_64:
515; GCN-IR:       ; %bb.0:
516; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
517; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
518; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
519; GCN-IR-NEXT:    s_mov_b32 s2, -1
520; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
521; GCN-IR-NEXT:    s_mov_b32 s0, s4
522; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
523; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
524; GCN-IR-NEXT:    s_mov_b32 s1, s5
525; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
526; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
527; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
528; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
529; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
530; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
531; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
532; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
533; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
534; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
535; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
536; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
537; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
538; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
539; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
540; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
541; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
542; GCN-IR-NEXT:    s_endpgm
543  %1 = ashr i64 %x, 40
544  %2 = ashr i64 %y, 40
545  %result = sdiv i64 %1, %2
546  store i64 %result, i64 addrspace(1)* %out
547  ret void
548}
549
550define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
551; GCN-LABEL: v_test_sdiv24_64:
552; GCN:       ; %bb.0:
553; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
554; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
555; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
556; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
557; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
558; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
559; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
560; GCN-NEXT:    v_trunc_f32_e32 v2, v2
561; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
562; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
563; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
564; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
565; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
566; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
567; GCN-NEXT:    s_setpc_b64 s[30:31]
568;
569; GCN-IR-LABEL: v_test_sdiv24_64:
570; GCN-IR:       ; %bb.0:
571; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
572; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
573; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, v0
574; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
575; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v1
576; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
577; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
578; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
579; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
580; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
581; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
582; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
583; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
584; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
585; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
586  %1 = lshr i64 %x, 40
587  %2 = lshr i64 %y, 40
588  %result = sdiv i64 %1, %2
589  ret i64 %result
590}
591
592define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
593; GCN-LABEL: s_test_sdiv32_64:
594; GCN:       ; %bb.0:
595; GCN-NEXT:    s_load_dword s8, s[0:1], 0xe
596; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
597; GCN-NEXT:    s_mov_b32 s7, 0xf000
598; GCN-NEXT:    s_mov_b32 s6, -1
599; GCN-NEXT:    s_waitcnt lgkmcnt(0)
600; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
601; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
602; GCN-NEXT:    s_mov_b32 s4, s0
603; GCN-NEXT:    s_xor_b32 s0, s3, s8
604; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
605; GCN-NEXT:    s_ashr_i32 s0, s0, 30
606; GCN-NEXT:    s_or_b32 s0, s0, 1
607; GCN-NEXT:    v_mov_b32_e32 v3, s0
608; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
609; GCN-NEXT:    v_trunc_f32_e32 v2, v2
610; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
611; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
612; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
613; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
614; GCN-NEXT:    s_mov_b32 s5, s1
615; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
616; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
617; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
618; GCN-NEXT:    s_endpgm
619;
620; GCN-IR-LABEL: s_test_sdiv32_64:
621; GCN-IR:       ; %bb.0:
622; GCN-IR-NEXT:    s_load_dword s8, s[0:1], 0xe
623; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
624; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
625; GCN-IR-NEXT:    s_mov_b32 s6, -1
626; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
627; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
628; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
629; GCN-IR-NEXT:    s_mov_b32 s4, s0
630; GCN-IR-NEXT:    s_xor_b32 s0, s3, s8
631; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
632; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
633; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
634; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
635; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
636; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
637; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
638; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
639; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
640; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
641; GCN-IR-NEXT:    s_mov_b32 s5, s1
642; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
643; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
644; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
645; GCN-IR-NEXT:    s_endpgm
646  %1 = ashr i64 %x, 32
647  %2 = ashr i64 %y, 32
648  %result = sdiv i64 %1, %2
649  store i64 %result, i64 addrspace(1)* %out
650  ret void
651}
652
653define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
654; GCN-LABEL: s_test_sdiv31_64:
655; GCN:       ; %bb.0:
656; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
657; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
658; GCN-NEXT:    s_mov_b32 s3, 0xf000
659; GCN-NEXT:    s_mov_b32 s2, -1
660; GCN-NEXT:    s_waitcnt lgkmcnt(0)
661; GCN-NEXT:    s_mov_b32 s0, s4
662; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
663; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
664; GCN-NEXT:    s_mov_b32 s1, s5
665; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
666; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
667; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
668; GCN-NEXT:    s_xor_b32 s4, s4, s8
669; GCN-NEXT:    s_ashr_i32 s4, s4, 30
670; GCN-NEXT:    s_or_b32 s4, s4, 1
671; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
672; GCN-NEXT:    v_trunc_f32_e32 v2, v2
673; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
674; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
675; GCN-NEXT:    v_mov_b32_e32 v3, s4
676; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
677; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
678; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
679; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
680; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
681; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
682; GCN-NEXT:    s_endpgm
683;
684; GCN-IR-LABEL: s_test_sdiv31_64:
685; GCN-IR:       ; %bb.0:
686; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
687; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
688; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
689; GCN-IR-NEXT:    s_mov_b32 s2, -1
690; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
691; GCN-IR-NEXT:    s_mov_b32 s0, s4
692; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
693; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
694; GCN-IR-NEXT:    s_mov_b32 s1, s5
695; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
696; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
697; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
698; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
699; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
700; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
701; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
702; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
703; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
704; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
705; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
706; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
707; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
708; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
709; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
710; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
711; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
712; GCN-IR-NEXT:    s_endpgm
713  %1 = ashr i64 %x, 33
714  %2 = ashr i64 %y, 33
715  %result = sdiv i64 %1, %2
716  store i64 %result, i64 addrspace(1)* %out
717  ret void
718}
719
720define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
721; GCN-LABEL: s_test_sdiv23_64:
722; GCN:       ; %bb.0:
723; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
724; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
725; GCN-NEXT:    s_mov_b32 s3, 0xf000
726; GCN-NEXT:    s_mov_b32 s2, -1
727; GCN-NEXT:    s_waitcnt lgkmcnt(0)
728; GCN-NEXT:    s_mov_b32 s0, s4
729; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
730; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
731; GCN-NEXT:    s_mov_b32 s1, s5
732; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
733; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
734; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
735; GCN-NEXT:    s_xor_b32 s4, s4, s8
736; GCN-NEXT:    s_ashr_i32 s4, s4, 30
737; GCN-NEXT:    s_or_b32 s4, s4, 1
738; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
739; GCN-NEXT:    v_trunc_f32_e32 v2, v2
740; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
741; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
742; GCN-NEXT:    v_mov_b32_e32 v3, s4
743; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
744; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
745; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
746; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
747; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
748; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
749; GCN-NEXT:    s_endpgm
750;
751; GCN-IR-LABEL: s_test_sdiv23_64:
752; GCN-IR:       ; %bb.0:
753; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
754; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
755; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
756; GCN-IR-NEXT:    s_mov_b32 s2, -1
757; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
758; GCN-IR-NEXT:    s_mov_b32 s0, s4
759; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
760; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
761; GCN-IR-NEXT:    s_mov_b32 s1, s5
762; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
763; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
764; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
765; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
766; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
767; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
768; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
769; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
770; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
771; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
772; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
773; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
774; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
775; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
776; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
777; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
778; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
779; GCN-IR-NEXT:    s_endpgm
780  %1 = ashr i64 %x, 41
781  %2 = ashr i64 %y, 41
782  %result = sdiv i64 %1, %2
783  store i64 %result, i64 addrspace(1)* %out
784  ret void
785}
786
787define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
788; GCN-LABEL: s_test_sdiv25_64:
789; GCN:       ; %bb.0:
790; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
791; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
792; GCN-NEXT:    s_mov_b32 s3, 0xf000
793; GCN-NEXT:    s_mov_b32 s2, -1
794; GCN-NEXT:    s_waitcnt lgkmcnt(0)
795; GCN-NEXT:    s_mov_b32 s0, s4
796; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
797; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
798; GCN-NEXT:    s_mov_b32 s1, s5
799; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
800; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
801; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
802; GCN-NEXT:    s_xor_b32 s4, s4, s8
803; GCN-NEXT:    s_ashr_i32 s4, s4, 30
804; GCN-NEXT:    s_or_b32 s4, s4, 1
805; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
806; GCN-NEXT:    v_trunc_f32_e32 v2, v2
807; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
808; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
809; GCN-NEXT:    v_mov_b32_e32 v3, s4
810; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
811; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
812; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
813; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
814; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
815; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
816; GCN-NEXT:    s_endpgm
817;
818; GCN-IR-LABEL: s_test_sdiv25_64:
819; GCN-IR:       ; %bb.0:
820; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
821; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
822; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
823; GCN-IR-NEXT:    s_mov_b32 s2, -1
824; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
825; GCN-IR-NEXT:    s_mov_b32 s0, s4
826; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
827; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
828; GCN-IR-NEXT:    s_mov_b32 s1, s5
829; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
830; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
831; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
832; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
833; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
834; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
835; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
836; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
837; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
838; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
839; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
840; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
841; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
842; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
843; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
844; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
845; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
846; GCN-IR-NEXT:    s_endpgm
847  %1 = ashr i64 %x, 39
848  %2 = ashr i64 %y, 39
849  %result = sdiv i64 %1, %2
850  store i64 %result, i64 addrspace(1)* %out
851  ret void
852}
853
854define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
855; GCN-LABEL: s_test_sdiv24_v2i64:
856; GCN:       ; %bb.0:
857; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
858; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
859; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
860; GCN-NEXT:    s_mov_b32 s3, 0xf000
861; GCN-NEXT:    s_mov_b32 s2, -1
862; GCN-NEXT:    s_waitcnt lgkmcnt(0)
863; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
864; GCN-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
865; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
866; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
867; GCN-NEXT:    s_xor_b32 s4, s4, s8
868; GCN-NEXT:    s_ashr_i32 s4, s4, 30
869; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
870; GCN-NEXT:    s_or_b32 s4, s4, 1
871; GCN-NEXT:    v_mov_b32_e32 v3, s4
872; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
873; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
874; GCN-NEXT:    v_trunc_f32_e32 v2, v2
875; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
876; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
877; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
878; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
879; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
880; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
881; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s10
882; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s6
883; GCN-NEXT:    s_xor_b32 s4, s6, s10
884; GCN-NEXT:    s_ashr_i32 s4, s4, 30
885; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
886; GCN-NEXT:    s_or_b32 s4, s4, 1
887; GCN-NEXT:    v_mov_b32_e32 v5, s4
888; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
889; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
890; GCN-NEXT:    v_trunc_f32_e32 v4, v4
891; GCN-NEXT:    v_mad_f32 v3, -v4, v2, v3
892; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
893; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
894; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
895; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
896; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
897; GCN-NEXT:    v_bfe_i32 v2, v2, 0, 24
898; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
899; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
900; GCN-NEXT:    s_endpgm
901;
902; GCN-IR-LABEL: s_test_sdiv24_v2i64:
903; GCN-IR:       ; %bb.0:
904; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
905; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
906; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
907; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
908; GCN-IR-NEXT:    s_mov_b32 s2, -1
909; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
910; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
911; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
912; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
913; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
914; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
915; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
916; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
917; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
918; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
919; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
920; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
921; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
922; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
923; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
924; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
925; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
926; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
927; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
928; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v2, s10
929; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, s6
930; GCN-IR-NEXT:    s_xor_b32 s4, s6, s10
931; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
932; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v2
933; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
934; GCN-IR-NEXT:    v_mov_b32_e32 v5, s4
935; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
936; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
937; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
938; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v2, v3
939; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
940; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
941; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
942; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
943; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
944; GCN-IR-NEXT:    v_bfe_i32 v2, v2, 0, 24
945; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
946; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
947; GCN-IR-NEXT:    s_endpgm
948  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
949  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
950  %result = sdiv <2 x i64> %1, %2
951  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
952  ret void
953}
954
955define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
956; GCN-LABEL: s_test_sdiv24_48:
957; GCN:       ; %bb.0:
958; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
959; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
960; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
961; GCN-NEXT:    s_load_dword s8, s[0:1], 0xe
962; GCN-NEXT:    s_load_dword s0, s[0:1], 0xd
963; GCN-NEXT:    s_mov_b32 s7, 0xf000
964; GCN-NEXT:    s_waitcnt lgkmcnt(0)
965; GCN-NEXT:    v_mov_b32_e32 v2, s2
966; GCN-NEXT:    s_sext_i32_i16 s1, s3
967; GCN-NEXT:    s_sext_i32_i16 s3, s8
968; GCN-NEXT:    v_mov_b32_e32 v0, s0
969; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
970; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
971; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
972; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
973; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
974; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
975; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
976; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
977; GCN-NEXT:    s_mov_b32 s6, -1
978; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
979; GCN-NEXT:    v_trunc_f32_e32 v2, v2
980; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
981; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
982; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
983; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
984; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
985; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
986; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
987; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
988; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
989; GCN-NEXT:    s_endpgm
990;
991; GCN-IR-LABEL: s_test_sdiv24_48:
992; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
993; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
994; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
995; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
996; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
997; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
998; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
999; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1000; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
1001; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[2:3], 24
1002; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1003; GCN-IR-NEXT:    s_mov_b32 s3, s2
1004; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 24
1005; GCN-IR-NEXT:    s_ashr_i32 s4, s5, 31
1006; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[6:7]
1007; GCN-IR-NEXT:    s_mov_b32 s5, s4
1008; GCN-IR-NEXT:    s_sub_u32 s10, s6, s2
1009; GCN-IR-NEXT:    s_subb_u32 s11, s7, s2
1010; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], s[8:9]
1011; GCN-IR-NEXT:    s_sub_u32 s6, s6, s4
1012; GCN-IR-NEXT:    s_subb_u32 s7, s7, s4
1013; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
1014; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
1015; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1016; GCN-IR-NEXT:    s_or_b64 s[18:19], s[12:13], s[14:15]
1017; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s6
1018; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1019; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s7
1020; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1021; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s10
1022; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1023; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s11
1024; GCN-IR-NEXT:    s_min_u32 s16, s12, s13
1025; GCN-IR-NEXT:    s_sub_u32 s12, s14, s16
1026; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1027; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[20:21], s[12:13], 63
1028; GCN-IR-NEXT:    s_mov_b32 s15, 0
1029; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
1030; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[20:21], s[12:13], 63
1031; GCN-IR-NEXT:    s_xor_b64 s[22:23], s[18:19], -1
1032; GCN-IR-NEXT:    s_and_b64 s[20:21], s[22:23], s[20:21]
1033; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1034; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_5
1035; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1036; GCN-IR-NEXT:    s_add_u32 s18, s12, 1
1037; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1038; GCN-IR-NEXT:    s_addc_u32 s19, s13, 0
1039; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1040; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
1041; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1042; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1043; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[10:11], s12
1044; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_4
1045; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1046; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[10:11], s18
1047; GCN-IR-NEXT:    s_add_u32 s20, s6, -1
1048; GCN-IR-NEXT:    s_addc_u32 s21, s7, -1
1049; GCN-IR-NEXT:    s_not_b64 s[8:9], s[14:15]
1050; GCN-IR-NEXT:    s_add_u32 s10, s8, s16
1051; GCN-IR-NEXT:    s_mov_b32 s17, s15
1052; GCN-IR-NEXT:    s_addc_u32 s11, s9, s15
1053; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1054; GCN-IR-NEXT:    s_mov_b32 s9, 0
1055; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1056; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1057; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[18:19], 1
1058; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1059; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1060; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1061; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1062; GCN-IR-NEXT:    s_sub_u32 s8, s20, s16
1063; GCN-IR-NEXT:    s_subb_u32 s8, s21, s17
1064; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1065; GCN-IR-NEXT:    s_mov_b32 s15, s14
1066; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1067; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[6:7]
1068; GCN-IR-NEXT:    s_sub_u32 s18, s16, s18
1069; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1070; GCN-IR-NEXT:    s_subb_u32 s19, s17, s19
1071; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1072; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1073; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1074; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1075; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1076; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1077; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_3
1078; GCN-IR-NEXT:  .LBB9_4: ; %Flow3
1079; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[12:13], 1
1080; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1081; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1082; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1083; GCN-IR-NEXT:    s_branch .LBB9_6
1084; GCN-IR-NEXT:  .LBB9_5:
1085; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
1086; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[18:19]
1087; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1088; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[18:19]
1089; GCN-IR-NEXT:  .LBB9_6: ; %udiv-end
1090; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1091; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1092; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1093; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1094; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1095; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1096; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1097; GCN-IR-NEXT:    s_mov_b32 s2, -1
1098; GCN-IR-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
1099; GCN-IR-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1100; GCN-IR-NEXT:    s_endpgm
1101  %1 = ashr i48 %x, 24
1102  %2 = ashr i48 %y, 24
1103  %result = sdiv i48 %1, %2
1104  store i48 %result, i48 addrspace(1)* %out
1105  ret void
1106}
1107
1108define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1109; GCN-LABEL: s_test_sdiv_k_num_i64:
1110; GCN:       ; %bb.0:
1111; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1112; GCN-NEXT:    s_mov_b32 s7, 0xf000
1113; GCN-NEXT:    s_mov_b32 s6, -1
1114; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1115; GCN-NEXT:    s_ashr_i32 s8, s3, 31
1116; GCN-NEXT:    s_add_u32 s2, s2, s8
1117; GCN-NEXT:    s_mov_b32 s9, s8
1118; GCN-NEXT:    s_addc_u32 s3, s3, s8
1119; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[8:9]
1120; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1121; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
1122; GCN-NEXT:    s_sub_u32 s4, 0, s2
1123; GCN-NEXT:    s_subb_u32 s5, 0, s3
1124; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1125; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1126; GCN-NEXT:    v_mov_b32_e32 v1, 0
1127; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1128; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
1129; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1130; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
1131; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1132; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1133; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
1134; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
1135; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
1136; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
1137; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1138; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1139; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
1140; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1141; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
1142; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1143; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
1144; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
1145; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1146; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
1147; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1148; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1149; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
1150; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
1151; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1152; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
1153; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1154; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
1155; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
1156; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
1157; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
1158; GCN-NEXT:    s_mov_b32 s5, s1
1159; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1160; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
1161; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1162; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
1163; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
1164; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
1165; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
1166; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
1167; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
1168; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1169; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1170; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1171; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1172; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
1173; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
1174; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1175; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1176; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1177; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1178; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1179; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1180; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1181; GCN-NEXT:    v_mov_b32_e32 v4, s3
1182; GCN-NEXT:    s_mov_b32 s4, s0
1183; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1184; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
1185; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0
1186; GCN-NEXT:    v_mul_hi_u32 v2, s2, v0
1187; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1188; GCN-NEXT:    v_mul_lo_u32 v2, s2, v0
1189; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
1190; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1191; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
1192; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v2
1193; GCN-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
1194; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v3
1195; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1196; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v4
1197; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
1198; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v3
1199; GCN-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
1200; GCN-NEXT:    v_add_i32_e64 v4, s[0:1], 2, v0
1201; GCN-NEXT:    v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
1202; GCN-NEXT:    v_add_i32_e64 v6, s[0:1], 1, v0
1203; GCN-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
1204; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1205; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
1206; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
1207; GCN-NEXT:    v_cndmask_b32_e64 v3, v7, v5, s[0:1]
1208; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1209; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
1210; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
1211; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
1212; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
1213; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1214; GCN-NEXT:    v_cndmask_b32_e64 v2, v6, v4, s[0:1]
1215; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1216; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
1217; GCN-NEXT:    v_xor_b32_e32 v0, s8, v0
1218; GCN-NEXT:    v_xor_b32_e32 v1, s8, v1
1219; GCN-NEXT:    v_mov_b32_e32 v2, s8
1220; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
1221; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1222; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1223; GCN-NEXT:    s_endpgm
1224;
1225; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1226; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1227; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1228; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1229; GCN-IR-NEXT:    s_ashr_i32 s4, s3, 31
1230; GCN-IR-NEXT:    s_mov_b32 s5, s4
1231; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[4:5], s[2:3]
1232; GCN-IR-NEXT:    s_sub_u32 s2, s2, s4
1233; GCN-IR-NEXT:    s_subb_u32 s3, s3, s4
1234; GCN-IR-NEXT:    s_flbit_i32_b32 s6, s2
1235; GCN-IR-NEXT:    s_add_i32 s6, s6, 32
1236; GCN-IR-NEXT:    s_flbit_i32_b32 s7, s3
1237; GCN-IR-NEXT:    s_min_u32 s8, s6, s7
1238; GCN-IR-NEXT:    s_add_u32 s10, s8, 0xffffffc5
1239; GCN-IR-NEXT:    s_addc_u32 s11, 0, -1
1240; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1241; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[14:15], s[10:11], 63
1242; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1243; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
1244; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[14:15], s[10:11], 63
1245; GCN-IR-NEXT:    s_xor_b64 s[16:17], s[12:13], -1
1246; GCN-IR-NEXT:    s_and_b64 s[14:15], s[16:17], s[14:15]
1247; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
1248; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_5
1249; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1250; GCN-IR-NEXT:    s_add_u32 s12, s10, 1
1251; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1252; GCN-IR-NEXT:    s_addc_u32 s13, s11, 0
1253; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1254; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1255; GCN-IR-NEXT:    s_sub_i32 s9, 63, s10
1256; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1257; GCN-IR-NEXT:    s_lshl_b64 s[10:11], 24, s9
1258; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_4
1259; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1260; GCN-IR-NEXT:    s_lshr_b64 s[14:15], 24, s12
1261; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
1262; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
1263; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1264; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1265; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1266; GCN-IR-NEXT:    s_mov_b32 s7, 0
1267; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1268; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1269; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1270; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
1271; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1272; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
1273; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
1274; GCN-IR-NEXT:    s_sub_u32 s6, s16, s14
1275; GCN-IR-NEXT:    s_subb_u32 s6, s17, s15
1276; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
1277; GCN-IR-NEXT:    s_mov_b32 s13, s12
1278; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
1279; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[2:3]
1280; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
1281; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1282; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
1283; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1284; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1285; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1286; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
1287; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
1288; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1289; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_3
1290; GCN-IR-NEXT:  .LBB10_4: ; %Flow5
1291; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[10:11], 1
1292; GCN-IR-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
1293; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1294; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1295; GCN-IR-NEXT:    s_branch .LBB10_6
1296; GCN-IR-NEXT:  .LBB10_5:
1297; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1298; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[12:13]
1299; GCN-IR-NEXT:  .LBB10_6: ; %udiv-end
1300; GCN-IR-NEXT:    v_xor_b32_e32 v0, s4, v0
1301; GCN-IR-NEXT:    v_xor_b32_e32 v1, s5, v1
1302; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1303; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
1304; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1305; GCN-IR-NEXT:    s_mov_b32 s2, -1
1306; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1307; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1308; GCN-IR-NEXT:    s_endpgm
1309  %result = sdiv i64 24, %x
1310  store i64 %result, i64 addrspace(1)* %out
1311  ret void
1312}
1313
1314define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1315; GCN-LABEL: v_test_sdiv_k_num_i64:
1316; GCN:       ; %bb.0:
1317; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1318; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1319; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1320; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1321; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1322; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1323; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1324; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1325; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1326; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1327; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1328; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1329; GCN-NEXT:    v_mov_b32_e32 v12, 0
1330; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1331; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1332; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1333; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1334; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1335; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1336; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1337; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1338; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1339; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1340; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1341; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1342; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
1343; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
1344; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
1345; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
1346; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1347; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1348; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1349; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1350; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1351; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
1352; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
1353; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
1354; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1355; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1356; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1357; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1358; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1359; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1360; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1361; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1362; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1363; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1364; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1365; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1366; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1367; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1368; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1369; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1370; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1371; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1372; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1373; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1374; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1375; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1376; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1377; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
1378; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1379; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
1380; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
1381; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1382; GCN-NEXT:    v_mul_hi_u32 v4, v4, 24
1383; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1384; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1385; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1386; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1387; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1388; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1389; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1390; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 24, v5
1391; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1392; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1393; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1394; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1395; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1396; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1397; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1398; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1399; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1400; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1401; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1402; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1403; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1404; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1405; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1406; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1407; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1408; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1409; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1410; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1411; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1412; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1413; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1414; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1415; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1416; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1417; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1418; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1419; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1420; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1421; GCN-NEXT:    s_setpc_b64 s[30:31]
1422;
1423; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1424; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1425; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1426; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1427; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1428; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1429; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1430; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1431; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1432; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1433; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1434; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1435; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1436; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1437; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1438; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1439; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1440; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1441; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1442; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1443; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, 24, 0, s[4:5]
1444; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1445; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1446; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1447; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1448; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1449; GCN-IR-NEXT:    s_cbranch_execz .LBB11_6
1450; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1451; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1452; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1453; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1454; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1455; GCN-IR-NEXT:    v_lshl_b64 v[4:5], 24, v4
1456; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1457; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1458; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1459; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1460; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1461; GCN-IR-NEXT:    s_cbranch_execz .LBB11_5
1462; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1463; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1464; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1465; GCN-IR-NEXT:    v_lshr_b64 v[10:11], 24, v10
1466; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 58, v8
1467; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1468; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1469; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1470; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1471; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1472; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1473; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1474; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1475; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1476; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1477; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1478; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1479; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1480; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1481; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1482; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1483; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1484; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1485; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1486; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1487; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1488; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1489; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1490; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1491; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1492; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1493; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1494; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1495; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1496; GCN-IR-NEXT:    s_cbranch_execnz .LBB11_3
1497; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1498; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1499; GCN-IR-NEXT:  .LBB11_5: ; %Flow3
1500; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1501; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1502; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1503; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1504; GCN-IR-NEXT:  .LBB11_6: ; %Flow4
1505; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1506; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1507; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1508; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1509; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1510; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1511  %result = sdiv i64 24, %x
1512  ret i64 %result
1513}
1514
1515define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1516; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1517; GCN:       ; %bb.0:
1518; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1519; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1520; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1521; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1522; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1523; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1524; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1525; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1526; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1527; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1528; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1529; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1530; GCN-NEXT:    v_mov_b32_e32 v12, 0
1531; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1532; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1533; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1534; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1535; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1536; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1537; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1538; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1539; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1540; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1541; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1542; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1543; GCN-NEXT:    v_mul_lo_u32 v9, v3, v7
1544; GCN-NEXT:    v_mul_hi_u32 v10, v3, v8
1545; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
1546; GCN-NEXT:    v_mul_hi_u32 v13, v4, v7
1547; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1548; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1549; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1550; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1551; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1552; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
1553; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
1554; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v12, vcc
1555; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1556; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1557; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1558; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v8, vcc
1559; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
1560; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
1561; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1562; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1563; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1564; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1565; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1566; GCN-NEXT:    v_mul_hi_u32 v10, v3, v5
1567; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1568; GCN-NEXT:    v_mul_hi_u32 v8, v4, v5
1569; GCN-NEXT:    v_mul_lo_u32 v5, v4, v5
1570; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
1571; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1572; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
1573; GCN-NEXT:    v_mul_lo_u32 v6, v4, v6
1574; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1575; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
1576; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
1577; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1578; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
1579; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1580; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v4, v6, vcc
1581; GCN-NEXT:    v_lshrrev_b32_e32 v3, 17, v3
1582; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
1583; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
1584; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1585; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
1586; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v4
1587; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0x8000, v5
1588; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1589; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v5, v0
1590; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1591; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
1592; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1593; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v0
1594; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1595; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
1596; GCN-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1597; GCN-NEXT:    v_add_i32_e64 v7, s[4:5], 2, v3
1598; GCN-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1599; GCN-NEXT:    v_add_i32_e64 v9, s[4:5], 1, v3
1600; GCN-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1601; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
1602; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
1603; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v1
1604; GCN-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1605; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
1606; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
1607; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1608; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
1609; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
1610; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1611; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1612; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v6, vcc
1613; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1614; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1615; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1616; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1617; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1618; GCN-NEXT:    s_setpc_b64 s[30:31]
1619;
1620; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1621; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1622; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1623; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1624; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1625; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1626; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1627; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1628; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1629; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1630; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1631; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
1632; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1633; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1634; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1635; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1636; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1637; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1638; GCN-IR-NEXT:    v_mov_b32_e32 v6, s8
1639; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1640; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1641; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1642; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[4:5]
1643; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1644; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1645; GCN-IR-NEXT:    v_mov_b32_e32 v7, v9
1646; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1647; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1648; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1649; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1650; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1651; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1652; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5]
1653; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1654; GCN-IR-NEXT:    v_lshl_b64 v[4:5], s[8:9], v4
1655; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1656; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1657; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1658; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1659; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1660; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1661; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1662; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v0
1663; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1664; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v1, vcc
1665; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v10
1666; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1667; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1668; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1669; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1670; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1671; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1672; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1673; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1674; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1675; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1676; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1677; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
1678; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
1679; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1680; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1681; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1682; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v1
1683; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v0
1684; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1685; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1686; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1687; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1688; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1689; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v17
1690; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1691; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1692; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v16, s[4:5]
1693; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1694; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1695; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1696; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1697; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1698; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1699; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1700; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1701; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1702; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v1
1703; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v0
1704; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1705; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1706; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1707; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1708; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1709; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1710; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1711  %result = sdiv i64 32768, %x
1712  ret i64 %result
1713}
1714
1715define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1716; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1717; GCN:       ; %bb.0:
1718; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1719; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1720; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1721; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1722; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1723; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1724; GCN-NEXT:    s_setpc_b64 s[30:31]
1725;
1726; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1727; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1728; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1729; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1730; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1731; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1732; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v2
1733; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v1, v2, vcc
1734; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v7
1735; GCN-IR-NEXT:    v_add_i32_e64 v0, s[4:5], 32, v0
1736; GCN-IR-NEXT:    v_ffbh_u32_e32 v1, v8
1737; GCN-IR-NEXT:    v_min_u32_e32 v0, v0, v1
1738; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 48, v0
1739; GCN-IR-NEXT:    v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1740; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1741; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1742; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1743; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1744; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1745; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1746; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1747; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1748; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1749; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1750; GCN-IR-NEXT:    s_cbranch_execz .LBB13_6
1751; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1752; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
1753; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
1754; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4]
1755; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v3
1756; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[7:8], v3
1757; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1758; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1759; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1760; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1761; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1762; GCN-IR-NEXT:    s_cbranch_execz .LBB13_5
1763; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1764; GCN-IR-NEXT:    v_lshr_b64 v[9:10], v[7:8], v9
1765; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1766; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1767; GCN-IR-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1768; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1769; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1770; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1771; GCN-IR-NEXT:  .LBB13_3: ; %udiv-do-while
1772; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1773; GCN-IR-NEXT:    v_lshl_b64 v[9:10], v[9:10], 1
1774; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v4
1775; GCN-IR-NEXT:    v_or_b32_e32 v0, v9, v0
1776; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1777; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, s12, v0
1778; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v10, vcc
1779; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1780; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
1781; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1782; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
1783; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
1784; GCN-IR-NEXT:    v_and_b32_e32 v5, 1, v9
1785; GCN-IR-NEXT:    v_and_b32_e32 v9, 0x8000, v9
1786; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
1787; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1788; GCN-IR-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v9
1789; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1790; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1791; GCN-IR-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5]
1792; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1793; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1794; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1795; GCN-IR-NEXT:    s_cbranch_execnz .LBB13_3
1796; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1797; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1798; GCN-IR-NEXT:  .LBB13_5: ; %Flow3
1799; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1800; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1801; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1802; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1803; GCN-IR-NEXT:  .LBB13_6: ; %Flow4
1804; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1805; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v2
1806; GCN-IR-NEXT:    v_xor_b32_e32 v3, v6, v1
1807; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1808; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
1809; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1810  %result = sdiv i64 %x, 32768
1811  ret i64 %result
1812}
1813
1814define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1815; GCN-LABEL: s_test_sdiv24_k_num_i64:
1816; GCN:       ; %bb.0:
1817; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1818; GCN-NEXT:    s_mov_b32 s7, 0xf000
1819; GCN-NEXT:    s_mov_b32 s6, -1
1820; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1821; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1822; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1823; GCN-NEXT:    s_mov_b32 s3, 0x41c00000
1824; GCN-NEXT:    s_mov_b32 s4, s0
1825; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1826; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1827; GCN-NEXT:    s_or_b32 s0, s0, 1
1828; GCN-NEXT:    v_mov_b32_e32 v3, s0
1829; GCN-NEXT:    s_mov_b32 s5, s1
1830; GCN-NEXT:    v_mul_f32_e32 v1, s3, v1
1831; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1832; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s3
1833; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1834; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1835; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1836; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1837; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1838; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1839; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1840; GCN-NEXT:    s_endpgm
1841;
1842; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1843; GCN-IR:       ; %bb.0:
1844; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1845; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1846; GCN-IR-NEXT:    s_mov_b32 s6, -1
1847; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1848; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1849; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1850; GCN-IR-NEXT:    s_mov_b32 s3, 0x41c00000
1851; GCN-IR-NEXT:    s_mov_b32 s4, s0
1852; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1853; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1854; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1855; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
1856; GCN-IR-NEXT:    s_mov_b32 s5, s1
1857; GCN-IR-NEXT:    v_mul_f32_e32 v1, s3, v1
1858; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1859; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s3
1860; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1861; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1862; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1863; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1864; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1865; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1866; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1867; GCN-IR-NEXT:    s_endpgm
1868  %x.shr = ashr i64 %x, 40
1869  %result = sdiv i64 24, %x.shr
1870  store i64 %result, i64 addrspace(1)* %out
1871  ret void
1872}
1873
1874define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1875; GCN-LABEL: s_test_sdiv24_k_den_i64:
1876; GCN:       ; %bb.0:
1877; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1878; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1879; GCN-NEXT:    s_mov_b32 s7, 0xf000
1880; GCN-NEXT:    s_mov_b32 s6, -1
1881; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1882; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1883; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
1884; GCN-NEXT:    s_mov_b32 s4, s0
1885; GCN-NEXT:    s_ashr_i32 s0, s2, 30
1886; GCN-NEXT:    s_or_b32 s0, s0, 1
1887; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1888; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1889; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
1890; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1891; GCN-NEXT:    v_mov_b32_e32 v2, s0
1892; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1893; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1894; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1895; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1896; GCN-NEXT:    s_mov_b32 s5, s1
1897; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1898; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1899; GCN-NEXT:    s_endpgm
1900;
1901; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1902; GCN-IR:       ; %bb.0:
1903; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1904; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
1905; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1906; GCN-IR-NEXT:    s_mov_b32 s6, -1
1907; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1908; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
1909; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
1910; GCN-IR-NEXT:    s_mov_b32 s4, s0
1911; GCN-IR-NEXT:    s_ashr_i32 s0, s2, 30
1912; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
1913; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1914; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1915; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
1916; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1917; GCN-IR-NEXT:    v_mov_b32_e32 v2, s0
1918; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1919; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1920; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1921; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1922; GCN-IR-NEXT:    s_mov_b32 s5, s1
1923; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1924; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1925; GCN-IR-NEXT:    s_endpgm
1926  %x.shr = ashr i64 %x, 40
1927  %result = sdiv i64 %x.shr, 23423
1928  store i64 %result, i64 addrspace(1)* %out
1929  ret void
1930}
1931
1932define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
1933; GCN-LABEL: v_test_sdiv24_k_num_i64:
1934; GCN:       ; %bb.0:
1935; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1936; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1937; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1938; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1939; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1940; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1941; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1942; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1943; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1944; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1945; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1946; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1947; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1948; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1949; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1950; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1951; GCN-NEXT:    s_setpc_b64 s[30:31]
1952;
1953; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
1954; GCN-IR:       ; %bb.0:
1955; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1956; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1957; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1958; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
1959; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1960; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
1961; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1962; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1963; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1964; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
1965; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
1966; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1967; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1968; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1969; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1970; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1971; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1972  %x.shr = ashr i64 %x, 40
1973  %result = sdiv i64 24, %x.shr
1974  ret i64 %result
1975}
1976
1977define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
1978; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
1979; GCN:       ; %bb.0:
1980; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1981; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
1982; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1983; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1984; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
1985; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
1986; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1987; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1988; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1989; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
1990; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
1991; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1992; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1993; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
1994; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1995; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1996; GCN-NEXT:    s_setpc_b64 s[30:31]
1997;
1998; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
1999; GCN-IR:       ; %bb.0:
2000; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2001; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2002; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2003; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2004; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2005; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2006; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2007; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2008; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2009; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2010; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2011; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2012; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2013; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2014; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2015; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2016; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2017  %x.shr = ashr i64 %x, 40
2018  %result = sdiv i64 32768, %x.shr
2019  ret i64 %result
2020}
2021
2022define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
2023; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
2024; GCN:       ; %bb.0:
2025; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2026; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2027; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2028; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2029; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2030; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
2031; GCN-NEXT:    s_setpc_b64 s[30:31]
2032;
2033; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
2034; GCN-IR:       ; %bb.0:
2035; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2036; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2037; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2038; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2039; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2040; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2041; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
2042; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2043; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
2044; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2045; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2046; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2047; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2048; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2049; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2050; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2051  %x.shr = ashr i64 %x, 40
2052  %result = sdiv i64 %x.shr, 32768
2053  ret i64 %result
2054}
2055