1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s 4 5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { 6; GCN-LABEL: s_test_sdiv: 7; GCN: ; %bb.0: 8; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd 9; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 10; GCN-NEXT: s_mov_b32 s7, 0xf000 11; GCN-NEXT: s_mov_b32 s6, -1 12; GCN-NEXT: s_waitcnt lgkmcnt(0) 13; GCN-NEXT: s_ashr_i32 s12, s3, 31 14; GCN-NEXT: s_add_u32 s2, s2, s12 15; GCN-NEXT: s_mov_b32 s13, s12 16; GCN-NEXT: s_addc_u32 s3, s3, s12 17; GCN-NEXT: s_xor_b64 s[14:15], s[2:3], s[12:13] 18; GCN-NEXT: v_cvt_f32_u32_e32 v0, s14 19; GCN-NEXT: v_cvt_f32_u32_e32 v1, s15 20; GCN-NEXT: s_sub_u32 s2, 0, s14 21; GCN-NEXT: s_subb_u32 s3, 0, s15 22; GCN-NEXT: s_ashr_i32 s16, s11, 31 23; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 24; GCN-NEXT: v_rcp_f32_e32 v0, v0 25; GCN-NEXT: s_mov_b32 s17, s16 26; GCN-NEXT: s_mov_b32 s4, s8 27; GCN-NEXT: s_mov_b32 s5, s9 28; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 29; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 30; GCN-NEXT: v_trunc_f32_e32 v1, v1 31; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 32; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 33; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 34; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 35; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 36; GCN-NEXT: v_mul_lo_u32 v5, s3, v0 37; GCN-NEXT: v_mul_lo_u32 v4, s2, v0 38; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 39; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 40; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 41; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 42; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 43; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 44; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 45; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 46; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 47; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc 48; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 49; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 50; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc 51; GCN-NEXT: v_mov_b32_e32 v4, 0 52; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc 53; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 54; GCN-NEXT: v_mov_b32_e32 v6, 0 55; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 56; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc 57; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] 58; GCN-NEXT: v_mul_lo_u32 v5, s2, v2 59; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 60; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 61; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 62; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 63; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 64; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 65; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 66; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 67; GCN-NEXT: v_mul_hi_u32 v9, v2, v7 68; GCN-NEXT: v_mul_lo_u32 v7, v2, v7 69; GCN-NEXT: v_mul_hi_u32 v8, v2, v5 70; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 71; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc 72; GCN-NEXT: v_mul_lo_u32 v2, v2, v5 73; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 74; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc 75; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc 76; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2 77; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc 78; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 79; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1] 80; GCN-NEXT: s_add_u32 s0, s10, s16 81; GCN-NEXT: s_addc_u32 s1, s11, s16 82; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 83; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[16:17] 84; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 85; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 86; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 87; GCN-NEXT: v_mul_hi_u32 v5, s10, v1 88; GCN-NEXT: v_mul_hi_u32 v7, s11, v1 89; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 90; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 91; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc 92; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 93; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 94; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 95; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc 96; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc 97; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 98; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc 99; GCN-NEXT: v_mul_lo_u32 v2, s14, v1 100; GCN-NEXT: v_mul_hi_u32 v3, s14, v0 101; GCN-NEXT: v_mul_lo_u32 v4, s15, v0 102; GCN-NEXT: v_mov_b32_e32 v5, s15 103; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 104; GCN-NEXT: v_mul_lo_u32 v3, s14, v0 105; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 106; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 107; GCN-NEXT: v_sub_i32_e64 v3, s[0:1], s10, v3 108; GCN-NEXT: v_subb_u32_e64 v4, vcc, v4, v5, s[0:1] 109; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s14, v3 110; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc 111; GCN-NEXT: v_cmp_le_u32_e32 vcc, s15, v4 112; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc 113; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v5 114; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc 115; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s15, v4 116; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc 117; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 118; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc 119; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 120; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc 121; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v4 122; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[2:3] 123; GCN-NEXT: v_mov_b32_e32 v6, s11 124; GCN-NEXT: v_subb_u32_e64 v2, vcc, v6, v2, s[0:1] 125; GCN-NEXT: v_cmp_le_u32_e32 vcc, s15, v2 126; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc 127; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v3 128; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc 129; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s15, v2 130; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc 131; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 132; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[2:3] 133; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 134; GCN-NEXT: s_xor_b64 s[0:1], s[16:17], s[12:13] 135; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc 136; GCN-NEXT: v_xor_b32_e32 v0, s0, v0 137; GCN-NEXT: v_xor_b32_e32 v1, s1, v1 138; GCN-NEXT: v_mov_b32_e32 v2, s1 139; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 140; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc 141; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 142; GCN-NEXT: s_endpgm 143; 144; GCN-IR-LABEL: s_test_sdiv: 145; GCN-IR: ; %bb.0: ; %_udiv-special-cases 146; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 147; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd 148; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 149; GCN-IR-NEXT: s_ashr_i32 s0, s7, 31 150; GCN-IR-NEXT: s_mov_b32 s1, s0 151; GCN-IR-NEXT: s_ashr_i32 s2, s9, 31 152; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], s[6:7] 153; GCN-IR-NEXT: s_sub_u32 s10, s6, s0 154; GCN-IR-NEXT: s_mov_b32 s3, s2 155; GCN-IR-NEXT: s_subb_u32 s11, s7, s0 156; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[8:9] 157; GCN-IR-NEXT: s_sub_u32 s6, s6, s2 158; GCN-IR-NEXT: s_subb_u32 s7, s7, s2 159; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 0 160; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[10:11], 0 161; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 162; GCN-IR-NEXT: s_or_b64 s[18:19], s[12:13], s[14:15] 163; GCN-IR-NEXT: s_flbit_i32_b32 s12, s6 164; GCN-IR-NEXT: s_add_i32 s12, s12, 32 165; GCN-IR-NEXT: s_flbit_i32_b32 s14, s7 166; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0 167; GCN-IR-NEXT: s_cselect_b32 s12, s12, s14 168; GCN-IR-NEXT: s_flbit_i32_b32 s14, s10 169; GCN-IR-NEXT: s_add_i32 s14, s14, 32 170; GCN-IR-NEXT: s_flbit_i32_b32 s15, s11 171; GCN-IR-NEXT: s_cmp_eq_u32 s11, 0 172; GCN-IR-NEXT: s_cselect_b32 s16, s14, s15 173; GCN-IR-NEXT: s_sub_u32 s14, s12, s16 174; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 175; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[14:15], 63 176; GCN-IR-NEXT: s_mov_b32 s13, 0 177; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] 178; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[20:21], s[14:15], 63 179; GCN-IR-NEXT: s_xor_b64 s[22:23], s[18:19], -1 180; GCN-IR-NEXT: s_and_b64 s[20:21], s[22:23], s[20:21] 181; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] 182; GCN-IR-NEXT: s_cbranch_vccz BB0_5 183; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 184; GCN-IR-NEXT: s_add_u32 s18, s14, 1 185; GCN-IR-NEXT: v_mov_b32_e32 v0, s14 186; GCN-IR-NEXT: s_addc_u32 s19, s15, 0 187; GCN-IR-NEXT: v_mov_b32_e32 v1, s15 188; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1] 189; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 190; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc 191; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[10:11], s14 192; GCN-IR-NEXT: s_cbranch_vccz BB0_4 193; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 194; GCN-IR-NEXT: s_lshr_b64 s[18:19], s[10:11], s18 195; GCN-IR-NEXT: s_add_u32 s10, s6, -1 196; GCN-IR-NEXT: s_addc_u32 s11, s7, -1 197; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13] 198; GCN-IR-NEXT: s_mov_b32 s17, s13 199; GCN-IR-NEXT: s_add_u32 s12, s8, s16 200; GCN-IR-NEXT: s_addc_u32 s13, s9, s13 201; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 202; GCN-IR-NEXT: s_mov_b32 s9, 0 203; GCN-IR-NEXT: BB0_3: ; %udiv-do-while 204; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 205; GCN-IR-NEXT: s_lshr_b32 s8, s15, 31 206; GCN-IR-NEXT: s_lshl_b64 s[18:19], s[18:19], 1 207; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 208; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[8:9] 209; GCN-IR-NEXT: s_or_b64 s[14:15], s[16:17], s[14:15] 210; GCN-IR-NEXT: s_sub_u32 s8, s10, s18 211; GCN-IR-NEXT: s_subb_u32 s8, s11, s19 212; GCN-IR-NEXT: s_ashr_i32 s16, s8, 31 213; GCN-IR-NEXT: s_mov_b32 s17, s16 214; GCN-IR-NEXT: s_and_b32 s8, s16, 1 215; GCN-IR-NEXT: s_and_b64 s[20:21], s[16:17], s[6:7] 216; GCN-IR-NEXT: s_sub_u32 s18, s18, s20 217; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 218; GCN-IR-NEXT: s_subb_u32 s19, s19, s21 219; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 220; GCN-IR-NEXT: s_add_u32 s12, s12, 1 221; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 222; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1] 223; GCN-IR-NEXT: s_mov_b64 s[16:17], s[8:9] 224; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc 225; GCN-IR-NEXT: s_cbranch_vccz BB0_3 226; GCN-IR-NEXT: BB0_4: ; %Flow6 227; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[14:15], 1 228; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] 229; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 230; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 231; GCN-IR-NEXT: s_branch BB0_6 232; GCN-IR-NEXT: BB0_5: 233; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 234; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[18:19] 235; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 236; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[18:19] 237; GCN-IR-NEXT: BB0_6: ; %Flow7 238; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] 239; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 240; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1 241; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 242; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 243; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc 244; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 245; GCN-IR-NEXT: s_mov_b32 s6, -1 246; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 247; GCN-IR-NEXT: s_endpgm 248 %result = sdiv i64 %x, %y 249 store i64 %result, i64 addrspace(1)* %out 250 ret void 251} 252 253define i64 @v_test_sdiv(i64 %x, i64 %y) { 254; GCN-LABEL: v_test_sdiv: 255; GCN: ; %bb.0: 256; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 257; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v3 258; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 259; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc 260; GCN-NEXT: v_xor_b32_e32 v2, v2, v4 261; GCN-NEXT: v_xor_b32_e32 v3, v3, v4 262; GCN-NEXT: v_cvt_f32_u32_e32 v5, v2 263; GCN-NEXT: v_cvt_f32_u32_e32 v6, v3 264; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v2 265; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v3, vcc 266; GCN-NEXT: v_mov_b32_e32 v15, 0 267; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 268; GCN-NEXT: v_rcp_f32_e32 v5, v5 269; GCN-NEXT: v_mov_b32_e32 v14, 0 270; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 271; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 272; GCN-NEXT: v_trunc_f32_e32 v6, v6 273; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 274; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 275; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6 276; GCN-NEXT: v_mul_hi_u32 v9, v7, v5 277; GCN-NEXT: v_mul_lo_u32 v10, v7, v6 278; GCN-NEXT: v_mul_lo_u32 v11, v8, v5 279; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 280; GCN-NEXT: v_mul_lo_u32 v10, v7, v5 281; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11 282; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 283; GCN-NEXT: v_mul_hi_u32 v11, v5, v9 284; GCN-NEXT: v_mul_hi_u32 v13, v5, v10 285; GCN-NEXT: v_mul_hi_u32 v16, v6, v9 286; GCN-NEXT: v_mul_lo_u32 v9, v6, v9 287; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 288; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 289; GCN-NEXT: v_mul_hi_u32 v10, v6, v10 290; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v11, vcc 291; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v13 292; GCN-NEXT: v_addc_u32_e32 v10, vcc, v11, v10, vcc 293; GCN-NEXT: v_addc_u32_e32 v11, vcc, v16, v14, vcc 294; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 295; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9 296; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v11, vcc 297; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5] 298; GCN-NEXT: v_mul_lo_u32 v11, v7, v9 299; GCN-NEXT: v_mul_hi_u32 v12, v7, v5 300; GCN-NEXT: v_mul_lo_u32 v8, v8, v5 301; GCN-NEXT: v_mul_lo_u32 v7, v7, v5 302; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 303; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v8 304; GCN-NEXT: v_mul_lo_u32 v13, v5, v8 305; GCN-NEXT: v_mul_hi_u32 v16, v5, v7 306; GCN-NEXT: v_mul_hi_u32 v17, v5, v8 307; GCN-NEXT: v_mul_hi_u32 v12, v9, v7 308; GCN-NEXT: v_mul_lo_u32 v7, v9, v7 309; GCN-NEXT: v_add_i32_e32 v13, vcc, v16, v13 310; GCN-NEXT: v_mul_hi_u32 v11, v9, v8 311; GCN-NEXT: v_addc_u32_e32 v16, vcc, v15, v17, vcc 312; GCN-NEXT: v_mul_lo_u32 v8, v9, v8 313; GCN-NEXT: v_add_i32_e32 v7, vcc, v13, v7 314; GCN-NEXT: v_addc_u32_e32 v7, vcc, v16, v12, vcc 315; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v14, vcc 316; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 317; GCN-NEXT: v_addc_u32_e32 v8, vcc, v15, v9, vcc 318; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 319; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5] 320; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 321; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc 322; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1 323; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7 324; GCN-NEXT: v_xor_b32_e32 v0, v0, v7 325; GCN-NEXT: v_mul_lo_u32 v8, v0, v6 326; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 327; GCN-NEXT: v_mul_hi_u32 v10, v0, v6 328; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc 329; GCN-NEXT: v_xor_b32_e32 v1, v1, v7 330; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 331; GCN-NEXT: v_addc_u32_e32 v9, vcc, v15, v10, vcc 332; GCN-NEXT: v_mul_lo_u32 v10, v1, v5 333; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 334; GCN-NEXT: v_mul_hi_u32 v11, v1, v6 335; GCN-NEXT: v_mul_lo_u32 v6, v1, v6 336; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 337; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc 338; GCN-NEXT: v_addc_u32_e32 v8, vcc, v11, v14, vcc 339; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 340; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v8, vcc 341; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 342; GCN-NEXT: v_mul_hi_u32 v9, v2, v5 343; GCN-NEXT: v_mul_lo_u32 v10, v3, v5 344; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 345; GCN-NEXT: v_mul_lo_u32 v9, v2, v5 346; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 347; GCN-NEXT: v_sub_i32_e32 v10, vcc, v1, v8 348; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v9 349; GCN-NEXT: v_subb_u32_e64 v9, s[4:5], v10, v3, vcc 350; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v0, v2 351; GCN-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5] 352; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3 353; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] 354; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v2 355; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] 356; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v3 357; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc 358; GCN-NEXT: v_cndmask_b32_e64 v9, v11, v10, s[4:5] 359; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 2, v5 360; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5] 361; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 362; GCN-NEXT: v_add_i32_e64 v12, s[4:5], 1, v5 363; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc 364; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 365; GCN-NEXT: v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5] 366; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc 367; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 368; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 369; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 370; GCN-NEXT: v_cndmask_b32_e64 v9, v13, v11, s[4:5] 371; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 372; GCN-NEXT: v_cndmask_b32_e64 v1, v12, v10, s[4:5] 373; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc 374; GCN-NEXT: v_xor_b32_e32 v2, v7, v4 375; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 376; GCN-NEXT: v_xor_b32_e32 v3, v0, v2 377; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 378; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 379; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc 380; GCN-NEXT: s_setpc_b64 s[30:31] 381; 382; GCN-IR-LABEL: v_test_sdiv: 383; GCN-IR: ; %bb.0: ; %_udiv-special-cases 384; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 385; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v1 386; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v0 387; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 31, v3 388; GCN-IR-NEXT: v_sub_i32_e32 v9, vcc, v0, v4 389; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v1 390; GCN-IR-NEXT: v_subb_u32_e32 v10, vcc, v1, v4, vcc 391; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v2 392; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v5 393; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v3 394; GCN-IR-NEXT: v_subb_u32_e32 v3, vcc, v0, v5, vcc 395; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] 396; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[9:10] 397; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v2 398; GCN-IR-NEXT: s_or_b64 s[6:7], vcc, s[4:5] 399; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 32, v0 400; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v3 401; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 402; GCN-IR-NEXT: v_cndmask_b32_e32 v13, v7, v0, vcc 403; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v9 404; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 32, v0 405; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v10 406; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10 407; GCN-IR-NEXT: v_cndmask_b32_e32 v14, v7, v0, vcc 408; GCN-IR-NEXT: v_sub_i32_e32 v11, vcc, v13, v14 409; GCN-IR-NEXT: v_subb_u32_e64 v12, s[4:5], 0, 0, vcc 410; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[11:12] 411; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[4:5], 63, v[11:12] 412; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], vcc 413; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1 414; GCN-IR-NEXT: v_mov_b32_e32 v18, 0 415; GCN-IR-NEXT: v_mov_b32_e32 v6, v4 416; GCN-IR-NEXT: v_mov_b32_e32 v1, v5 417; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v10, 0, s[6:7] 418; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] 419; GCN-IR-NEXT: v_mov_b32_e32 v15, v18 420; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v9, 0, s[6:7] 421; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 422; GCN-IR-NEXT: s_cbranch_execz BB1_6 423; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 424; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v11 425; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v12, vcc 426; GCN-IR-NEXT: v_sub_i32_e64 v0, s[4:5], 63, v11 427; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[16:17], v[11:12] 428; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 429; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[9:10], v0 430; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 431; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 432; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 433; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] 434; GCN-IR-NEXT: s_cbranch_execz BB1_5 435; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 436; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, -1, v2 437; GCN-IR-NEXT: v_lshr_b64 v[16:17], v[9:10], v16 438; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v3, vcc 439; GCN-IR-NEXT: v_not_b32_e32 v10, v13 440; GCN-IR-NEXT: v_not_b32_e32 v11, v18 441; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, v10, v14 442; GCN-IR-NEXT: v_mov_b32_e32 v18, 0 443; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, v11, v15, vcc 444; GCN-IR-NEXT: v_mov_b32_e32 v19, 0 445; GCN-IR-NEXT: BB1_3: ; %udiv-do-while 446; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 447; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 448; GCN-IR-NEXT: v_lshrrev_b32_e32 v10, 31, v8 449; GCN-IR-NEXT: v_or_b32_e32 v10, v16, v10 450; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 451; GCN-IR-NEXT: v_sub_i32_e32 v11, vcc, v0, v10 452; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v9, v17, vcc 453; GCN-IR-NEXT: v_or_b32_e32 v7, v18, v7 454; GCN-IR-NEXT: v_add_i32_e32 v18, vcc, 1, v13 455; GCN-IR-NEXT: v_ashrrev_i32_e32 v15, 31, v11 456; GCN-IR-NEXT: v_or_b32_e32 v8, v19, v8 457; GCN-IR-NEXT: v_addc_u32_e32 v19, vcc, 0, v14, vcc 458; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[18:19], v[13:14] 459; GCN-IR-NEXT: v_mov_b32_e32 v13, v18 460; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 461; GCN-IR-NEXT: v_and_b32_e32 v11, 1, v15 462; GCN-IR-NEXT: v_and_b32_e32 v20, v15, v3 463; GCN-IR-NEXT: v_and_b32_e32 v15, v15, v2 464; GCN-IR-NEXT: v_sub_i32_e64 v16, s[4:5], v10, v15 465; GCN-IR-NEXT: v_mov_b32_e32 v14, v19 466; GCN-IR-NEXT: v_mov_b32_e32 v19, v12 467; GCN-IR-NEXT: v_subb_u32_e64 v17, s[4:5], v17, v20, s[4:5] 468; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] 469; GCN-IR-NEXT: v_mov_b32_e32 v18, v11 470; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] 471; GCN-IR-NEXT: s_cbranch_execnz BB1_3 472; GCN-IR-NEXT: ; %bb.4: ; %Flow 473; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 474; GCN-IR-NEXT: BB1_5: ; %Flow3 475; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 476; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[7:8], 1 477; GCN-IR-NEXT: v_or_b32_e32 v7, v12, v3 478; GCN-IR-NEXT: v_or_b32_e32 v0, v11, v2 479; GCN-IR-NEXT: BB1_6: ; %Flow4 480; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 481; GCN-IR-NEXT: v_xor_b32_e32 v2, v5, v4 482; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 483; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v6 484; GCN-IR-NEXT: v_xor_b32_e32 v3, v7, v1 485; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 486; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc 487; GCN-IR-NEXT: s_setpc_b64 s[30:31] 488 %result = sdiv i64 %x, %y 489 ret i64 %result 490} 491 492define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 493; GCN-LABEL: s_test_sdiv24_64: 494; GCN: ; %bb.0: 495; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 496; GCN-NEXT: s_load_dword s1, s[0:1], 0xe 497; GCN-NEXT: s_mov_b32 s3, 0xf000 498; GCN-NEXT: s_mov_b32 s2, -1 499; GCN-NEXT: s_waitcnt lgkmcnt(0) 500; GCN-NEXT: s_mov_b32 s0, s4 501; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 40 502; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 503; GCN-NEXT: s_mov_b32 s1, s5 504; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 40 505; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 506; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 507; GCN-NEXT: s_xor_b32 s4, s4, s8 508; GCN-NEXT: s_ashr_i32 s4, s4, 30 509; GCN-NEXT: s_or_b32 s6, s4, 1 510; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 511; GCN-NEXT: v_trunc_f32_e32 v2, v2 512; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 513; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 514; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 515; GCN-NEXT: s_cmp_lg_u32 s4, 0 516; GCN-NEXT: s_cselect_b32 s4, s6, 0 517; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 518; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 519; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 520; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 521; GCN-NEXT: s_endpgm 522; 523; GCN-IR-LABEL: s_test_sdiv24_64: 524; GCN-IR: ; %bb.0: 525; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 526; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe 527; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 528; GCN-IR-NEXT: s_mov_b32 s2, -1 529; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 530; GCN-IR-NEXT: s_mov_b32 s0, s4 531; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 40 532; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 533; GCN-IR-NEXT: s_mov_b32 s1, s5 534; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 40 535; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 536; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 537; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 538; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 539; GCN-IR-NEXT: s_or_b32 s6, s4, 1 540; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 541; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 542; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 543; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 544; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 545; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 546; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 547; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 548; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 549; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 550; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 551; GCN-IR-NEXT: s_endpgm 552 %1 = ashr i64 %x, 40 553 %2 = ashr i64 %y, 40 554 %result = sdiv i64 %1, %2 555 store i64 %result, i64 addrspace(1)* %out 556 ret void 557} 558 559define i64 @v_test_sdiv24_64(i64 %x, i64 %y) { 560; GCN-LABEL: v_test_sdiv24_64: 561; GCN: ; %bb.0: 562; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 563; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3 564; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 565; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1 566; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 567; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 568; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 569; GCN-NEXT: v_trunc_f32_e32 v2, v2 570; GCN-NEXT: v_cvt_i32_f32_e32 v3, v2 571; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 572; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| 573; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 574; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 575; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 576; GCN-NEXT: s_setpc_b64 s[30:31] 577; 578; GCN-IR-LABEL: v_test_sdiv24_64: 579; GCN-IR: ; %bb.0: 580; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 581; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3 582; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0 583; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1 584; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v1 585; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 586; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 587; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 588; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v2 589; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 590; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| 591; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 592; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 593; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 594; GCN-IR-NEXT: s_setpc_b64 s[30:31] 595 %1 = lshr i64 %x, 40 596 %2 = lshr i64 %y, 40 597 %result = sdiv i64 %1, %2 598 ret i64 %result 599} 600 601define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 602; GCN-LABEL: s_test_sdiv32_64: 603; GCN: ; %bb.0: 604; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 605; GCN-NEXT: s_waitcnt lgkmcnt(0) 606; GCN-NEXT: s_load_dword s6, s[0:1], 0xe 607; GCN-NEXT: s_mov_b32 s3, 0xf000 608; GCN-NEXT: s_mov_b32 s2, -1 609; GCN-NEXT: v_cvt_f32_i32_e32 v1, s7 610; GCN-NEXT: s_waitcnt lgkmcnt(0) 611; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 612; GCN-NEXT: s_mov_b32 s0, s4 613; GCN-NEXT: s_xor_b32 s4, s7, s6 614; GCN-NEXT: s_ashr_i32 s4, s4, 30 615; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 616; GCN-NEXT: s_mov_b32 s1, s5 617; GCN-NEXT: s_or_b32 s6, s4, 1 618; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 619; GCN-NEXT: v_trunc_f32_e32 v2, v2 620; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 621; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 622; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 623; GCN-NEXT: s_cmp_lg_u32 s4, 0 624; GCN-NEXT: s_cselect_b32 s4, s6, 0 625; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 626; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 627; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 628; GCN-NEXT: s_endpgm 629; 630; GCN-IR-LABEL: s_test_sdiv32_64: 631; GCN-IR: ; %bb.0: 632; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 633; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 634; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xe 635; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 636; GCN-IR-NEXT: s_mov_b32 s2, -1 637; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s7 638; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 639; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 640; GCN-IR-NEXT: s_mov_b32 s0, s4 641; GCN-IR-NEXT: s_xor_b32 s4, s7, s6 642; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 643; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 644; GCN-IR-NEXT: s_mov_b32 s1, s5 645; GCN-IR-NEXT: s_or_b32 s6, s4, 1 646; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 647; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 648; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 649; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 650; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 651; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 652; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 653; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 654; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 655; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 656; GCN-IR-NEXT: s_endpgm 657 %1 = ashr i64 %x, 32 658 %2 = ashr i64 %y, 32 659 %result = sdiv i64 %1, %2 660 store i64 %result, i64 addrspace(1)* %out 661 ret void 662} 663 664define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 665; GCN-LABEL: s_test_sdiv31_64: 666; GCN: ; %bb.0: 667; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 668; GCN-NEXT: s_load_dword s1, s[0:1], 0xe 669; GCN-NEXT: s_mov_b32 s3, 0xf000 670; GCN-NEXT: s_mov_b32 s2, -1 671; GCN-NEXT: s_waitcnt lgkmcnt(0) 672; GCN-NEXT: s_mov_b32 s0, s4 673; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 674; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 675; GCN-NEXT: s_mov_b32 s1, s5 676; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 677; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 678; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 679; GCN-NEXT: s_xor_b32 s4, s4, s8 680; GCN-NEXT: s_ashr_i32 s4, s4, 30 681; GCN-NEXT: s_or_b32 s6, s4, 1 682; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 683; GCN-NEXT: v_trunc_f32_e32 v2, v2 684; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 685; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 686; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 687; GCN-NEXT: s_cmp_lg_u32 s4, 0 688; GCN-NEXT: s_cselect_b32 s4, s6, 0 689; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 690; GCN-NEXT: v_bfe_i32 v0, v0, 0, 31 691; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 692; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 693; GCN-NEXT: s_endpgm 694; 695; GCN-IR-LABEL: s_test_sdiv31_64: 696; GCN-IR: ; %bb.0: 697; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 698; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe 699; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 700; GCN-IR-NEXT: s_mov_b32 s2, -1 701; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 702; GCN-IR-NEXT: s_mov_b32 s0, s4 703; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 704; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 705; GCN-IR-NEXT: s_mov_b32 s1, s5 706; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 707; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 708; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 709; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 710; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 711; GCN-IR-NEXT: s_or_b32 s6, s4, 1 712; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 713; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 714; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 715; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 716; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 717; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 718; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 719; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 720; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31 721; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 722; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 723; GCN-IR-NEXT: s_endpgm 724 %1 = ashr i64 %x, 33 725 %2 = ashr i64 %y, 33 726 %result = sdiv i64 %1, %2 727 store i64 %result, i64 addrspace(1)* %out 728 ret void 729} 730 731define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 732; GCN-LABEL: s_test_sdiv23_64: 733; GCN: ; %bb.0: 734; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 735; GCN-NEXT: s_load_dword s1, s[0:1], 0xe 736; GCN-NEXT: s_mov_b32 s3, 0xf000 737; GCN-NEXT: s_mov_b32 s2, -1 738; GCN-NEXT: s_waitcnt lgkmcnt(0) 739; GCN-NEXT: s_mov_b32 s0, s4 740; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 41 741; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 742; GCN-NEXT: s_mov_b32 s1, s5 743; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 41 744; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 745; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 746; GCN-NEXT: s_xor_b32 s4, s4, s8 747; GCN-NEXT: s_ashr_i32 s4, s4, 30 748; GCN-NEXT: s_or_b32 s6, s4, 1 749; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 750; GCN-NEXT: v_trunc_f32_e32 v2, v2 751; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 752; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 753; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 754; GCN-NEXT: s_cmp_lg_u32 s4, 0 755; GCN-NEXT: s_cselect_b32 s4, s6, 0 756; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 757; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23 758; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 759; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 760; GCN-NEXT: s_endpgm 761; 762; GCN-IR-LABEL: s_test_sdiv23_64: 763; GCN-IR: ; %bb.0: 764; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 765; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe 766; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 767; GCN-IR-NEXT: s_mov_b32 s2, -1 768; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 769; GCN-IR-NEXT: s_mov_b32 s0, s4 770; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 41 771; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 772; GCN-IR-NEXT: s_mov_b32 s1, s5 773; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 41 774; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 775; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 776; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 777; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 778; GCN-IR-NEXT: s_or_b32 s6, s4, 1 779; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 780; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 781; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 782; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 783; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 784; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 785; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 786; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 787; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 23 788; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 789; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 790; GCN-IR-NEXT: s_endpgm 791 %1 = ashr i64 %x, 41 792 %2 = ashr i64 %y, 41 793 %result = sdiv i64 %1, %2 794 store i64 %result, i64 addrspace(1)* %out 795 ret void 796} 797 798define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 799; GCN-LABEL: s_test_sdiv25_64: 800; GCN: ; %bb.0: 801; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 802; GCN-NEXT: s_load_dword s1, s[0:1], 0xe 803; GCN-NEXT: s_mov_b32 s3, 0xf000 804; GCN-NEXT: s_mov_b32 s2, -1 805; GCN-NEXT: s_waitcnt lgkmcnt(0) 806; GCN-NEXT: s_mov_b32 s0, s4 807; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 808; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 809; GCN-NEXT: s_mov_b32 s1, s5 810; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 811; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 812; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 813; GCN-NEXT: s_xor_b32 s4, s4, s8 814; GCN-NEXT: s_ashr_i32 s4, s4, 30 815; GCN-NEXT: s_or_b32 s6, s4, 1 816; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 817; GCN-NEXT: v_trunc_f32_e32 v2, v2 818; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 819; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 820; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 821; GCN-NEXT: s_cmp_lg_u32 s4, 0 822; GCN-NEXT: s_cselect_b32 s4, s6, 0 823; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 824; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 825; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 826; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 827; GCN-NEXT: s_endpgm 828; 829; GCN-IR-LABEL: s_test_sdiv25_64: 830; GCN-IR: ; %bb.0: 831; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 832; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe 833; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 834; GCN-IR-NEXT: s_mov_b32 s2, -1 835; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 836; GCN-IR-NEXT: s_mov_b32 s0, s4 837; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 838; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 839; GCN-IR-NEXT: s_mov_b32 s1, s5 840; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 841; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 842; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 843; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 844; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 845; GCN-IR-NEXT: s_or_b32 s6, s4, 1 846; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 847; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 848; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 849; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 850; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| 851; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 852; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 853; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 854; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 855; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 856; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 857; GCN-IR-NEXT: s_endpgm 858 %1 = ashr i64 %x, 39 859 %2 = ashr i64 %y, 39 860 %result = sdiv i64 %1, %2 861 store i64 %result, i64 addrspace(1)* %out 862 ret void 863} 864 865define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { 866; GCN-LABEL: s_test_sdiv24_v2i64: 867; GCN: ; %bb.0: 868; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 869; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd 870; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 871; GCN-NEXT: s_mov_b32 s7, 0xf000 872; GCN-NEXT: s_mov_b32 s6, -1 873; GCN-NEXT: s_waitcnt lgkmcnt(0) 874; GCN-NEXT: s_ashr_i64 s[8:9], s[8:9], 40 875; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 40 876; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 877; GCN-NEXT: v_cvt_f32_i32_e32 v1, s8 878; GCN-NEXT: s_xor_b32 s0, s8, s0 879; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40 880; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 881; GCN-NEXT: s_ashr_i32 s0, s0, 30 882; GCN-NEXT: s_ashr_i64 s[10:11], s[10:11], 40 883; GCN-NEXT: s_or_b32 s3, s0, 1 884; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 885; GCN-NEXT: v_trunc_f32_e32 v2, v2 886; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 887; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 888; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| 889; GCN-NEXT: s_cmp_lg_u32 s0, 0 890; GCN-NEXT: s_cselect_b32 s0, s3, 0 891; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 892; GCN-NEXT: v_cvt_f32_i32_e32 v2, s2 893; GCN-NEXT: v_cvt_f32_i32_e32 v3, s10 894; GCN-NEXT: s_xor_b32 s0, s10, s2 895; GCN-NEXT: s_ashr_i32 s0, s0, 30 896; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 897; GCN-NEXT: s_or_b32 s2, s0, 1 898; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 899; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 900; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 901; GCN-NEXT: v_trunc_f32_e32 v4, v4 902; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 903; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 904; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v2| 905; GCN-NEXT: s_cmp_lg_u32 s0, 0 906; GCN-NEXT: s_cselect_b32 s0, s2, 0 907; GCN-NEXT: v_add_i32_e32 v2, vcc, s0, v4 908; GCN-NEXT: v_bfe_i32 v2, v2, 0, 24 909; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2 910; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 911; GCN-NEXT: s_endpgm 912; 913; GCN-IR-LABEL: s_test_sdiv24_v2i64: 914; GCN-IR: ; %bb.0: 915; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 916; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd 917; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 918; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 919; GCN-IR-NEXT: s_mov_b32 s6, -1 920; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 921; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[8:9], 40 922; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 40 923; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 924; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s8 925; GCN-IR-NEXT: s_xor_b32 s0, s8, s0 926; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40 927; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 928; GCN-IR-NEXT: s_ashr_i32 s0, s0, 30 929; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[10:11], 40 930; GCN-IR-NEXT: s_or_b32 s3, s0, 1 931; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 932; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 933; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 934; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 935; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| 936; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0 937; GCN-IR-NEXT: s_cselect_b32 s0, s3, 0 938; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v2 939; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, s2 940; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, s10 941; GCN-IR-NEXT: s_xor_b32 s0, s10, s2 942; GCN-IR-NEXT: s_ashr_i32 s0, s0, 30 943; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v2 944; GCN-IR-NEXT: s_or_b32 s2, s0, 1 945; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 946; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 947; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4 948; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4 949; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3 950; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4 951; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v2| 952; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0 953; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0 954; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s0, v4 955; GCN-IR-NEXT: v_bfe_i32 v2, v2, 0, 24 956; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 31, v2 957; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 958; GCN-IR-NEXT: s_endpgm 959 %1 = ashr <2 x i64> %x, <i64 40, i64 40> 960 %2 = ashr <2 x i64> %y, <i64 40, i64 40> 961 %result = sdiv <2 x i64> %1, %2 962 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 963 ret void 964} 965 966define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) { 967; GCN-LABEL: s_test_sdiv24_48: 968; GCN: ; %bb.0: 969; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 970; GCN-NEXT: s_load_dword s2, s[0:1], 0xb 971; GCN-NEXT: s_load_dword s3, s[0:1], 0xc 972; GCN-NEXT: s_load_dword s8, s[0:1], 0xd 973; GCN-NEXT: s_load_dword s0, s[0:1], 0xe 974; GCN-NEXT: s_mov_b32 s7, 0xf000 975; GCN-NEXT: s_waitcnt lgkmcnt(0) 976; GCN-NEXT: v_mov_b32_e32 v2, s2 977; GCN-NEXT: s_sext_i32_i16 s1, s3 978; GCN-NEXT: v_mov_b32_e32 v0, s8 979; GCN-NEXT: s_sext_i32_i16 s0, s0 980; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 24 981; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 982; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 24 983; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2 984; GCN-NEXT: v_xor_b32_e32 v0, v2, v0 985; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1 986; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 987; GCN-NEXT: v_or_b32_e32 v0, 1, v0 988; GCN-NEXT: s_mov_b32 s6, -1 989; GCN-NEXT: v_mul_f32_e32 v2, v3, v4 990; GCN-NEXT: v_trunc_f32_e32 v2, v2 991; GCN-NEXT: v_mad_f32 v3, -v2, v1, v3 992; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 993; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| 994; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 995; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 996; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 997; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 998; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 999; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 1000; GCN-NEXT: s_endpgm 1001; 1002; GCN-IR-LABEL: s_test_sdiv24_48: 1003; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1004; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1005; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb 1006; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc 1007; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd 1008; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe 1009; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1010; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 1011; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[2:3], 24 1012; GCN-IR-NEXT: s_sext_i32_i16 s7, s0 1013; GCN-IR-NEXT: s_ashr_i32 s0, s3, 31 1014; GCN-IR-NEXT: s_mov_b32 s1, s0 1015; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31 1016; GCN-IR-NEXT: s_ashr_i64 s[12:13], s[6:7], 24 1017; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], s[8:9] 1018; GCN-IR-NEXT: s_sub_u32 s10, s6, s0 1019; GCN-IR-NEXT: s_mov_b32 s3, s2 1020; GCN-IR-NEXT: s_subb_u32 s11, s7, s0 1021; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[12:13] 1022; GCN-IR-NEXT: s_sub_u32 s6, s6, s2 1023; GCN-IR-NEXT: s_subb_u32 s7, s7, s2 1024; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 0 1025; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[10:11], 0 1026; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 1027; GCN-IR-NEXT: s_or_b64 s[18:19], s[12:13], s[14:15] 1028; GCN-IR-NEXT: s_flbit_i32_b32 s12, s6 1029; GCN-IR-NEXT: s_add_i32 s12, s12, 32 1030; GCN-IR-NEXT: s_flbit_i32_b32 s14, s7 1031; GCN-IR-NEXT: s_cmp_eq_u32 s7, 0 1032; GCN-IR-NEXT: s_cselect_b32 s12, s12, s14 1033; GCN-IR-NEXT: s_flbit_i32_b32 s14, s10 1034; GCN-IR-NEXT: s_add_i32 s14, s14, 32 1035; GCN-IR-NEXT: s_flbit_i32_b32 s15, s11 1036; GCN-IR-NEXT: s_cmp_eq_u32 s11, 0 1037; GCN-IR-NEXT: s_cselect_b32 s16, s14, s15 1038; GCN-IR-NEXT: s_sub_u32 s14, s12, s16 1039; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 1040; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[14:15], 63 1041; GCN-IR-NEXT: s_mov_b32 s13, 0 1042; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] 1043; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[20:21], s[14:15], 63 1044; GCN-IR-NEXT: s_xor_b64 s[22:23], s[18:19], -1 1045; GCN-IR-NEXT: s_and_b64 s[20:21], s[22:23], s[20:21] 1046; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] 1047; GCN-IR-NEXT: s_cbranch_vccz BB9_5 1048; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1049; GCN-IR-NEXT: s_add_u32 s18, s14, 1 1050; GCN-IR-NEXT: v_mov_b32_e32 v0, s14 1051; GCN-IR-NEXT: s_addc_u32 s19, s15, 0 1052; GCN-IR-NEXT: v_mov_b32_e32 v1, s15 1053; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1] 1054; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 1055; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc 1056; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[10:11], s14 1057; GCN-IR-NEXT: s_cbranch_vccz BB9_4 1058; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1059; GCN-IR-NEXT: s_lshr_b64 s[18:19], s[10:11], s18 1060; GCN-IR-NEXT: s_add_u32 s10, s6, -1 1061; GCN-IR-NEXT: s_addc_u32 s11, s7, -1 1062; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13] 1063; GCN-IR-NEXT: s_mov_b32 s17, s13 1064; GCN-IR-NEXT: s_add_u32 s12, s8, s16 1065; GCN-IR-NEXT: s_addc_u32 s13, s9, s13 1066; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 1067; GCN-IR-NEXT: s_mov_b32 s9, 0 1068; GCN-IR-NEXT: BB9_3: ; %udiv-do-while 1069; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1070; GCN-IR-NEXT: s_lshr_b32 s8, s15, 31 1071; GCN-IR-NEXT: s_lshl_b64 s[18:19], s[18:19], 1 1072; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 1073; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[8:9] 1074; GCN-IR-NEXT: s_or_b64 s[14:15], s[16:17], s[14:15] 1075; GCN-IR-NEXT: s_sub_u32 s8, s10, s18 1076; GCN-IR-NEXT: s_subb_u32 s8, s11, s19 1077; GCN-IR-NEXT: s_ashr_i32 s16, s8, 31 1078; GCN-IR-NEXT: s_mov_b32 s17, s16 1079; GCN-IR-NEXT: s_and_b32 s8, s16, 1 1080; GCN-IR-NEXT: s_and_b64 s[20:21], s[16:17], s[6:7] 1081; GCN-IR-NEXT: s_sub_u32 s18, s18, s20 1082; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 1083; GCN-IR-NEXT: s_subb_u32 s19, s19, s21 1084; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 1085; GCN-IR-NEXT: s_add_u32 s12, s12, 1 1086; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 1087; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1] 1088; GCN-IR-NEXT: s_mov_b64 s[16:17], s[8:9] 1089; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc 1090; GCN-IR-NEXT: s_cbranch_vccz BB9_3 1091; GCN-IR-NEXT: BB9_4: ; %Flow3 1092; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[14:15], 1 1093; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] 1094; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 1095; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 1096; GCN-IR-NEXT: s_branch BB9_6 1097; GCN-IR-NEXT: BB9_5: 1098; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 1099; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[18:19] 1100; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 1101; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[18:19] 1102; GCN-IR-NEXT: BB9_6: ; %Flow4 1103; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] 1104; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 1105; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1 1106; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 1107; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 1108; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc 1109; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 1110; GCN-IR-NEXT: s_mov_b32 s6, -1 1111; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 1112; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 1113; GCN-IR-NEXT: s_endpgm 1114 %1 = ashr i48 %x, 24 1115 %2 = ashr i48 %y, 24 1116 %result = sdiv i48 %1, %2 1117 store i48 %result, i48 addrspace(1)* %out 1118 ret void 1119} 1120 1121define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) { 1122; GCN-LABEL: s_test_sdiv_k_num_i64: 1123; GCN: ; %bb.0: 1124; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1125; GCN-NEXT: v_mov_b32_e32 v2, 0 1126; GCN-NEXT: s_waitcnt lgkmcnt(0) 1127; GCN-NEXT: s_ashr_i32 s8, s7, 31 1128; GCN-NEXT: s_add_u32 s0, s6, s8 1129; GCN-NEXT: s_addc_u32 s1, s7, s8 1130; GCN-NEXT: s_mov_b32 s9, s8 1131; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9] 1132; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 1133; GCN-NEXT: v_cvt_f32_u32_e32 v1, s11 1134; GCN-NEXT: s_sub_u32 s2, 0, s10 1135; GCN-NEXT: s_subb_u32 s3, 0, s11 1136; GCN-NEXT: s_mov_b32 s7, 0xf000 1137; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 1138; GCN-NEXT: v_rcp_f32_e32 v0, v0 1139; GCN-NEXT: v_mov_b32_e32 v1, 0 1140; GCN-NEXT: s_mov_b32 s6, -1 1141; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 1142; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 1143; GCN-NEXT: v_trunc_f32_e32 v3, v3 1144; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 1145; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 1146; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 1147; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 1148; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 1149; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 1150; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 1151; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1152; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 1153; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 1154; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 1155; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 1156; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 1157; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 1158; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 1159; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc 1160; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 1161; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 1162; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 1163; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc 1164; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc 1165; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1166; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 1167; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc 1168; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] 1169; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 1170; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 1171; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 1172; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 1173; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 1174; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 1175; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 1176; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 1177; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 1178; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 1179; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 1180; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 1181; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 1182; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc 1183; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 1184; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 1185; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc 1186; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc 1187; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 1188; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc 1189; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 1190; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] 1191; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 1192; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 1193; GCN-NEXT: v_mul_hi_u32 v5, 24, v0 1194; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 1195; GCN-NEXT: v_mul_hi_u32 v6, 24, v3 1196; GCN-NEXT: v_mul_hi_u32 v0, 0, v0 1197; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 1198; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1199; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v6, vcc 1200; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 1201; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v0, vcc 1202; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc 1203; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 1204; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 1205; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 1206; GCN-NEXT: v_mov_b32_e32 v5, s11 1207; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 1208; GCN-NEXT: v_mul_lo_u32 v3, s10, v0 1209; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 1210; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 1211; GCN-NEXT: v_sub_i32_e64 v3, s[0:1], 24, v3 1212; GCN-NEXT: v_subb_u32_e64 v4, vcc, v4, v5, s[0:1] 1213; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s10, v3 1214; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc 1215; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v4 1216; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc 1217; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v5 1218; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc 1219; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4 1220; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc 1221; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 1222; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc 1223; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 1224; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc 1225; GCN-NEXT: v_subb_u32_e64 v2, vcc, 0, v2, s[0:1] 1226; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v4 1227; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v2 1228; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[2:3] 1229; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc 1230; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 1231; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc 1232; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2 1233; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc 1234; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 1235; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[2:3] 1236; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 1237; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc 1238; GCN-NEXT: v_xor_b32_e32 v0, s8, v0 1239; GCN-NEXT: v_xor_b32_e32 v1, s8, v1 1240; GCN-NEXT: v_mov_b32_e32 v2, s8 1241; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 1242; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc 1243; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1244; GCN-NEXT: s_endpgm 1245; 1246; GCN-IR-LABEL: s_test_sdiv_k_num_i64: 1247; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1248; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1249; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1250; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31 1251; GCN-IR-NEXT: s_mov_b32 s5, s4 1252; GCN-IR-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3] 1253; GCN-IR-NEXT: s_sub_u32 s2, s2, s4 1254; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 1255; GCN-IR-NEXT: s_subb_u32 s3, s3, s4 1256; GCN-IR-NEXT: s_add_i32 s6, s6, 32 1257; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 1258; GCN-IR-NEXT: s_cmp_eq_u32 s3, 0 1259; GCN-IR-NEXT: s_cselect_b32 s10, s6, s7 1260; GCN-IR-NEXT: s_add_u32 s8, s10, 0xffffffc5 1261; GCN-IR-NEXT: s_addc_u32 s9, 0, -1 1262; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 0 1263; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[8:9], 63 1264; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 1265; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] 1266; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[14:15], s[8:9], 63 1267; GCN-IR-NEXT: s_xor_b64 s[16:17], s[12:13], -1 1268; GCN-IR-NEXT: s_and_b64 s[14:15], s[16:17], s[14:15] 1269; GCN-IR-NEXT: s_and_b64 vcc, exec, s[14:15] 1270; GCN-IR-NEXT: s_cbranch_vccz BB10_5 1271; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1272; GCN-IR-NEXT: s_add_u32 s14, s8, 1 1273; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 1274; GCN-IR-NEXT: s_addc_u32 s15, s9, 0 1275; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 1276; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1] 1277; GCN-IR-NEXT: s_sub_i32 s8, 63, s8 1278; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc 1279; GCN-IR-NEXT: s_lshl_b64 s[12:13], 24, s8 1280; GCN-IR-NEXT: s_cbranch_vccz BB10_4 1281; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1282; GCN-IR-NEXT: s_lshr_b64 s[16:17], 24, s14 1283; GCN-IR-NEXT: s_add_u32 s8, s2, -1 1284; GCN-IR-NEXT: s_addc_u32 s9, s3, -1 1285; GCN-IR-NEXT: s_sub_u32 s10, 58, s10 1286; GCN-IR-NEXT: s_subb_u32 s11, 0, 0 1287; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 1288; GCN-IR-NEXT: s_mov_b32 s7, 0 1289; GCN-IR-NEXT: BB10_3: ; %udiv-do-while 1290; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1291; GCN-IR-NEXT: s_lshr_b32 s6, s13, 31 1292; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 1293; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 1294; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[6:7] 1295; GCN-IR-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13] 1296; GCN-IR-NEXT: s_sub_u32 s6, s8, s16 1297; GCN-IR-NEXT: s_subb_u32 s6, s9, s17 1298; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31 1299; GCN-IR-NEXT: s_mov_b32 s15, s14 1300; GCN-IR-NEXT: s_and_b32 s6, s14, 1 1301; GCN-IR-NEXT: s_and_b64 s[18:19], s[14:15], s[2:3] 1302; GCN-IR-NEXT: s_sub_u32 s16, s16, s18 1303; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 1304; GCN-IR-NEXT: s_subb_u32 s17, s17, s19 1305; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 1306; GCN-IR-NEXT: s_add_u32 s10, s10, 1 1307; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 1308; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1] 1309; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7] 1310; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc 1311; GCN-IR-NEXT: s_cbranch_vccz BB10_3 1312; GCN-IR-NEXT: BB10_4: ; %Flow5 1313; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[12:13], 1 1314; GCN-IR-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3] 1315; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 1316; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 1317; GCN-IR-NEXT: s_branch BB10_6 1318; GCN-IR-NEXT: BB10_5: 1319; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 1320; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[12:13] 1321; GCN-IR-NEXT: BB10_6: ; %udiv-end 1322; GCN-IR-NEXT: v_xor_b32_e32 v0, s4, v0 1323; GCN-IR-NEXT: v_xor_b32_e32 v1, s5, v1 1324; GCN-IR-NEXT: v_mov_b32_e32 v2, s5 1325; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0 1326; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc 1327; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 1328; GCN-IR-NEXT: s_mov_b32 s2, -1 1329; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1330; GCN-IR-NEXT: s_endpgm 1331 %result = sdiv i64 24, %x 1332 store i64 %result, i64 addrspace(1)* %out 1333 ret void 1334} 1335 1336define i64 @v_test_sdiv_k_num_i64(i64 %x) { 1337; GCN-LABEL: v_test_sdiv_k_num_i64: 1338; GCN: ; %bb.0: 1339; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1340; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1341; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 1342; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc 1343; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 1344; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 1345; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 1346; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1 1347; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0 1348; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc 1349; GCN-NEXT: v_mov_b32_e32 v13, 0 1350; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 1351; GCN-NEXT: v_rcp_f32_e32 v3, v3 1352; GCN-NEXT: v_mov_b32_e32 v12, 0 1353; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 1354; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 1355; GCN-NEXT: v_trunc_f32_e32 v4, v4 1356; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 1357; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 1358; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 1359; GCN-NEXT: v_mul_hi_u32 v7, v5, v3 1360; GCN-NEXT: v_mul_lo_u32 v8, v5, v4 1361; GCN-NEXT: v_mul_lo_u32 v9, v6, v3 1362; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 1363; GCN-NEXT: v_mul_lo_u32 v8, v5, v3 1364; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 1365; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 1366; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 1367; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 1368; GCN-NEXT: v_mul_hi_u32 v14, v4, v7 1369; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 1370; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 1371; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 1372; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 1373; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc 1374; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 1375; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc 1376; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc 1377; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 1378; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v3, v7 1379; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc 1380; GCN-NEXT: v_addc_u32_e64 v7, vcc, v4, v8, s[4:5] 1381; GCN-NEXT: v_mul_lo_u32 v9, v5, v7 1382; GCN-NEXT: v_mul_hi_u32 v10, v5, v3 1383; GCN-NEXT: v_mul_lo_u32 v6, v6, v3 1384; GCN-NEXT: v_mul_lo_u32 v5, v5, v3 1385; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 1386; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 1387; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 1388; GCN-NEXT: v_mul_hi_u32 v14, v3, v5 1389; GCN-NEXT: v_mul_hi_u32 v15, v3, v6 1390; GCN-NEXT: v_mul_hi_u32 v10, v7, v5 1391; GCN-NEXT: v_mul_lo_u32 v5, v7, v5 1392; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v11 1393; GCN-NEXT: v_mul_hi_u32 v9, v7, v6 1394; GCN-NEXT: v_addc_u32_e32 v14, vcc, v13, v15, vcc 1395; GCN-NEXT: v_mul_lo_u32 v6, v7, v6 1396; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5 1397; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v10, vcc 1398; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v12, vcc 1399; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 1400; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc 1401; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 1402; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v6, s[4:5] 1403; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 1404; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc 1405; GCN-NEXT: v_mul_hi_u32 v6, 24, v3 1406; GCN-NEXT: v_mul_lo_u32 v5, v4, 24 1407; GCN-NEXT: v_mul_hi_u32 v7, 24, v4 1408; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 1409; GCN-NEXT: v_mul_hi_u32 v4, 0, v4 1410; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 1411; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc 1412; GCN-NEXT: v_add_i32_e32 v5, vcc, 0, v5 1413; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc 1414; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v12, vcc 1415; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 1416; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 1417; GCN-NEXT: v_mul_lo_u32 v7, v1, v3 1418; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 1419; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 1420; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 1421; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 1422; GCN-NEXT: v_sub_i32_e32 v6, vcc, 24, v6 1423; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v1, vcc 1424; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v0 1425; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5] 1426; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1 1427; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] 1428; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0 1429; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] 1430; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v1 1431; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5] 1432; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v3 1433; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5] 1434; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v3 1435; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc 1436; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5] 1437; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7 1438; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 1439; GCN-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5] 1440; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc 1441; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0 1442; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc 1443; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1 1444; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc 1445; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 1446; GCN-NEXT: v_cndmask_b32_e64 v1, v10, v8, s[4:5] 1447; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc 1448; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 1449; GCN-NEXT: v_xor_b32_e32 v3, v0, v2 1450; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 1451; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 1452; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc 1453; GCN-NEXT: s_setpc_b64 s[30:31] 1454; 1455; GCN-IR-LABEL: v_test_sdiv_k_num_i64: 1456; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1457; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1458; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1459; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 1460; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 1461; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 1462; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 1463; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc 1464; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 1465; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 1466; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 1467; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc 1468; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5 1469; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s6, v10 1470; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc 1471; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] 1472; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] 1473; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 1474; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc 1475; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] 1476; GCN-IR-NEXT: v_cndmask_b32_e64 v6, 24, 0, s[4:5] 1477; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 1478; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 1479; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 1480; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc 1481; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 1482; GCN-IR-NEXT: s_cbranch_execz BB11_6 1483; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1484; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 1485; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc 1486; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5] 1487; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 1488; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 1489; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4 1490; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 1491; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 1492; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 1493; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] 1494; GCN-IR-NEXT: s_cbranch_execz BB11_5 1495; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1496; GCN-IR-NEXT: v_lshr_b64 v[12:13], 24, v8 1497; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, -1, v0 1498; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v1, vcc 1499; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 58, v10 1500; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 1501; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, 0, v11, vcc 1502; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 1503; GCN-IR-NEXT: BB11_3: ; %udiv-do-while 1504; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1505; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 1506; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 1507; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 1508; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 1509; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v8, v12 1510; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v9, v13, vcc 1511; GCN-IR-NEXT: v_or_b32_e32 v4, v14, v4 1512; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v6 1513; GCN-IR-NEXT: v_and_b32_e32 v17, v14, v0 1514; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v14 1515; GCN-IR-NEXT: v_and_b32_e32 v16, v14, v1 1516; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v10 1517; GCN-IR-NEXT: v_or_b32_e32 v5, v15, v5 1518; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v11, vcc 1519; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11] 1520; GCN-IR-NEXT: v_mov_b32_e32 v10, v14 1521; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 1522; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v17 1523; GCN-IR-NEXT: v_mov_b32_e32 v11, v15 1524; GCN-IR-NEXT: v_mov_b32_e32 v15, v7 1525; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5] 1526; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] 1527; GCN-IR-NEXT: v_mov_b32_e32 v14, v6 1528; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] 1529; GCN-IR-NEXT: s_cbranch_execnz BB11_3 1530; GCN-IR-NEXT: ; %bb.4: ; %Flow 1531; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 1532; GCN-IR-NEXT: BB11_5: ; %Flow3 1533; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 1534; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 1535; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v1 1536; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v0 1537; GCN-IR-NEXT: BB11_6: ; %Flow4 1538; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 1539; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2 1540; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3 1541; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 1542; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc 1543; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1544 %result = sdiv i64 24, %x 1545 ret i64 %result 1546} 1547 1548define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) { 1549; GCN-LABEL: v_test_sdiv_pow2_k_num_i64: 1550; GCN: ; %bb.0: 1551; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1552; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1553; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 1554; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc 1555; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 1556; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 1557; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 1558; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1 1559; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0 1560; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc 1561; GCN-NEXT: v_mov_b32_e32 v13, 0 1562; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 1563; GCN-NEXT: v_rcp_f32_e32 v3, v3 1564; GCN-NEXT: v_mov_b32_e32 v12, 0 1565; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 1566; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 1567; GCN-NEXT: v_trunc_f32_e32 v4, v4 1568; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 1569; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 1570; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 1571; GCN-NEXT: v_mul_hi_u32 v7, v5, v3 1572; GCN-NEXT: v_mul_lo_u32 v8, v5, v4 1573; GCN-NEXT: v_mul_lo_u32 v9, v6, v3 1574; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 1575; GCN-NEXT: v_mul_lo_u32 v8, v5, v3 1576; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 1577; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 1578; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 1579; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 1580; GCN-NEXT: v_mul_hi_u32 v14, v4, v7 1581; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 1582; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 1583; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 1584; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 1585; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc 1586; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 1587; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc 1588; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc 1589; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 1590; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v3, v7 1591; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc 1592; GCN-NEXT: v_addc_u32_e64 v7, vcc, v4, v8, s[4:5] 1593; GCN-NEXT: v_mul_lo_u32 v9, v5, v7 1594; GCN-NEXT: v_mul_hi_u32 v10, v5, v3 1595; GCN-NEXT: v_mul_lo_u32 v6, v6, v3 1596; GCN-NEXT: v_mul_lo_u32 v5, v5, v3 1597; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 1598; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 1599; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 1600; GCN-NEXT: v_mul_hi_u32 v14, v3, v5 1601; GCN-NEXT: v_mul_hi_u32 v15, v3, v6 1602; GCN-NEXT: v_mul_hi_u32 v10, v7, v5 1603; GCN-NEXT: v_mul_lo_u32 v5, v7, v5 1604; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v11 1605; GCN-NEXT: v_mul_hi_u32 v9, v7, v6 1606; GCN-NEXT: v_addc_u32_e32 v14, vcc, v13, v15, vcc 1607; GCN-NEXT: v_mul_lo_u32 v6, v7, v6 1608; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5 1609; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v10, vcc 1610; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v12, vcc 1611; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 1612; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc 1613; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 1614; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v6, s[4:5] 1615; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 1616; GCN-NEXT: s_mov_b32 s4, 0x8000 1617; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc 1618; GCN-NEXT: v_mul_hi_u32 v5, s4, v3 1619; GCN-NEXT: v_mul_hi_u32 v6, s4, v4 1620; GCN-NEXT: v_lshlrev_b32_e32 v7, 15, v4 1621; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 1622; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 1623; GCN-NEXT: v_mul_hi_u32 v4, 0, v4 1624; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v6, vcc 1625; GCN-NEXT: v_add_i32_e32 v5, vcc, 0, v5 1626; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc 1627; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v12, vcc 1628; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 1629; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 1630; GCN-NEXT: v_mul_lo_u32 v7, v1, v3 1631; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 1632; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 1633; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 1634; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 1635; GCN-NEXT: v_sub_i32_e32 v6, vcc, s4, v6 1636; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v1, vcc 1637; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v0 1638; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5] 1639; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1 1640; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] 1641; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0 1642; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] 1643; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v1 1644; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5] 1645; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v3 1646; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5] 1647; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v3 1648; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc 1649; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5] 1650; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7 1651; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 1652; GCN-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5] 1653; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc 1654; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0 1655; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc 1656; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1 1657; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc 1658; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 1659; GCN-NEXT: v_cndmask_b32_e64 v1, v10, v8, s[4:5] 1660; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc 1661; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 1662; GCN-NEXT: v_xor_b32_e32 v3, v0, v2 1663; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 1664; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 1665; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc 1666; GCN-NEXT: s_setpc_b64 s[30:31] 1667; 1668; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64: 1669; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1670; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1671; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1672; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 1673; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 1674; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 1675; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 1676; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc 1677; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 1678; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 1679; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 1680; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc 1681; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 1682; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s6, v10 1683; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc 1684; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] 1685; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] 1686; GCN-IR-NEXT: s_mov_b32 s8, 0x8000 1687; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc 1688; GCN-IR-NEXT: v_mov_b32_e32 v6, s8 1689; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] 1690; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 1691; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5] 1692; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 1693; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 1694; GCN-IR-NEXT: s_mov_b32 s9, 0 1695; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 1696; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc 1697; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 1698; GCN-IR-NEXT: s_cbranch_execz BB12_6 1699; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1700; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 1701; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc 1702; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5] 1703; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 1704; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[8:9], v4 1705; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 1706; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 1707; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 1708; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 1709; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] 1710; GCN-IR-NEXT: s_cbranch_execz BB12_5 1711; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1712; GCN-IR-NEXT: s_mov_b32 s5, 0 1713; GCN-IR-NEXT: s_mov_b32 s4, 0x8000 1714; GCN-IR-NEXT: v_lshr_b64 v[12:13], s[4:5], v8 1715; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, -1, v0 1716; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v1, vcc 1717; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 47, v10 1718; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 1719; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, 0, v11, vcc 1720; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 1721; GCN-IR-NEXT: BB12_3: ; %udiv-do-while 1722; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1723; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 1724; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 1725; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 1726; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 1727; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v8, v12 1728; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v9, v13, vcc 1729; GCN-IR-NEXT: v_or_b32_e32 v4, v14, v4 1730; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v6 1731; GCN-IR-NEXT: v_and_b32_e32 v17, v14, v0 1732; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v14 1733; GCN-IR-NEXT: v_and_b32_e32 v16, v14, v1 1734; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v10 1735; GCN-IR-NEXT: v_or_b32_e32 v5, v15, v5 1736; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v11, vcc 1737; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11] 1738; GCN-IR-NEXT: v_mov_b32_e32 v10, v14 1739; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 1740; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v17 1741; GCN-IR-NEXT: v_mov_b32_e32 v11, v15 1742; GCN-IR-NEXT: v_mov_b32_e32 v15, v7 1743; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5] 1744; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] 1745; GCN-IR-NEXT: v_mov_b32_e32 v14, v6 1746; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] 1747; GCN-IR-NEXT: s_cbranch_execnz BB12_3 1748; GCN-IR-NEXT: ; %bb.4: ; %Flow 1749; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 1750; GCN-IR-NEXT: BB12_5: ; %Flow3 1751; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 1752; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 1753; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v1 1754; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v0 1755; GCN-IR-NEXT: BB12_6: ; %Flow4 1756; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 1757; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2 1758; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3 1759; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 1760; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc 1761; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1762 %result = sdiv i64 32768, %x 1763 ret i64 %result 1764} 1765 1766define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) { 1767; GCN-LABEL: v_test_sdiv_pow2_k_den_i64: 1768; GCN: ; %bb.0: 1769; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1770; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1771; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 1772; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 1773; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1774; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15 1775; GCN-NEXT: s_setpc_b64 s[30:31] 1776; 1777; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64: 1778; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1779; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1780; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1781; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 1782; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v0, v2 1783; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v7 1784; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 1785; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v1, v2, vcc 1786; GCN-IR-NEXT: v_add_i32_e64 v0, s[4:5], 32, v0 1787; GCN-IR-NEXT: v_ffbh_u32_e32 v1, v8 1788; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 1789; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[4:5] 1790; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 48, v0 1791; GCN-IR-NEXT: v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5] 1792; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8] 1793; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[3:4] 1794; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 1795; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] 1796; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] 1797; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 1798; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5] 1799; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5] 1800; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc 1801; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 1802; GCN-IR-NEXT: s_cbranch_execz BB13_6 1803; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1804; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3 1805; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc 1806; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4] 1807; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v3 1808; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 1809; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3 1810; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 1811; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 1812; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 1813; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] 1814; GCN-IR-NEXT: s_cbranch_execz BB13_5 1815; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1816; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9 1817; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0 1818; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 1819; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc 1820; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 1821; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff 1822; GCN-IR-NEXT: BB13_3: ; %udiv-do-while 1823; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1824; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1 1825; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4 1826; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0 1827; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 1828; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0 1829; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc 1830; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 1831; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v7 1832; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5 1833; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 1834; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v8, vcc 1835; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8] 1836; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9 1837; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9 1838; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 1839; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 1840; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 1841; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 1842; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 1843; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9 1844; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5] 1845; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] 1846; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 1847; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] 1848; GCN-IR-NEXT: s_cbranch_execnz BB13_3 1849; GCN-IR-NEXT: ; %bb.4: ; %Flow 1850; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 1851; GCN-IR-NEXT: BB13_5: ; %Flow3 1852; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 1853; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 1854; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 1855; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 1856; GCN-IR-NEXT: BB13_6: ; %Flow4 1857; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 1858; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2 1859; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1 1860; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 1861; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc 1862; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1863 %result = sdiv i64 %x, 32768 1864 ret i64 %result 1865} 1866 1867define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) { 1868; GCN-LABEL: s_test_sdiv24_k_num_i64: 1869; GCN: ; %bb.0: 1870; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1871; GCN-NEXT: s_mov_b32 s3, 0xf000 1872; GCN-NEXT: s_mov_b32 s2, -1 1873; GCN-NEXT: s_waitcnt lgkmcnt(0) 1874; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 1875; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 1876; GCN-NEXT: s_mov_b32 s7, 0x41c00000 1877; GCN-NEXT: s_mov_b32 s0, s4 1878; GCN-NEXT: s_ashr_i32 s4, s6, 30 1879; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 1880; GCN-NEXT: s_mov_b32 s1, s5 1881; GCN-NEXT: s_or_b32 s6, s4, 1 1882; GCN-NEXT: v_mul_f32_e32 v1, s7, v1 1883; GCN-NEXT: v_trunc_f32_e32 v1, v1 1884; GCN-NEXT: v_mad_f32 v2, -v1, v0, s7 1885; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 1886; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v0| 1887; GCN-NEXT: s_cmp_lg_u32 s4, 0 1888; GCN-NEXT: s_cselect_b32 s4, s6, 0 1889; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v1 1890; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 1891; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1892; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1893; GCN-NEXT: s_endpgm 1894; 1895; GCN-IR-LABEL: s_test_sdiv24_k_num_i64: 1896; GCN-IR: ; %bb.0: 1897; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1898; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 1899; GCN-IR-NEXT: s_mov_b32 s2, -1 1900; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1901; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 1902; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 1903; GCN-IR-NEXT: s_mov_b32 s7, 0x41c00000 1904; GCN-IR-NEXT: s_mov_b32 s0, s4 1905; GCN-IR-NEXT: s_ashr_i32 s4, s6, 30 1906; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 1907; GCN-IR-NEXT: s_mov_b32 s1, s5 1908; GCN-IR-NEXT: s_or_b32 s6, s4, 1 1909; GCN-IR-NEXT: v_mul_f32_e32 v1, s7, v1 1910; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 1911; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s7 1912; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 1913; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v0| 1914; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 1915; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 1916; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v1 1917; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 1918; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1919; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1920; GCN-IR-NEXT: s_endpgm 1921 %x.shr = ashr i64 %x, 40 1922 %result = sdiv i64 24, %x.shr 1923 store i64 %result, i64 addrspace(1)* %out 1924 ret void 1925} 1926 1927define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { 1928; GCN-LABEL: s_test_sdiv24_k_den_i64: 1929; GCN: ; %bb.0: 1930; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1931; GCN-NEXT: s_mov_b32 s8, 0x46b6fe00 1932; GCN-NEXT: s_mov_b32 s3, 0xf000 1933; GCN-NEXT: s_mov_b32 s2, -1 1934; GCN-NEXT: s_waitcnt lgkmcnt(0) 1935; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 1936; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 1937; GCN-NEXT: s_mov_b32 s0, s4 1938; GCN-NEXT: s_ashr_i32 s4, s6, 30 1939; GCN-NEXT: s_mov_b32 s1, s5 1940; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 1941; GCN-NEXT: v_trunc_f32_e32 v1, v1 1942; GCN-NEXT: v_mad_f32 v0, -v1, s8, v0 1943; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 1944; GCN-NEXT: s_or_b32 s6, s4, 1 1945; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, s8 1946; GCN-NEXT: s_cmp_lg_u32 s4, 0 1947; GCN-NEXT: s_cselect_b32 s4, s6, 0 1948; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v1 1949; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 1950; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1951; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1952; GCN-NEXT: s_endpgm 1953; 1954; GCN-IR-LABEL: s_test_sdiv24_k_den_i64: 1955; GCN-IR: ; %bb.0: 1956; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1957; GCN-IR-NEXT: s_mov_b32 s8, 0x46b6fe00 1958; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 1959; GCN-IR-NEXT: s_mov_b32 s2, -1 1960; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1961; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 1962; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 1963; GCN-IR-NEXT: s_mov_b32 s0, s4 1964; GCN-IR-NEXT: s_ashr_i32 s4, s6, 30 1965; GCN-IR-NEXT: s_mov_b32 s1, s5 1966; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 1967; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 1968; GCN-IR-NEXT: v_mad_f32 v0, -v1, s8, v0 1969; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 1970; GCN-IR-NEXT: s_or_b32 s6, s4, 1 1971; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, s8 1972; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 1973; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 1974; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v1 1975; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 1976; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1977; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1978; GCN-IR-NEXT: s_endpgm 1979 %x.shr = ashr i64 %x, 40 1980 %result = sdiv i64 %x.shr, 23423 1981 store i64 %result, i64 addrspace(1)* %out 1982 ret void 1983} 1984 1985define i64 @v_test_sdiv24_k_num_i64(i64 %x) { 1986; GCN-LABEL: v_test_sdiv24_k_num_i64: 1987; GCN: ; %bb.0: 1988; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1989; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 1990; GCN-NEXT: s_mov_b32 s4, 0x41c00000 1991; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 1992; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 1993; GCN-NEXT: v_or_b32_e32 v0, 1, v0 1994; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 1995; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 1996; GCN-NEXT: v_trunc_f32_e32 v2, v2 1997; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4 1998; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 1999; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| 2000; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 2001; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 2002; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 2003; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 2004; GCN-NEXT: s_setpc_b64 s[30:31] 2005; 2006; GCN-IR-LABEL: v_test_sdiv24_k_num_i64: 2007; GCN-IR: ; %bb.0: 2008; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2009; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 2010; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 2011; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 2012; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 2013; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 2014; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 2015; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 2016; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 2017; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4 2018; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 2019; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| 2020; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 2021; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0 2022; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 2023; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 2024; GCN-IR-NEXT: s_setpc_b64 s[30:31] 2025 %x.shr = ashr i64 %x, 40 2026 %result = sdiv i64 24, %x.shr 2027 ret i64 %result 2028} 2029 2030define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) { 2031; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64: 2032; GCN: ; %bb.0: 2033; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2034; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 2035; GCN-NEXT: s_mov_b32 s4, 0x47000000 2036; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 2037; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 2038; GCN-NEXT: v_or_b32_e32 v0, 1, v0 2039; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 2040; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 2041; GCN-NEXT: v_trunc_f32_e32 v2, v2 2042; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4 2043; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 2044; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| 2045; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 2046; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 2047; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 2048; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 2049; GCN-NEXT: s_setpc_b64 s[30:31] 2050; 2051; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64: 2052; GCN-IR: ; %bb.0: 2053; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2054; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 2055; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 2056; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 2057; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 2058; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 2059; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 2060; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 2061; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 2062; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4 2063; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 2064; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| 2065; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 2066; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0 2067; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 2068; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 2069; GCN-IR-NEXT: s_setpc_b64 s[30:31] 2070 %x.shr = ashr i64 %x, 40 2071 %result = sdiv i64 32768, %x.shr 2072 ret i64 %result 2073} 2074 2075define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) { 2076; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64: 2077; GCN: ; %bb.0: 2078; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2079; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 2080; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v1 2081; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 2082; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2083; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15 2084; GCN-NEXT: s_setpc_b64 s[30:31] 2085; 2086; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64: 2087; GCN-IR: ; %bb.0: 2088; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2089; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 2090; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 2091; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 2092; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 2093; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 2094; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v1 2095; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 2096; GCN-IR-NEXT: v_mad_f32 v1, -v2, s4, v1 2097; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 2098; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4 2099; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 2100; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0 2101; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 2102; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 2103; GCN-IR-NEXT: s_setpc_b64 s[30:31] 2104 %x.shr = ashr i64 %x, 40 2105 %result = sdiv i64 %x.shr, 32768 2106 ret i64 %result 2107} 2108