1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_sdiv:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    v_mov_b32_e32 v7, 0
10; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    s_ashr_i32 s12, s3, 31
15; GCN-NEXT:    s_add_u32 s2, s2, s12
16; GCN-NEXT:    s_mov_b32 s13, s12
17; GCN-NEXT:    s_addc_u32 s3, s3, s12
18; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
19; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
20; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
21; GCN-NEXT:    s_sub_u32 s4, 0, s2
22; GCN-NEXT:    s_subb_u32 s5, 0, s3
23; GCN-NEXT:    s_ashr_i32 s14, s11, 31
24; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
25; GCN-NEXT:    v_rcp_f32_e32 v0, v0
26; GCN-NEXT:    v_mov_b32_e32 v1, 0
27; GCN-NEXT:    s_mov_b32 s15, s14
28; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
29; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
30; GCN-NEXT:    v_trunc_f32_e32 v2, v2
31; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
32; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
33; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
34; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
35; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
36; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
37; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
38; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
39; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
40; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
41; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
42; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
43; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
44; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
45; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
47; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
48; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
49; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
50; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
51; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
52; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
53; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
54; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
55; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
56; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
57; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
58; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
59; GCN-NEXT:    s_mov_b32 s5, s9
60; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
61; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
62; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
63; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
64; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
65; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
66; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
67; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
68; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
69; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
70; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
71; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
72; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
73; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
74; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
75; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
76; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
77; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
78; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
79; GCN-NEXT:    s_add_u32 s0, s10, s14
80; GCN-NEXT:    s_addc_u32 s1, s11, s14
81; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
82; GCN-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
83; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
84; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
85; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
86; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
87; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
88; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
89; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
90; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
91; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
92; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
93; GCN-NEXT:    s_mov_b32 s4, s8
94; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
95; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
96; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
97; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
98; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
99; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
100; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
101; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
102; GCN-NEXT:    v_mov_b32_e32 v5, s3
103; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
104; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
105; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
106; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
107; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
108; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
109; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
110; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
111; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
112; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
113; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
114; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
115; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
116; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
117; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
118; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
119; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
120; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
121; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
122; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
123; GCN-NEXT:    v_mov_b32_e32 v6, s11
124; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
125; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
126; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
127; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
128; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
129; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
130; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
131; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
132; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
133; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
134; GCN-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
135; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
136; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
137; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
138; GCN-NEXT:    v_mov_b32_e32 v2, s1
139; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
140; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
141; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
142; GCN-NEXT:    s_endpgm
143;
144; GCN-IR-LABEL: s_test_sdiv:
145; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
146; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
147; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
148; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
149; GCN-IR-NEXT:    s_ashr_i32 s2, s7, 31
150; GCN-IR-NEXT:    s_mov_b32 s3, s2
151; GCN-IR-NEXT:    s_ashr_i32 s8, s1, 31
152; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[2:3], s[6:7]
153; GCN-IR-NEXT:    s_sub_u32 s10, s6, s2
154; GCN-IR-NEXT:    s_mov_b32 s9, s8
155; GCN-IR-NEXT:    s_subb_u32 s11, s7, s2
156; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[8:9], s[0:1]
157; GCN-IR-NEXT:    s_sub_u32 s6, s0, s8
158; GCN-IR-NEXT:    s_subb_u32 s7, s1, s8
159; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
160; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
161; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
162; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[0:1]
163; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s6
164; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
165; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s7
166; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
167; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s10
168; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
169; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
170; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s11
171; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
172; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
173; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
174; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s11, 0
175; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
176; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
177; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[0:1], 0, 0, vcc
178; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
179; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], 63, v[0:1]
180; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], vcc
181; GCN-IR-NEXT:    s_or_b64 s[0:1], s[12:13], s[0:1]
182; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
183; GCN-IR-NEXT:    s_cbranch_vccz BB0_2
184; GCN-IR-NEXT:  ; %bb.1:
185; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
186; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
187; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
188; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
189; GCN-IR-NEXT:    s_branch BB0_7
190; GCN-IR-NEXT:  BB0_2: ; %udiv-bb1
191; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
192; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
193; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
194; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
195; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[10:11], v0
196; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
197; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
198; GCN-IR-NEXT:  ; %bb.3:
199; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
200; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
201; GCN-IR-NEXT:    s_branch BB0_6
202; GCN-IR-NEXT:  BB0_4: ; %udiv-preheader
203; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
204; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[10:11], v4
205; GCN-IR-NEXT:    s_add_u32 s10, s6, -1
206; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
207; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
208; GCN-IR-NEXT:    s_addc_u32 s11, s7, -1
209; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
210; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
211; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
212; GCN-IR-NEXT:  BB0_5: ; %udiv-do-while
213; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
214; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
215; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
216; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
217; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
218; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
219; GCN-IR-NEXT:    v_mov_b32_e32 v2, s11
220; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s10, v6
221; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
222; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
223; GCN-IR-NEXT:    v_and_b32_e32 v10, s6, v8
224; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
225; GCN-IR-NEXT:    v_and_b32_e32 v11, s7, v8
226; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
227; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
228; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
229; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
230; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
231; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
232; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
233; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
234; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
235; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
236; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
237; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
238; GCN-IR-NEXT:  BB0_6: ; %udiv-loop-exit
239; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
240; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
241; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
242; GCN-IR-NEXT:  BB0_7: ; %udiv-end
243; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[8:9], s[2:3]
244; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
245; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
246; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
247; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
248; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
249; GCN-IR-NEXT:    s_mov_b32 s6, -1
250; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
251; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
252; GCN-IR-NEXT:    s_endpgm
253  %result = sdiv i64 %x, %y
254  store i64 %result, i64 addrspace(1)* %out
255  ret void
256}
257
258define i64 @v_test_sdiv(i64 %x, i64 %y) {
259; GCN-LABEL: v_test_sdiv:
260; GCN:       ; %bb.0:
261; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
262; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
263; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
264; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
265; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
266; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
267; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
268; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v3
269; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v2
270; GCN-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
271; GCN-NEXT:    v_mov_b32_e32 v15, 0
272; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
273; GCN-NEXT:    v_rcp_f32_e32 v5, v5
274; GCN-NEXT:    v_mov_b32_e32 v14, 0
275; GCN-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
276; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
277; GCN-NEXT:    v_trunc_f32_e32 v6, v6
278; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
279; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
280; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
281; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
282; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
283; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
284; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
285; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
286; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
287; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
288; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
289; GCN-NEXT:    v_mul_hi_u32 v13, v5, v10
290; GCN-NEXT:    v_mul_hi_u32 v16, v6, v9
291; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
292; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
293; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
294; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
295; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v11, vcc
296; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
297; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v10, vcc
298; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v16, v14, vcc
299; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
300; GCN-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
301; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v11, vcc
302; GCN-NEXT:    v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
303; GCN-NEXT:    v_mul_lo_u32 v11, v7, v9
304; GCN-NEXT:    v_mul_hi_u32 v12, v7, v5
305; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
306; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
307; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
308; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
309; GCN-NEXT:    v_mul_lo_u32 v13, v5, v8
310; GCN-NEXT:    v_mul_hi_u32 v16, v5, v7
311; GCN-NEXT:    v_mul_hi_u32 v17, v5, v8
312; GCN-NEXT:    v_mul_hi_u32 v12, v9, v7
313; GCN-NEXT:    v_mul_lo_u32 v7, v9, v7
314; GCN-NEXT:    v_add_i32_e32 v13, vcc, v16, v13
315; GCN-NEXT:    v_mul_hi_u32 v11, v9, v8
316; GCN-NEXT:    v_addc_u32_e32 v16, vcc, v15, v17, vcc
317; GCN-NEXT:    v_mul_lo_u32 v8, v9, v8
318; GCN-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
319; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v16, v12, vcc
320; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v14, vcc
321; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
322; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v15, v9, vcc
323; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
324; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
325; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
326; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
327; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
328; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
329; GCN-NEXT:    v_xor_b32_e32 v0, v0, v7
330; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
331; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
332; GCN-NEXT:    v_mul_hi_u32 v10, v0, v6
333; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
334; GCN-NEXT:    v_xor_b32_e32 v1, v1, v7
335; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
336; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v15, v10, vcc
337; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
338; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
339; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
340; GCN-NEXT:    v_mul_lo_u32 v6, v1, v6
341; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
342; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
343; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
344; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
345; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v8, vcc
346; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
347; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
348; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
349; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
350; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
351; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
352; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
353; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
354; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
355; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
356; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
357; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
358; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
359; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
360; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
361; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
362; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
363; GCN-NEXT:    v_cndmask_b32_e64 v9, v11, v10, s[4:5]
364; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 2, v5
365; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
366; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
367; GCN-NEXT:    v_add_i32_e64 v12, s[4:5], 1, v5
368; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
369; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
370; GCN-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
371; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
372; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
373; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
374; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
375; GCN-NEXT:    v_cndmask_b32_e64 v9, v13, v11, s[4:5]
376; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
377; GCN-NEXT:    v_cndmask_b32_e64 v1, v12, v10, s[4:5]
378; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v9, vcc
379; GCN-NEXT:    v_xor_b32_e32 v2, v7, v4
380; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
381; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
382; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
383; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
384; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
385; GCN-NEXT:    s_setpc_b64 s[30:31]
386;
387; GCN-IR-LABEL: v_test_sdiv:
388; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
389; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
390; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
391; GCN-IR-NEXT:    v_xor_b32_e32 v0, v4, v0
392; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
393; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v0, v4
394; GCN-IR-NEXT:    v_xor_b32_e32 v1, v4, v1
395; GCN-IR-NEXT:    v_subb_u32_e32 v10, vcc, v1, v4, vcc
396; GCN-IR-NEXT:    v_xor_b32_e32 v1, v5, v2
397; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
398; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v3
399; GCN-IR-NEXT:    v_subb_u32_e32 v3, vcc, v0, v5, vcc
400; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
401; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[9:10]
402; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v2
403; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
404; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
405; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v3
406; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
407; GCN-IR-NEXT:    v_cndmask_b32_e32 v13, v7, v0, vcc
408; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v9
409; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 32, v0
410; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v10
411; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
412; GCN-IR-NEXT:    v_cndmask_b32_e32 v14, v7, v0, vcc
413; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v13, v14
414; GCN-IR-NEXT:    v_subb_u32_e64 v12, s[4:5], 0, 0, vcc
415; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[11:12]
416; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[11:12]
417; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
418; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
419; GCN-IR-NEXT:    v_mov_b32_e32 v18, 0
420; GCN-IR-NEXT:    v_mov_b32_e32 v6, v4
421; GCN-IR-NEXT:    v_mov_b32_e32 v1, v5
422; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v10, 0, s[6:7]
423; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
424; GCN-IR-NEXT:    v_mov_b32_e32 v17, v18
425; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v9, 0, s[6:7]
426; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
427; GCN-IR-NEXT:    s_cbranch_execz BB1_6
428; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
429; GCN-IR-NEXT:    v_add_i32_e32 v15, vcc, 1, v11
430; GCN-IR-NEXT:    v_addc_u32_e32 v16, vcc, 0, v12, vcc
431; GCN-IR-NEXT:    v_sub_i32_e64 v0, s[4:5], 63, v11
432; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[15:16], v[11:12]
433; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
434; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[9:10], v0
435; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
436; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
437; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
438; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
439; GCN-IR-NEXT:    s_cbranch_execz BB1_5
440; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
441; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, -1, v2
442; GCN-IR-NEXT:    v_lshr_b64 v[15:16], v[9:10], v15
443; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, -1, v3, vcc
444; GCN-IR-NEXT:    v_not_b32_e32 v10, v13
445; GCN-IR-NEXT:    v_not_b32_e32 v11, v18
446; GCN-IR-NEXT:    v_add_i32_e32 v13, vcc, v10, v14
447; GCN-IR-NEXT:    v_addc_u32_e32 v14, vcc, v11, v17, vcc
448; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
449; GCN-IR-NEXT:    v_mov_b32_e32 v18, 0
450; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
451; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
452; GCN-IR-NEXT:    v_lshl_b64 v[15:16], v[15:16], 1
453; GCN-IR-NEXT:    v_lshrrev_b32_e32 v10, 31, v8
454; GCN-IR-NEXT:    v_or_b32_e32 v10, v15, v10
455; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
456; GCN-IR-NEXT:    v_sub_i32_e32 v11, vcc, v0, v10
457; GCN-IR-NEXT:    v_subb_u32_e32 v11, vcc, v9, v16, vcc
458; GCN-IR-NEXT:    v_or_b32_e32 v7, v17, v7
459; GCN-IR-NEXT:    v_add_i32_e32 v17, vcc, 1, v13
460; GCN-IR-NEXT:    v_ashrrev_i32_e32 v15, 31, v11
461; GCN-IR-NEXT:    v_or_b32_e32 v8, v18, v8
462; GCN-IR-NEXT:    v_addc_u32_e32 v18, vcc, 0, v14, vcc
463; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[17:18], v[13:14]
464; GCN-IR-NEXT:    v_mov_b32_e32 v13, v17
465; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
466; GCN-IR-NEXT:    v_and_b32_e32 v11, 1, v15
467; GCN-IR-NEXT:    v_and_b32_e32 v19, v15, v3
468; GCN-IR-NEXT:    v_and_b32_e32 v15, v15, v2
469; GCN-IR-NEXT:    v_sub_i32_e64 v15, s[4:5], v10, v15
470; GCN-IR-NEXT:    v_mov_b32_e32 v14, v18
471; GCN-IR-NEXT:    v_mov_b32_e32 v18, v12
472; GCN-IR-NEXT:    v_subb_u32_e64 v16, s[4:5], v16, v19, s[4:5]
473; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
474; GCN-IR-NEXT:    v_mov_b32_e32 v17, v11
475; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
476; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
477; GCN-IR-NEXT:  ; %bb.4: ; %Flow
478; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
479; GCN-IR-NEXT:  BB1_5: ; %Flow3
480; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
481; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[7:8], 1
482; GCN-IR-NEXT:    v_or_b32_e32 v7, v12, v3
483; GCN-IR-NEXT:    v_or_b32_e32 v0, v11, v2
484; GCN-IR-NEXT:  BB1_6: ; %Flow4
485; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
486; GCN-IR-NEXT:    v_xor_b32_e32 v2, v5, v4
487; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
488; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v6
489; GCN-IR-NEXT:    v_xor_b32_e32 v3, v7, v1
490; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
491; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
492; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
493  %result = sdiv i64 %x, %y
494  ret i64 %result
495}
496
497define amdgpu_kernel void @s_test_sdiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
498; GCN-LABEL: s_test_sdiv24_64:
499; GCN:       ; %bb.0:
500; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
501; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
502; GCN-NEXT:    s_mov_b32 s3, 0xf000
503; GCN-NEXT:    s_mov_b32 s2, -1
504; GCN-NEXT:    s_waitcnt lgkmcnt(0)
505; GCN-NEXT:    s_mov_b32 s0, s4
506; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
507; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
508; GCN-NEXT:    s_mov_b32 s1, s5
509; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
510; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
511; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
512; GCN-NEXT:    s_xor_b32 s4, s4, s8
513; GCN-NEXT:    s_ashr_i32 s4, s4, 30
514; GCN-NEXT:    s_or_b32 s4, s4, 1
515; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
516; GCN-NEXT:    v_trunc_f32_e32 v2, v2
517; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
518; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
519; GCN-NEXT:    v_mov_b32_e32 v3, s4
520; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
521; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
522; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
523; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
524; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
525; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
526; GCN-NEXT:    s_endpgm
527;
528; GCN-IR-LABEL: s_test_sdiv24_64:
529; GCN-IR:       ; %bb.0:
530; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
531; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
532; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
533; GCN-IR-NEXT:    s_mov_b32 s2, -1
534; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
535; GCN-IR-NEXT:    s_mov_b32 s0, s4
536; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 40
537; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
538; GCN-IR-NEXT:    s_mov_b32 s1, s5
539; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 40
540; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
541; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
542; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
543; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
544; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
545; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
546; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
547; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
548; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
549; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
550; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
551; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
552; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
553; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
554; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
555; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
556; GCN-IR-NEXT:    s_endpgm
557  %1 = ashr i64 %x, 40
558  %2 = ashr i64 %y, 40
559  %result = sdiv i64 %1, %2
560  store i64 %result, i64 addrspace(1)* %out
561  ret void
562}
563
564define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
565; GCN-LABEL: v_test_sdiv24_64:
566; GCN:       ; %bb.0:
567; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
568; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
569; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
570; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
571; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
572; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
573; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
574; GCN-NEXT:    v_trunc_f32_e32 v2, v2
575; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
576; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
577; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
578; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
579; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
580; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
581; GCN-NEXT:    s_setpc_b64 s[30:31]
582;
583; GCN-IR-LABEL: v_test_sdiv24_64:
584; GCN-IR:       ; %bb.0:
585; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
586; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
587; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, v0
588; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
589; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v1
590; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
591; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
592; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
593; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
594; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
595; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
596; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
597; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
598; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
599; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
600  %1 = lshr i64 %x, 40
601  %2 = lshr i64 %y, 40
602  %result = sdiv i64 %1, %2
603  ret i64 %result
604}
605
606define amdgpu_kernel void @s_test_sdiv32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
607; GCN-LABEL: s_test_sdiv32_64:
608; GCN:       ; %bb.0:
609; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
610; GCN-NEXT:    s_waitcnt lgkmcnt(0)
611; GCN-NEXT:    s_load_dword s6, s[0:1], 0xe
612; GCN-NEXT:    s_mov_b32 s3, 0xf000
613; GCN-NEXT:    s_mov_b32 s2, -1
614; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
615; GCN-NEXT:    s_waitcnt lgkmcnt(0)
616; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
617; GCN-NEXT:    s_mov_b32 s0, s4
618; GCN-NEXT:    s_xor_b32 s4, s7, s6
619; GCN-NEXT:    s_ashr_i32 s4, s4, 30
620; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
621; GCN-NEXT:    s_or_b32 s4, s4, 1
622; GCN-NEXT:    v_mov_b32_e32 v3, s4
623; GCN-NEXT:    s_mov_b32 s1, s5
624; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
625; GCN-NEXT:    v_trunc_f32_e32 v2, v2
626; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
627; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
628; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
629; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
630; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
631; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
632; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
633; GCN-NEXT:    s_endpgm
634;
635; GCN-IR-LABEL: s_test_sdiv32_64:
636; GCN-IR:       ; %bb.0:
637; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
638; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
639; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xe
640; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
641; GCN-IR-NEXT:    s_mov_b32 s2, -1
642; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
643; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
644; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
645; GCN-IR-NEXT:    s_mov_b32 s0, s4
646; GCN-IR-NEXT:    s_xor_b32 s4, s7, s6
647; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
648; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
649; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
650; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
651; GCN-IR-NEXT:    s_mov_b32 s1, s5
652; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
653; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
654; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
655; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
656; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
657; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
658; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
659; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
660; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
661; GCN-IR-NEXT:    s_endpgm
662  %1 = ashr i64 %x, 32
663  %2 = ashr i64 %y, 32
664  %result = sdiv i64 %1, %2
665  store i64 %result, i64 addrspace(1)* %out
666  ret void
667}
668
669define amdgpu_kernel void @s_test_sdiv31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
670; GCN-LABEL: s_test_sdiv31_64:
671; GCN:       ; %bb.0:
672; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
673; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
674; GCN-NEXT:    s_mov_b32 s3, 0xf000
675; GCN-NEXT:    s_mov_b32 s2, -1
676; GCN-NEXT:    s_waitcnt lgkmcnt(0)
677; GCN-NEXT:    s_mov_b32 s0, s4
678; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
679; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
680; GCN-NEXT:    s_mov_b32 s1, s5
681; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
682; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
683; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
684; GCN-NEXT:    s_xor_b32 s4, s4, s8
685; GCN-NEXT:    s_ashr_i32 s4, s4, 30
686; GCN-NEXT:    s_or_b32 s4, s4, 1
687; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
688; GCN-NEXT:    v_trunc_f32_e32 v2, v2
689; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
690; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
691; GCN-NEXT:    v_mov_b32_e32 v3, s4
692; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
693; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
694; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
695; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
696; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
697; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
698; GCN-NEXT:    s_endpgm
699;
700; GCN-IR-LABEL: s_test_sdiv31_64:
701; GCN-IR:       ; %bb.0:
702; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
703; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
704; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
705; GCN-IR-NEXT:    s_mov_b32 s2, -1
706; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
707; GCN-IR-NEXT:    s_mov_b32 s0, s4
708; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 33
709; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
710; GCN-IR-NEXT:    s_mov_b32 s1, s5
711; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 33
712; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
713; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
714; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
715; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
716; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
717; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
718; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
719; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
720; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
721; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
722; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
723; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
724; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
725; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
726; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
727; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
728; GCN-IR-NEXT:    s_endpgm
729  %1 = ashr i64 %x, 33
730  %2 = ashr i64 %y, 33
731  %result = sdiv i64 %1, %2
732  store i64 %result, i64 addrspace(1)* %out
733  ret void
734}
735
736define amdgpu_kernel void @s_test_sdiv23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
737; GCN-LABEL: s_test_sdiv23_64:
738; GCN:       ; %bb.0:
739; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
740; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
741; GCN-NEXT:    s_mov_b32 s3, 0xf000
742; GCN-NEXT:    s_mov_b32 s2, -1
743; GCN-NEXT:    s_waitcnt lgkmcnt(0)
744; GCN-NEXT:    s_mov_b32 s0, s4
745; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
746; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
747; GCN-NEXT:    s_mov_b32 s1, s5
748; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
749; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
750; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
751; GCN-NEXT:    s_xor_b32 s4, s4, s8
752; GCN-NEXT:    s_ashr_i32 s4, s4, 30
753; GCN-NEXT:    s_or_b32 s4, s4, 1
754; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
755; GCN-NEXT:    v_trunc_f32_e32 v2, v2
756; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
757; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
758; GCN-NEXT:    v_mov_b32_e32 v3, s4
759; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
760; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
761; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
762; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
763; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
764; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
765; GCN-NEXT:    s_endpgm
766;
767; GCN-IR-LABEL: s_test_sdiv23_64:
768; GCN-IR:       ; %bb.0:
769; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
770; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
771; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
772; GCN-IR-NEXT:    s_mov_b32 s2, -1
773; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
774; GCN-IR-NEXT:    s_mov_b32 s0, s4
775; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 41
776; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
777; GCN-IR-NEXT:    s_mov_b32 s1, s5
778; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 41
779; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
780; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
781; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
782; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
783; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
784; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
785; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
786; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
787; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
788; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
789; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
790; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
791; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
792; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
793; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
794; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
795; GCN-IR-NEXT:    s_endpgm
796  %1 = ashr i64 %x, 41
797  %2 = ashr i64 %y, 41
798  %result = sdiv i64 %1, %2
799  store i64 %result, i64 addrspace(1)* %out
800  ret void
801}
802
803define amdgpu_kernel void @s_test_sdiv25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
804; GCN-LABEL: s_test_sdiv25_64:
805; GCN:       ; %bb.0:
806; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
807; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
808; GCN-NEXT:    s_mov_b32 s3, 0xf000
809; GCN-NEXT:    s_mov_b32 s2, -1
810; GCN-NEXT:    s_waitcnt lgkmcnt(0)
811; GCN-NEXT:    s_mov_b32 s0, s4
812; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
813; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s8
814; GCN-NEXT:    s_mov_b32 s1, s5
815; GCN-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
816; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s4
817; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
818; GCN-NEXT:    s_xor_b32 s4, s4, s8
819; GCN-NEXT:    s_ashr_i32 s4, s4, 30
820; GCN-NEXT:    s_or_b32 s4, s4, 1
821; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
822; GCN-NEXT:    v_trunc_f32_e32 v2, v2
823; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
824; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
825; GCN-NEXT:    v_mov_b32_e32 v3, s4
826; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
827; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
828; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
829; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
830; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
831; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
832; GCN-NEXT:    s_endpgm
833;
834; GCN-IR-LABEL: s_test_sdiv25_64:
835; GCN-IR:       ; %bb.0:
836; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
837; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
838; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
839; GCN-IR-NEXT:    s_mov_b32 s2, -1
840; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
841; GCN-IR-NEXT:    s_mov_b32 s0, s4
842; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 39
843; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s8
844; GCN-IR-NEXT:    s_mov_b32 s1, s5
845; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[6:7], 39
846; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s4
847; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
848; GCN-IR-NEXT:    s_xor_b32 s4, s4, s8
849; GCN-IR-NEXT:    s_ashr_i32 s4, s4, 30
850; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
851; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
852; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
853; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
854; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
855; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
856; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
857; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
858; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
859; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
860; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
861; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
862; GCN-IR-NEXT:    s_endpgm
863  %1 = ashr i64 %x, 39
864  %2 = ashr i64 %y, 39
865  %result = sdiv i64 %1, %2
866  store i64 %result, i64 addrspace(1)* %out
867  ret void
868}
869
870define amdgpu_kernel void @s_test_sdiv24_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
871; GCN-LABEL: s_test_sdiv24_v2i64:
872; GCN:       ; %bb.0:
873; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
874; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
875; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
876; GCN-NEXT:    s_mov_b32 s7, 0xf000
877; GCN-NEXT:    s_mov_b32 s6, -1
878; GCN-NEXT:    s_waitcnt lgkmcnt(0)
879; GCN-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
880; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
881; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
882; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s8
883; GCN-NEXT:    s_xor_b32 s0, s8, s0
884; GCN-NEXT:    s_ashr_i32 s0, s0, 30
885; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
886; GCN-NEXT:    s_or_b32 s0, s0, 1
887; GCN-NEXT:    v_mov_b32_e32 v3, s0
888; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
889; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
890; GCN-NEXT:    v_trunc_f32_e32 v2, v2
891; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
892; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
893; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
894; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
895; GCN-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
896; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
897; GCN-NEXT:    v_cvt_f32_i32_e32 v2, s2
898; GCN-NEXT:    v_cvt_f32_i32_e32 v3, s10
899; GCN-NEXT:    s_xor_b32 s0, s10, s2
900; GCN-NEXT:    s_ashr_i32 s0, s0, 30
901; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
902; GCN-NEXT:    s_or_b32 s0, s0, 1
903; GCN-NEXT:    v_mov_b32_e32 v5, s0
904; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
905; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
906; GCN-NEXT:    v_trunc_f32_e32 v4, v4
907; GCN-NEXT:    v_mad_f32 v3, -v4, v2, v3
908; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
909; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
910; GCN-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
911; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
912; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
913; GCN-NEXT:    v_bfe_i32 v2, v2, 0, 24
914; GCN-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
915; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
916; GCN-NEXT:    s_endpgm
917;
918; GCN-IR-LABEL: s_test_sdiv24_v2i64:
919; GCN-IR:       ; %bb.0:
920; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
921; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
922; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
923; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
924; GCN-IR-NEXT:    s_mov_b32 s6, -1
925; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
926; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[8:9], 40
927; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
928; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
929; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s8
930; GCN-IR-NEXT:    s_xor_b32 s0, s8, s0
931; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
932; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
933; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
934; GCN-IR-NEXT:    v_mov_b32_e32 v3, s0
935; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
936; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
937; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
938; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
939; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
940; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
941; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
942; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[10:11], 40
943; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
944; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v2, s2
945; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, s10
946; GCN-IR-NEXT:    s_xor_b32 s0, s10, s2
947; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
948; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v2
949; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
950; GCN-IR-NEXT:    v_mov_b32_e32 v5, s0
951; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
952; GCN-IR-NEXT:    v_mul_f32_e32 v4, v3, v4
953; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
954; GCN-IR-NEXT:    v_mad_f32 v3, -v4, v2, v3
955; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
956; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
957; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
958; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
959; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
960; GCN-IR-NEXT:    v_bfe_i32 v2, v2, 0, 24
961; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
962; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
963; GCN-IR-NEXT:    s_endpgm
964  %1 = ashr <2 x i64> %x, <i64 40, i64 40>
965  %2 = ashr <2 x i64> %y, <i64 40, i64 40>
966  %result = sdiv <2 x i64> %1, %2
967  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
968  ret void
969}
970
971define amdgpu_kernel void @s_test_sdiv24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
972; GCN-LABEL: s_test_sdiv24_48:
973; GCN:       ; %bb.0:
974; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
975; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
976; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
977; GCN-NEXT:    s_load_dword s8, s[0:1], 0xd
978; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
979; GCN-NEXT:    s_mov_b32 s7, 0xf000
980; GCN-NEXT:    s_waitcnt lgkmcnt(0)
981; GCN-NEXT:    v_mov_b32_e32 v2, s2
982; GCN-NEXT:    s_sext_i32_i16 s1, s3
983; GCN-NEXT:    v_mov_b32_e32 v0, s8
984; GCN-NEXT:    s_sext_i32_i16 s0, s0
985; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
986; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
987; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
988; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
989; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
990; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
991; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
992; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
993; GCN-NEXT:    s_mov_b32 s6, -1
994; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
995; GCN-NEXT:    v_trunc_f32_e32 v2, v2
996; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
997; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
998; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
999; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
1000; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1001; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1002; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1003; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1004; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1005; GCN-NEXT:    s_endpgm
1006;
1007; GCN-IR-LABEL: s_test_sdiv24_48:
1008; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1009; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1010; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1011; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
1012; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
1013; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1014; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1015; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[2:3], 24
1016; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1017; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
1018; GCN-IR-NEXT:    s_mov_b32 s3, s2
1019; GCN-IR-NEXT:    s_ashr_i32 s6, s5, 31
1020; GCN-IR-NEXT:    s_ashr_i64 s[12:13], s[4:5], 24
1021; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[2:3], s[8:9]
1022; GCN-IR-NEXT:    s_sub_u32 s10, s4, s2
1023; GCN-IR-NEXT:    s_mov_b32 s7, s6
1024; GCN-IR-NEXT:    s_subb_u32 s11, s5, s2
1025; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[6:7], s[12:13]
1026; GCN-IR-NEXT:    s_sub_u32 s8, s4, s6
1027; GCN-IR-NEXT:    s_subb_u32 s9, s5, s6
1028; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1029; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s8
1030; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1031; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s9
1032; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1033; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s10
1034; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1035; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s9, 0
1036; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1037; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s11
1038; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1039; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1040; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1041; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s11, 0
1042; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1043; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
1044; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[0:1], 0, 0, vcc
1045; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[8:9], 0
1046; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[10:11], 0
1047; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1048; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
1049; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], 63, v[0:1]
1050; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], vcc
1051; GCN-IR-NEXT:    s_or_b64 s[0:1], s[12:13], s[0:1]
1052; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1053; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1054; GCN-IR-NEXT:    s_mov_b64 vcc, vcc
1055; GCN-IR-NEXT:    s_cbranch_vccz BB9_2
1056; GCN-IR-NEXT:  ; %bb.1:
1057; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
1058; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
1059; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1060; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
1061; GCN-IR-NEXT:    s_branch BB9_7
1062; GCN-IR-NEXT:  BB9_2: ; %udiv-bb1
1063; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1064; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
1065; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
1066; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1067; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[10:11], v0
1068; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1069; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1070; GCN-IR-NEXT:  ; %bb.3:
1071; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1072; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1073; GCN-IR-NEXT:    s_branch BB9_6
1074; GCN-IR-NEXT:  BB9_4: ; %udiv-preheader
1075; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
1076; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[10:11], v4
1077; GCN-IR-NEXT:    s_add_u32 s10, s8, -1
1078; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
1079; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1080; GCN-IR-NEXT:    s_addc_u32 s11, s9, -1
1081; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
1082; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1083; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1084; GCN-IR-NEXT:  BB9_5: ; %udiv-do-while
1085; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1086; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1087; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1088; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1089; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1090; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1091; GCN-IR-NEXT:    v_mov_b32_e32 v2, s11
1092; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s10, v6
1093; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
1094; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1095; GCN-IR-NEXT:    v_and_b32_e32 v10, s8, v8
1096; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1097; GCN-IR-NEXT:    v_and_b32_e32 v11, s9, v8
1098; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1099; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1100; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1101; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1102; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1103; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1104; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1105; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1106; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1107; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1108; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1109; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1110; GCN-IR-NEXT:  BB9_6: ; %udiv-loop-exit
1111; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1112; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1113; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1114; GCN-IR-NEXT:  BB9_7: ; %udiv-end
1115; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[6:7], s[2:3]
1116; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1117; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1118; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1119; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1120; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1121; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1122; GCN-IR-NEXT:    s_mov_b32 s6, -1
1123; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1124; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1125; GCN-IR-NEXT:    s_endpgm
1126  %1 = ashr i48 %x, 24
1127  %2 = ashr i48 %y, 24
1128  %result = sdiv i48 %1, %2
1129  store i48 %result, i48 addrspace(1)* %out
1130  ret void
1131}
1132
1133define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1134; GCN-LABEL: s_test_sdiv_k_num_i64:
1135; GCN:       ; %bb.0:
1136; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1137; GCN-NEXT:    v_mov_b32_e32 v2, 0
1138; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1139; GCN-NEXT:    s_ashr_i32 s2, s7, 31
1140; GCN-NEXT:    s_add_u32 s0, s6, s2
1141; GCN-NEXT:    s_addc_u32 s1, s7, s2
1142; GCN-NEXT:    s_mov_b32 s3, s2
1143; GCN-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
1144; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1145; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1146; GCN-NEXT:    s_sub_u32 s3, 0, s8
1147; GCN-NEXT:    s_subb_u32 s10, 0, s9
1148; GCN-NEXT:    s_mov_b32 s7, 0xf000
1149; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1150; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1151; GCN-NEXT:    v_mov_b32_e32 v1, 0
1152; GCN-NEXT:    s_mov_b32 s6, -1
1153; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1154; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1155; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1156; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1157; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1158; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1159; GCN-NEXT:    v_mul_hi_u32 v5, s3, v0
1160; GCN-NEXT:    v_mul_lo_u32 v4, s3, v3
1161; GCN-NEXT:    v_mul_lo_u32 v7, s10, v0
1162; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
1163; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1164; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1165; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1166; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1167; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1168; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1169; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1170; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1171; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1172; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
1173; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1174; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1175; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1176; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
1177; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1178; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
1179; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1180; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
1181; GCN-NEXT:    v_mul_lo_u32 v6, s3, v4
1182; GCN-NEXT:    v_mul_hi_u32 v7, s3, v0
1183; GCN-NEXT:    v_mul_lo_u32 v8, s10, v0
1184; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1185; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
1186; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
1187; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
1188; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
1189; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
1190; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
1191; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1192; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
1193; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1194; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
1195; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1196; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
1197; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
1198; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
1199; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1200; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
1201; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1202; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
1203; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1204; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1205; GCN-NEXT:    v_mul_hi_u32 v5, 24, v0
1206; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1207; GCN-NEXT:    v_mul_hi_u32 v6, 24, v3
1208; GCN-NEXT:    v_mul_hi_u32 v0, 0, v0
1209; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1210; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1211; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v6, vcc
1212; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
1213; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
1214; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
1215; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
1216; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
1217; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
1218; GCN-NEXT:    v_mov_b32_e32 v5, s9
1219; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1220; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
1221; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1222; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
1223; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
1224; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
1225; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v3
1226; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
1227; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
1228; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
1229; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v5
1230; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1231; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v4
1232; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
1233; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
1234; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
1235; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
1236; GCN-NEXT:    v_subb_u32_e32 v2, vcc, 0, v2, vcc
1237; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
1238; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
1239; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
1240; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
1241; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1242; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
1243; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1244; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
1245; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
1246; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
1247; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
1248; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1249; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1250; GCN-NEXT:    v_xor_b32_e32 v0, s2, v0
1251; GCN-NEXT:    v_xor_b32_e32 v1, s2, v1
1252; GCN-NEXT:    v_mov_b32_e32 v2, s2
1253; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1254; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1255; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1256; GCN-NEXT:    s_endpgm
1257;
1258; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1259; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1260; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1261; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1262; GCN-IR-NEXT:    s_ashr_i32 s2, s7, 31
1263; GCN-IR-NEXT:    s_mov_b32 s3, s2
1264; GCN-IR-NEXT:    s_xor_b64 s[0:1], s[2:3], s[6:7]
1265; GCN-IR-NEXT:    s_sub_u32 s8, s0, s2
1266; GCN-IR-NEXT:    s_subb_u32 s9, s1, s2
1267; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s8
1268; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1269; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s9
1270; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1271; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1272; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s9, 0
1273; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1274; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc5, v2
1275; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[0:1], 0, -1, vcc
1276; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1277; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1278; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], 63, v[0:1]
1279; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], vcc
1280; GCN-IR-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
1281; GCN-IR-NEXT:    s_mov_b32 s6, -1
1282; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1283; GCN-IR-NEXT:    s_cbranch_vccz BB10_2
1284; GCN-IR-NEXT:  ; %bb.1:
1285; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1286; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1287; GCN-IR-NEXT:    s_branch BB10_7
1288; GCN-IR-NEXT:  BB10_2: ; %udiv-bb1
1289; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1290; GCN-IR-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
1291; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
1292; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1293; GCN-IR-NEXT:    v_lshl_b64 v[0:1], 24, v0
1294; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1295; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1296; GCN-IR-NEXT:  ; %bb.3:
1297; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1298; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1299; GCN-IR-NEXT:    s_branch BB10_6
1300; GCN-IR-NEXT:  BB10_4: ; %udiv-preheader
1301; GCN-IR-NEXT:    s_add_u32 s7, s8, -1
1302; GCN-IR-NEXT:    v_lshr_b64 v[6:7], 24, v3
1303; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 58, v2
1304; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1305; GCN-IR-NEXT:    s_addc_u32 s10, s9, -1
1306; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[0:1], 0, 0, vcc
1307; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1308; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1309; GCN-IR-NEXT:  BB10_5: ; %udiv-do-while
1310; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1311; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1312; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1313; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1314; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1315; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1316; GCN-IR-NEXT:    v_mov_b32_e32 v2, s10
1317; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s7, v6
1318; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
1319; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1320; GCN-IR-NEXT:    v_and_b32_e32 v10, s8, v8
1321; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1322; GCN-IR-NEXT:    v_and_b32_e32 v11, s9, v8
1323; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1324; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1325; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1326; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1327; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1328; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1329; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1330; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1331; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1332; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1333; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1334; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1335; GCN-IR-NEXT:  BB10_6: ; %udiv-loop-exit
1336; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1337; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1338; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1339; GCN-IR-NEXT:  BB10_7: ; %udiv-end
1340; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1341; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1342; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1343; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1344; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1345; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1346; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1347; GCN-IR-NEXT:    s_endpgm
1348  %result = sdiv i64 24, %x
1349  store i64 %result, i64 addrspace(1)* %out
1350  ret void
1351}
1352
1353define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1354; GCN-LABEL: v_test_sdiv_k_num_i64:
1355; GCN:       ; %bb.0:
1356; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1357; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1358; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1359; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1360; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1361; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1362; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1363; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1364; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1365; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1366; GCN-NEXT:    v_mov_b32_e32 v13, 0
1367; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1368; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1369; GCN-NEXT:    v_mov_b32_e32 v12, 0
1370; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1371; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1372; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1373; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1374; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1375; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1376; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1377; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1378; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1379; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1380; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1381; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1382; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1383; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1384; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1385; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1386; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1387; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1388; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1389; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1390; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1391; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1392; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1393; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1394; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1395; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
1396; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1397; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
1398; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
1399; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
1400; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1401; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1402; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1403; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
1404; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
1405; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
1406; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
1407; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
1408; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
1409; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
1410; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
1411; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
1412; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
1413; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
1414; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
1415; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
1416; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1417; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1418; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
1419; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
1420; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1421; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
1422; GCN-NEXT:    v_mul_hi_u32 v6, 24, v3
1423; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
1424; GCN-NEXT:    v_mul_hi_u32 v7, 24, v4
1425; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1426; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
1427; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1428; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1429; GCN-NEXT:    v_add_i32_e32 v5, vcc, 0, v5
1430; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
1431; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
1432; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
1433; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1434; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
1435; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1436; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1437; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1438; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
1439; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 24, v6
1440; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
1441; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
1442; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
1443; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
1444; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
1445; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
1446; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1447; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
1448; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
1449; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
1450; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
1451; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
1452; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
1453; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
1454; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1455; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
1456; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
1457; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
1458; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
1459; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1460; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
1461; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
1462; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1463; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
1464; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
1465; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1466; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1467; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1468; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1469; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1470; GCN-NEXT:    s_setpc_b64 s[30:31]
1471;
1472; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1473; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1474; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1475; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1476; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1477; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1478; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1479; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1480; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1481; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1482; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1483; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1484; GCN-IR-NEXT:    v_cndmask_b32_e32 v10, v5, v4, vcc
1485; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1486; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v10
1487; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1488; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1489; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1490; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1491; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1492; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1493; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, 24, 0, s[4:5]
1494; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1495; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1496; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1497; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1498; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1499; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1500; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1501; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v4
1502; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v5, vcc
1503; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[6:7], v[4:5]
1504; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1505; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1506; GCN-IR-NEXT:    v_lshl_b64 v[4:5], 24, v4
1507; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1508; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1509; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1510; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1511; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1512; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1513; GCN-IR-NEXT:    v_lshr_b64 v[12:13], 24, v6
1514; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v0
1515; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v1, vcc
1516; GCN-IR-NEXT:    v_sub_i32_e32 v10, vcc, 58, v10
1517; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
1518; GCN-IR-NEXT:    v_subb_u32_e32 v11, vcc, 0, v11, vcc
1519; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
1520; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1521; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1522; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
1523; GCN-IR-NEXT:    v_lshrrev_b32_e32 v8, 31, v5
1524; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v8
1525; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1526; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, v6, v12
1527; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v7, v13, vcc
1528; GCN-IR-NEXT:    v_or_b32_e32 v4, v14, v4
1529; GCN-IR-NEXT:    v_ashrrev_i32_e32 v14, 31, v8
1530; GCN-IR-NEXT:    v_and_b32_e32 v17, v14, v0
1531; GCN-IR-NEXT:    v_and_b32_e32 v8, 1, v14
1532; GCN-IR-NEXT:    v_and_b32_e32 v16, v14, v1
1533; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v10
1534; GCN-IR-NEXT:    v_or_b32_e32 v5, v15, v5
1535; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
1536; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11]
1537; GCN-IR-NEXT:    v_mov_b32_e32 v10, v14
1538; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1539; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v17
1540; GCN-IR-NEXT:    v_mov_b32_e32 v11, v15
1541; GCN-IR-NEXT:    v_mov_b32_e32 v15, v9
1542; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5]
1543; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1544; GCN-IR-NEXT:    v_mov_b32_e32 v14, v8
1545; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1546; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1547; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1548; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1549; GCN-IR-NEXT:  BB11_5: ; %Flow3
1550; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1551; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1552; GCN-IR-NEXT:    v_or_b32_e32 v7, v9, v1
1553; GCN-IR-NEXT:    v_or_b32_e32 v6, v8, v0
1554; GCN-IR-NEXT:  BB11_6: ; %Flow4
1555; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1556; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1557; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1558; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1559; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1560; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1561  %result = sdiv i64 24, %x
1562  ret i64 %result
1563}
1564
1565define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1566; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1567; GCN:       ; %bb.0:
1568; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1569; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1570; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1571; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1572; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1573; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1574; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v0
1575; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v1
1576; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v0
1577; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v1, vcc
1578; GCN-NEXT:    v_mov_b32_e32 v13, 0
1579; GCN-NEXT:    v_mac_f32_e32 v3, 0x4f800000, v4
1580; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1581; GCN-NEXT:    v_mov_b32_e32 v12, 0
1582; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
1583; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
1584; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1585; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
1586; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1587; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
1588; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
1589; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
1590; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
1591; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1592; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
1593; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
1594; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1595; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
1596; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
1597; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
1598; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1599; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1600; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
1601; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1602; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
1603; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
1604; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
1605; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
1606; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1607; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
1608; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
1609; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
1610; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
1611; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
1612; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
1613; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
1614; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1615; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
1616; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
1617; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
1618; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
1619; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
1620; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
1621; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
1622; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
1623; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
1624; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
1625; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
1626; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
1627; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
1628; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1629; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
1630; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
1631; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
1632; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1633; GCN-NEXT:    s_mov_b32 s4, 0x8000
1634; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
1635; GCN-NEXT:    v_mul_hi_u32 v5, s4, v3
1636; GCN-NEXT:    v_mul_hi_u32 v6, s4, v4
1637; GCN-NEXT:    v_lshlrev_b32_e32 v7, 15, v4
1638; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1639; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1640; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
1641; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v6, vcc
1642; GCN-NEXT:    v_add_i32_e32 v5, vcc, 0, v5
1643; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v3, vcc
1644; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
1645; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
1646; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1647; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
1648; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1649; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1650; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1651; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
1652; GCN-NEXT:    v_sub_i32_e32 v6, vcc, s4, v6
1653; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
1654; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
1655; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
1656; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
1657; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
1658; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
1659; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1660; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
1661; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
1662; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
1663; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
1664; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
1665; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
1666; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
1667; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1668; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
1669; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
1670; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
1671; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
1672; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1673; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
1674; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
1675; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1676; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
1677; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
1678; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1679; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
1680; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
1681; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1682; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
1683; GCN-NEXT:    s_setpc_b64 s[30:31]
1684;
1685; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1686; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1687; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1688; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1689; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1690; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1691; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1692; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
1693; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1694; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
1695; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
1696; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1697; GCN-IR-NEXT:    v_cndmask_b32_e32 v10, v5, v4, vcc
1698; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1699; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v10
1700; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1701; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1702; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1703; GCN-IR-NEXT:    s_mov_b32 s8, 0x8000
1704; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1705; GCN-IR-NEXT:    v_mov_b32_e32 v6, s8
1706; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1707; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1708; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[4:5]
1709; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1710; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1711; GCN-IR-NEXT:    s_mov_b32 s9, 0
1712; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1713; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1714; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1715; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1716; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1717; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v4
1718; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v5, vcc
1719; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[6:7], v[4:5]
1720; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1721; GCN-IR-NEXT:    v_lshl_b64 v[4:5], s[8:9], v4
1722; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1723; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1724; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1725; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1726; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1727; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1728; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1729; GCN-IR-NEXT:    s_mov_b32 s5, 0
1730; GCN-IR-NEXT:    s_mov_b32 s4, 0x8000
1731; GCN-IR-NEXT:    v_lshr_b64 v[12:13], s[4:5], v6
1732; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v0
1733; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v1, vcc
1734; GCN-IR-NEXT:    v_sub_i32_e32 v10, vcc, 47, v10
1735; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
1736; GCN-IR-NEXT:    v_subb_u32_e32 v11, vcc, 0, v11, vcc
1737; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
1738; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1739; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1740; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
1741; GCN-IR-NEXT:    v_lshrrev_b32_e32 v8, 31, v5
1742; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v8
1743; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1744; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, v6, v12
1745; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v7, v13, vcc
1746; GCN-IR-NEXT:    v_or_b32_e32 v4, v14, v4
1747; GCN-IR-NEXT:    v_ashrrev_i32_e32 v14, 31, v8
1748; GCN-IR-NEXT:    v_and_b32_e32 v17, v14, v0
1749; GCN-IR-NEXT:    v_and_b32_e32 v8, 1, v14
1750; GCN-IR-NEXT:    v_and_b32_e32 v16, v14, v1
1751; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v10
1752; GCN-IR-NEXT:    v_or_b32_e32 v5, v15, v5
1753; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
1754; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11]
1755; GCN-IR-NEXT:    v_mov_b32_e32 v10, v14
1756; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1757; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v17
1758; GCN-IR-NEXT:    v_mov_b32_e32 v11, v15
1759; GCN-IR-NEXT:    v_mov_b32_e32 v15, v9
1760; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5]
1761; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1762; GCN-IR-NEXT:    v_mov_b32_e32 v14, v8
1763; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1764; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1765; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1766; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1767; GCN-IR-NEXT:  BB12_5: ; %Flow3
1768; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1769; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
1770; GCN-IR-NEXT:    v_or_b32_e32 v7, v9, v1
1771; GCN-IR-NEXT:    v_or_b32_e32 v6, v8, v0
1772; GCN-IR-NEXT:  BB12_6: ; %Flow4
1773; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1774; GCN-IR-NEXT:    v_xor_b32_e32 v0, v6, v2
1775; GCN-IR-NEXT:    v_xor_b32_e32 v1, v7, v3
1776; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1777; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1778; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1779  %result = sdiv i64 32768, %x
1780  ret i64 %result
1781}
1782
1783define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1784; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1785; GCN:       ; %bb.0:
1786; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1787; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1788; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1789; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1790; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1791; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
1792; GCN-NEXT:    s_setpc_b64 s[30:31]
1793;
1794; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1795; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1796; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1797; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1798; GCN-IR-NEXT:    v_xor_b32_e32 v0, v2, v0
1799; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v0, v2
1800; GCN-IR-NEXT:    v_ffbh_u32_e32 v0, v7
1801; GCN-IR-NEXT:    v_xor_b32_e32 v1, v2, v1
1802; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v1, v2, vcc
1803; GCN-IR-NEXT:    v_add_i32_e64 v0, s[4:5], 32, v0
1804; GCN-IR-NEXT:    v_ffbh_u32_e32 v1, v8
1805; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
1806; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v1, v0, s[4:5]
1807; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 48, v0
1808; GCN-IR-NEXT:    v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1809; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1810; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1811; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1812; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1813; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1814; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1815; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1816; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1817; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1818; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1819; GCN-IR-NEXT:    s_cbranch_execz BB13_6
1820; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1821; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
1822; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
1823; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4]
1824; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v3
1825; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1826; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[7:8], v3
1827; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1828; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1829; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1830; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1831; GCN-IR-NEXT:    s_cbranch_execz BB13_5
1832; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1833; GCN-IR-NEXT:    v_lshr_b64 v[9:10], v[7:8], v9
1834; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1835; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1836; GCN-IR-NEXT:    v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1837; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1838; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1839; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
1840; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1841; GCN-IR-NEXT:    v_lshl_b64 v[9:10], v[9:10], 1
1842; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 31, v4
1843; GCN-IR-NEXT:    v_or_b32_e32 v0, v9, v0
1844; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1845; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, s12, v0
1846; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v10, vcc
1847; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1848; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
1849; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
1850; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1851; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
1852; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
1853; GCN-IR-NEXT:    v_and_b32_e32 v5, 1, v9
1854; GCN-IR-NEXT:    v_and_b32_e32 v9, 0x8000, v9
1855; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1856; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1857; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1858; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1859; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1860; GCN-IR-NEXT:    v_sub_i32_e64 v9, s[4:5], v0, v9
1861; GCN-IR-NEXT:    v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5]
1862; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1863; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1864; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1865; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
1866; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1867; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1868; GCN-IR-NEXT:  BB13_5: ; %Flow3
1869; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1870; GCN-IR-NEXT:    v_lshl_b64 v[3:4], v[3:4], 1
1871; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1872; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1873; GCN-IR-NEXT:  BB13_6: ; %Flow4
1874; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1875; GCN-IR-NEXT:    v_xor_b32_e32 v0, v5, v2
1876; GCN-IR-NEXT:    v_xor_b32_e32 v3, v6, v1
1877; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1878; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
1879; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1880  %result = sdiv i64 %x, 32768
1881  ret i64 %result
1882}
1883
1884define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1885; GCN-LABEL: s_test_sdiv24_k_num_i64:
1886; GCN:       ; %bb.0:
1887; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1888; GCN-NEXT:    s_mov_b32 s3, 0xf000
1889; GCN-NEXT:    s_mov_b32 s2, -1
1890; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1891; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1892; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
1893; GCN-NEXT:    s_mov_b32 s7, 0x41c00000
1894; GCN-NEXT:    s_mov_b32 s0, s4
1895; GCN-NEXT:    s_ashr_i32 s4, s6, 30
1896; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1897; GCN-NEXT:    s_or_b32 s4, s4, 1
1898; GCN-NEXT:    v_mov_b32_e32 v3, s4
1899; GCN-NEXT:    s_mov_b32 s1, s5
1900; GCN-NEXT:    v_mul_f32_e32 v1, s7, v1
1901; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1902; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s7
1903; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1904; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1905; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1906; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1907; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1908; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1909; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1910; GCN-NEXT:    s_endpgm
1911;
1912; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1913; GCN-IR:       ; %bb.0:
1914; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1915; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1916; GCN-IR-NEXT:    s_mov_b32 s2, -1
1917; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1918; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1919; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
1920; GCN-IR-NEXT:    s_mov_b32 s7, 0x41c00000
1921; GCN-IR-NEXT:    s_mov_b32 s0, s4
1922; GCN-IR-NEXT:    s_ashr_i32 s4, s6, 30
1923; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1924; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
1925; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
1926; GCN-IR-NEXT:    s_mov_b32 s1, s5
1927; GCN-IR-NEXT:    v_mul_f32_e32 v1, s7, v1
1928; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1929; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s7
1930; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1931; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1932; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1933; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1934; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1935; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1936; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1937; GCN-IR-NEXT:    s_endpgm
1938  %x.shr = ashr i64 %x, 40
1939  %result = sdiv i64 24, %x.shr
1940  store i64 %result, i64 addrspace(1)* %out
1941  ret void
1942}
1943
1944define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1945; GCN-LABEL: s_test_sdiv24_k_den_i64:
1946; GCN:       ; %bb.0:
1947; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1948; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
1949; GCN-NEXT:    s_mov_b32 s3, 0xf000
1950; GCN-NEXT:    s_mov_b32 s2, -1
1951; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1952; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1953; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
1954; GCN-NEXT:    s_mov_b32 s0, s4
1955; GCN-NEXT:    s_ashr_i32 s4, s6, 30
1956; GCN-NEXT:    s_or_b32 s4, s4, 1
1957; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1958; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1959; GCN-NEXT:    v_mad_f32 v0, -v1, s8, v0
1960; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1961; GCN-NEXT:    v_mov_b32_e32 v2, s4
1962; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1963; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1964; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1965; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1966; GCN-NEXT:    s_mov_b32 s1, s5
1967; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1968; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1969; GCN-NEXT:    s_endpgm
1970;
1971; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1972; GCN-IR:       ; %bb.0:
1973; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1974; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
1975; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1976; GCN-IR-NEXT:    s_mov_b32 s2, -1
1977; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1978; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
1979; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
1980; GCN-IR-NEXT:    s_mov_b32 s0, s4
1981; GCN-IR-NEXT:    s_ashr_i32 s4, s6, 30
1982; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
1983; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1984; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1985; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s8, v0
1986; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
1987; GCN-IR-NEXT:    v_mov_b32_e32 v2, s4
1988; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
1989; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
1990; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1991; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
1992; GCN-IR-NEXT:    s_mov_b32 s1, s5
1993; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1994; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1995; GCN-IR-NEXT:    s_endpgm
1996  %x.shr = ashr i64 %x, 40
1997  %result = sdiv i64 %x.shr, 23423
1998  store i64 %result, i64 addrspace(1)* %out
1999  ret void
2000}
2001
2002define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
2003; GCN-LABEL: v_test_sdiv24_k_num_i64:
2004; GCN:       ; %bb.0:
2005; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2006; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2007; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2008; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2009; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2010; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
2011; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2012; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2013; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2014; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
2015; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2016; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2017; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2018; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2019; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2020; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2021; GCN-NEXT:    s_setpc_b64 s[30:31]
2022;
2023; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
2024; GCN-IR:       ; %bb.0:
2025; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2026; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2027; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2028; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2029; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2030; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2031; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2032; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2033; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2034; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2035; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2036; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2037; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2038; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2039; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2040; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2041; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2042  %x.shr = ashr i64 %x, 40
2043  %result = sdiv i64 24, %x.shr
2044  ret i64 %result
2045}
2046
2047define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
2048; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
2049; GCN:       ; %bb.0:
2050; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2051; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2052; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2053; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2054; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2055; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
2056; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2057; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2058; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2059; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
2060; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2061; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2062; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2063; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2064; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2065; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2066; GCN-NEXT:    s_setpc_b64 s[30:31]
2067;
2068; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
2069; GCN-IR:       ; %bb.0:
2070; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2071; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2072; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2073; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2074; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2075; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2076; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2077; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2078; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2079; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
2080; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2081; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
2082; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2083; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2084; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2085; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2086; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2087  %x.shr = ashr i64 %x, 40
2088  %result = sdiv i64 32768, %x.shr
2089  ret i64 %result
2090}
2091
2092define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
2093; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
2094; GCN:       ; %bb.0:
2095; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2096; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2097; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2098; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2099; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
2100; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 15
2101; GCN-NEXT:    s_setpc_b64 s[30:31]
2102;
2103; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
2104; GCN-IR:       ; %bb.0:
2105; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2106; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2107; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2108; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2109; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
2110; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
2111; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
2112; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2113; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
2114; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2115; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2116; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
2117; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
2118; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2119; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2120; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2121  %x.shr = ashr i64 %x, 40
2122  %result = sdiv i64 %x.shr, 32768
2123  ret i64 %result
2124}
2125