1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=machine-scheduler -o - %s | FileCheck %s 3 4--- 5# Check that the high latency loads are both scheduled first, before the 6# multiplies, despite the presence of a barrier in the function. 7name: test 8tracksRegLiveness: true 9body: | 10 bb.0: 11 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 12 13 ; CHECK-LABEL: name: test 14 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 15 ; CHECK-NEXT: {{ $}} 16 ; CHECK-NEXT: undef %0.sub3:vreg_128 = COPY $vgpr9 17 ; CHECK-NEXT: undef %1.sub2:vreg_128 = COPY $vgpr8 18 ; CHECK-NEXT: undef %2.sub1:vreg_128 = COPY $vgpr7 19 ; CHECK-NEXT: undef %8.sub1:vreg_64 = COPY $vgpr1 20 ; CHECK-NEXT: %8.sub0:vreg_64 = COPY $vgpr0 21 ; CHECK-NEXT: undef %3.sub0:vreg_128 = COPY $vgpr6 22 ; CHECK-NEXT: undef %4.sub3:vreg_128 = COPY $vgpr5 23 ; CHECK-NEXT: undef %5.sub2:vreg_128 = COPY $vgpr4 24 ; CHECK-NEXT: undef %6.sub1:vreg_128 = COPY $vgpr3 25 ; CHECK-NEXT: undef %7.sub0:vreg_128 = COPY $vgpr2 26 ; CHECK-NEXT: undef %9.sub0:sgpr_128 = V_READFIRSTLANE_B32 %7.sub0, implicit $exec 27 ; CHECK-NEXT: %9.sub1:sgpr_128 = V_READFIRSTLANE_B32 %6.sub1, implicit $exec 28 ; CHECK-NEXT: %9.sub2:sgpr_128 = V_READFIRSTLANE_B32 %5.sub2, implicit $exec 29 ; CHECK-NEXT: %9.sub3:sgpr_128 = V_READFIRSTLANE_B32 %4.sub3, implicit $exec 30 ; CHECK-NEXT: S_BARRIER 31 ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %9, 0, 0, 0, 0, 0, implicit $exec 32 ; CHECK-NEXT: undef %12.sub0:sgpr_128 = V_READFIRSTLANE_B32 %3.sub0, implicit $exec 33 ; CHECK-NEXT: %12.sub1:sgpr_128 = V_READFIRSTLANE_B32 %2.sub1, implicit $exec 34 ; CHECK-NEXT: %12.sub2:sgpr_128 = V_READFIRSTLANE_B32 %1.sub2, implicit $exec 35 ; CHECK-NEXT: %12.sub3:sgpr_128 = V_READFIRSTLANE_B32 %0.sub3, implicit $exec 36 ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %12, 0, 0, 0, 0, 0, implicit $exec 37 ; CHECK-NEXT: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 [[BUFFER_LOAD_DWORD_OFFSET]], [[BUFFER_LOAD_DWORD_OFFSET]], implicit $exec 38 ; CHECK-NEXT: [[V_MUL_LO_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 [[BUFFER_LOAD_DWORD_OFFSET1]], [[BUFFER_LOAD_DWORD_OFFSET1]], implicit $exec 39 ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MUL_LO_U32_e64_]], [[V_MUL_LO_U32_e64_1]], implicit $exec 40 ; CHECK-NEXT: GLOBAL_STORE_DWORD %8, [[V_ADD_U32_e32_]], 0, 0, implicit $exec 41 ; CHECK-NEXT: S_ENDPGM 0 42 undef %43.sub3:vreg_128 = COPY $vgpr9 43 undef %42.sub2:vreg_128 = COPY $vgpr8 44 undef %41.sub1:vreg_128 = COPY $vgpr7 45 undef %26.sub0:vreg_128 = COPY $vgpr6 46 undef %46.sub3:vreg_128 = COPY $vgpr5 47 undef %45.sub2:vreg_128 = COPY $vgpr4 48 undef %44.sub1:vreg_128 = COPY $vgpr3 49 undef %32.sub0:vreg_128 = COPY $vgpr2 50 undef %38.sub1:vreg_64 = COPY $vgpr1 51 %38.sub0:vreg_64 = COPY $vgpr0 52 53 S_BARRIER 54 55 undef %33.sub0:sgpr_128 = V_READFIRSTLANE_B32 %32.sub0, implicit $exec 56 %33.sub1:sgpr_128 = V_READFIRSTLANE_B32 %44.sub1, implicit $exec 57 %33.sub2:sgpr_128 = V_READFIRSTLANE_B32 %45.sub2, implicit $exec 58 %33.sub3:sgpr_128 = V_READFIRSTLANE_B32 %46.sub3, implicit $exec 59 %15:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %33, 0, 0, 0, 0, 0, implicit $exec 60 %39:vgpr_32 = V_MUL_LO_U32_e64 %15, %15, implicit $exec 61 62 undef %27.sub0:sgpr_128 = V_READFIRSTLANE_B32 %26.sub0, implicit $exec 63 %27.sub1:sgpr_128 = V_READFIRSTLANE_B32 %41.sub1, implicit $exec 64 %27.sub2:sgpr_128 = V_READFIRSTLANE_B32 %42.sub2, implicit $exec 65 %27.sub3:sgpr_128 = V_READFIRSTLANE_B32 %43.sub3, implicit $exec 66 %19:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %27, 0, 0, 0, 0, 0, implicit $exec 67 %40:vgpr_32 = V_MUL_LO_U32_e64 %19, %19, implicit $exec 68 69 %23:vgpr_32 = V_ADD_U32_e32 %39, %40, implicit $exec 70 GLOBAL_STORE_DWORD %38, %23, 0, 0, implicit $exec 71 S_ENDPGM 0 72... 73