1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s 3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s 4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s 5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s 6 7define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) { 8; GFX6-LABEL: v_saddsat_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8 12; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 13; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 14; GFX6-NEXT: v_min_i32_e32 v0, 0x7f, v0 15; GFX6-NEXT: v_max_i32_e32 v0, 0xffffff80, v0 16; GFX6-NEXT: s_setpc_b64 s[30:31] 17; 18; GFX8-LABEL: v_saddsat_i8: 19; GFX8: ; %bb.0: 20; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 21; GFX8-NEXT: v_add_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 22; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0 23; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v0 24; GFX8-NEXT: s_setpc_b64 s[30:31] 25; 26; GFX9-LABEL: v_saddsat_i8: 27; GFX9: ; %bb.0: 28; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 29; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 30; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 31; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp 32; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 33; GFX9-NEXT: s_setpc_b64 s[30:31] 34; 35; GFX10-LABEL: v_saddsat_i8: 36; GFX10: ; %bb.0: 37; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 38; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 39; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 40; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0 41; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp 42; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0 43; GFX10-NEXT: s_setpc_b64 s[30:31] 44 %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs) 45 ret i8 %result 46} 47 48define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) { 49; GFX6-LABEL: v_saddsat_i16: 50; GFX6: ; %bb.0: 51; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 52; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 53; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 54; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 55; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 56; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 57; GFX6-NEXT: s_setpc_b64 s[30:31] 58; 59; GFX8-LABEL: v_saddsat_i16: 60; GFX8: ; %bb.0: 61; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 62; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1 63; GFX8-NEXT: v_add_u16_e32 v1, v0, v1 64; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 65; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1 66; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 67; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 68; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 69; GFX8-NEXT: s_setpc_b64 s[30:31] 70; 71; GFX9-LABEL: v_saddsat_i16: 72; GFX9: ; %bb.0: 73; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 74; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp 75; GFX9-NEXT: s_setpc_b64 s[30:31] 76; 77; GFX10-LABEL: v_saddsat_i16: 78; GFX10: ; %bb.0: 79; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 80; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 81; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp 82; GFX10-NEXT: s_setpc_b64 s[30:31] 83 %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) 84 ret i16 %result 85} 86 87define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) { 88; GFX6-LABEL: v_saddsat_i32: 89; GFX6: ; %bb.0: 90; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 91; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1 92; GFX6-NEXT: v_add_i32_e64 v1, s[4:5], v0, v1 93; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 94; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v1 95; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 96; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 97; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 98; GFX6-NEXT: s_setpc_b64 s[30:31] 99; 100; GFX8-LABEL: v_saddsat_i32: 101; GFX8: ; %bb.0: 102; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 103; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1 104; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v0, v1 105; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 106; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v1 107; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 108; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 109; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 110; GFX8-NEXT: s_setpc_b64 s[30:31] 111; 112; GFX9-LABEL: v_saddsat_i32: 113; GFX9: ; %bb.0: 114; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 115; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp 116; GFX9-NEXT: s_setpc_b64 s[30:31] 117; 118; GFX10-LABEL: v_saddsat_i32: 119; GFX10: ; %bb.0: 120; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 121; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 122; GFX10-NEXT: v_add_nc_i32 v0, v0, v1 clamp 123; GFX10-NEXT: s_setpc_b64 s[30:31] 124 %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) 125 ret i32 %result 126} 127 128define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { 129; GFX6-LABEL: v_saddsat_v2i16: 130; GFX6: ; %bb.0: 131; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 132; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 133; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 134; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 135; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 136; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 137; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 138; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 139; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 140; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 141; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 142; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 143; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 144; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 145; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 146; GFX6-NEXT: s_setpc_b64 s[30:31] 147; 148; GFX8-LABEL: v_saddsat_v2i16: 149; GFX8: ; %bb.0: 150; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 151; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1 152; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0 153; GFX8-NEXT: v_add_u16_e32 v4, v3, v2 154; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3 155; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2 156; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v4 157; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2 158; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 159; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc 160; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1 161; GFX8-NEXT: v_add_u16_e32 v1, v0, v1 162; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 163; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1 164; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 165; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 166; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 167; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 168; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 169; GFX8-NEXT: s_setpc_b64 s[30:31] 170; 171; GFX9-LABEL: v_saddsat_v2i16: 172; GFX9: ; %bb.0: 173; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 174; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp 175; GFX9-NEXT: s_setpc_b64 s[30:31] 176; 177; GFX10-LABEL: v_saddsat_v2i16: 178; GFX10: ; %bb.0: 179; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 180; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 181; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp 182; GFX10-NEXT: s_setpc_b64 s[30:31] 183 %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) 184 ret <2 x i16> %result 185} 186 187define <3 x i16> @v_saddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { 188; GFX6-LABEL: v_saddsat_v3i16: 189; GFX6: ; %bb.0: 190; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 191; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 192; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 193; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 194; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 195; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 196; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 197; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4 198; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3 199; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 200; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 201; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 202; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 203; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 204; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2 205; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 206; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 207; GFX6-NEXT: v_max_i32_e32 v3, 0xffff8000, v2 208; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 209; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v3 210; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16 211; GFX6-NEXT: s_setpc_b64 s[30:31] 212; 213; GFX8-LABEL: v_saddsat_v3i16: 214; GFX8: ; %bb.0: 215; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 216; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 217; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 218; GFX8-NEXT: v_add_u16_e32 v6, v5, v4 219; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 220; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4 221; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6 222; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4 223; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 224; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc 225; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3 226; GFX8-NEXT: v_add_u16_e32 v3, v1, v3 227; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 228; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3 229; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 230; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 231; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 232; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2 233; GFX8-NEXT: v_add_u16_e32 v2, v0, v2 234; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 235; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2 236; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 237; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 238; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 239; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 240; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 241; GFX8-NEXT: s_setpc_b64 s[30:31] 242; 243; GFX9-LABEL: v_saddsat_v3i16: 244; GFX9: ; %bb.0: 245; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 246; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp 247; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp 248; GFX9-NEXT: s_setpc_b64 s[30:31] 249; 250; GFX10-LABEL: v_saddsat_v3i16: 251; GFX10: ; %bb.0: 252; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 253; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 254; GFX10-NEXT: v_pk_add_i16 v0, v0, v2 clamp 255; GFX10-NEXT: v_pk_add_i16 v1, v1, v3 clamp 256; GFX10-NEXT: s_setpc_b64 s[30:31] 257 %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs) 258 ret <3 x i16> %result 259} 260 261define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 262; GFX6-LABEL: v_saddsat_v4i16: 263; GFX6: ; %bb.0: 264; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 265; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 266; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 267; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 268; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 269; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5 270; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4 271; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 272; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 273; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 274; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 275; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16 276; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 277; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16 278; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 279; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 280; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 281; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 282; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v7 283; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6 284; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 285; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2 286; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 287; GFX6-NEXT: v_max_i32_e32 v2, 0xffff8000, v2 288; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 289; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 290; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 291; GFX6-NEXT: s_setpc_b64 s[30:31] 292; 293; GFX8-LABEL: v_saddsat_v4i16: 294; GFX8: ; %bb.0: 295; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 296; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 297; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 298; GFX8-NEXT: v_add_u16_e32 v6, v5, v4 299; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 300; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4 301; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6 302; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4 303; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 304; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc 305; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2 306; GFX8-NEXT: v_add_u16_e32 v2, v0, v2 307; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 308; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2 309; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 310; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 311; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 312; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 313; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 314; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3 315; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 316; GFX8-NEXT: v_add_u16_e32 v5, v4, v2 317; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4 318; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2 319; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v5 320; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2 321; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 322; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc 323; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3 324; GFX8-NEXT: v_add_u16_e32 v3, v1, v3 325; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 326; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3 327; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 328; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 329; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 330; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 331; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 332; GFX8-NEXT: s_setpc_b64 s[30:31] 333; 334; GFX9-LABEL: v_saddsat_v4i16: 335; GFX9: ; %bb.0: 336; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 337; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp 338; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp 339; GFX9-NEXT: s_setpc_b64 s[30:31] 340; 341; GFX10-LABEL: v_saddsat_v4i16: 342; GFX10: ; %bb.0: 343; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 344; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 345; GFX10-NEXT: v_pk_add_i16 v0, v0, v2 clamp 346; GFX10-NEXT: v_pk_add_i16 v1, v1, v3 clamp 347; GFX10-NEXT: s_setpc_b64 s[30:31] 348 %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 349 %cast = bitcast <4 x i16> %result to <2 x float> 350 ret <2 x float> %cast 351} 352 353define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 354; GFX6-LABEL: v_saddsat_v2i32: 355; GFX6: ; %bb.0: 356; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 357; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2 358; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v0, v2 359; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 360; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2 361; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 362; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 363; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 364; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v1, v3 365; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 366; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 367; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2 368; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 369; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 370; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc 371; GFX6-NEXT: s_setpc_b64 s[30:31] 372; 373; GFX8-LABEL: v_saddsat_v2i32: 374; GFX8: ; %bb.0: 375; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 376; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2 377; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v0, v2 378; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 379; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2 380; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 381; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 382; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 383; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v1, v3 384; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 385; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 386; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2 387; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 388; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 389; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc 390; GFX8-NEXT: s_setpc_b64 s[30:31] 391; 392; GFX9-LABEL: v_saddsat_v2i32: 393; GFX9: ; %bb.0: 394; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 395; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp 396; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp 397; GFX9-NEXT: s_setpc_b64 s[30:31] 398; 399; GFX10-LABEL: v_saddsat_v2i32: 400; GFX10: ; %bb.0: 401; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 402; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 403; GFX10-NEXT: v_add_nc_i32 v0, v0, v2 clamp 404; GFX10-NEXT: v_add_nc_i32 v1, v1, v3 clamp 405; GFX10-NEXT: s_setpc_b64 s[30:31] 406 %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 407 ret <2 x i32> %result 408} 409 410define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) { 411; GFX6-LABEL: v_saddsat_i64: 412; GFX6: ; %bb.0: 413; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 414; GFX6-NEXT: v_add_i32_e32 v4, vcc, v0, v2 415; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc 416; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 417; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3] 418; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v5 419; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc 420; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc 421; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 422; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 423; GFX6-NEXT: s_setpc_b64 s[30:31] 424; 425; GFX8-LABEL: v_saddsat_i64: 426; GFX8: ; %bb.0: 427; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 428; GFX8-NEXT: v_add_u32_e32 v4, vcc, v0, v2 429; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc 430; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 431; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3] 432; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v5 433; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 434; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc 435; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 436; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 437; GFX8-NEXT: s_setpc_b64 s[30:31] 438; 439; GFX9-LABEL: v_saddsat_i64: 440; GFX9: ; %bb.0: 441; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 442; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2 443; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc 444; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 445; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3] 446; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v5 447; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc 448; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc 449; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 450; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 451; GFX9-NEXT: s_setpc_b64 s[30:31] 452; 453; GFX10-LABEL: v_saddsat_i64: 454; GFX10: ; %bb.0: 455; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 456; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 457; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 458; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo 459; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[2:3] 460; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 461; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] 462; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 463; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo 464; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo 465; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo 466; GFX10-NEXT: s_setpc_b64 s[30:31] 467 %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs) 468 ret i64 %result 469} 470 471declare i8 @llvm.sadd.sat.i8(i8, i8) #0 472declare i16 @llvm.sadd.sat.i16(i16, i16) #0 473declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>) #0 474declare <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16>, <3 x i16>) #0 475declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>) #0 476declare i32 @llvm.sadd.sat.i32(i32, i32) #0 477declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>) #0 478declare i64 @llvm.sadd.sat.i64(i64, i64) #0 479