1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 3; GCN-LABEL: {{^}}v_sad_u32_pat1: 4; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 5define amdgpu_kernel void @v_sad_u32_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 6 %icmp0 = icmp ugt i32 %a, %b 7 %t0 = select i1 %icmp0, i32 %a, i32 %b 8 9 %icmp1 = icmp ule i32 %a, %b 10 %t1 = select i1 %icmp1, i32 %a, i32 %b 11 12 %ret0 = sub i32 %t0, %t1 13 %ret = add i32 %ret0, %c 14 15 store i32 %ret, i32 addrspace(1)* %out 16 ret void 17} 18 19; GCN-LABEL: {{^}}v_sad_u32_constant_pat1: 20; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 20 21define amdgpu_kernel void @v_sad_u32_constant_pat1(i32 addrspace(1)* %out, i32 %a) { 22 %icmp0 = icmp ugt i32 %a, 90 23 %t0 = select i1 %icmp0, i32 %a, i32 90 24 25 %icmp1 = icmp ule i32 %a, 90 26 %t1 = select i1 %icmp1, i32 %a, i32 90 27 28 %ret0 = sub i32 %t0, %t1 29 %ret = add i32 %ret0, 20 30 31 store i32 %ret, i32 addrspace(1)* %out 32 ret void 33} 34 35; GCN-LABEL: {{^}}v_sad_u32_pat2: 36; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 37define amdgpu_kernel void @v_sad_u32_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 38 %icmp0 = icmp ugt i32 %a, %b 39 %sub0 = sub i32 %a, %b 40 %sub1 = sub i32 %b, %a 41 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 42 43 %ret = add i32 %ret0, %c 44 45 store i32 %ret, i32 addrspace(1)* %out 46 ret void 47} 48 49; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat1: 50; GCN: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 51; GCN: s_min_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 52; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 53; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 54define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 55 %icmp0 = icmp ugt i32 %a, %b 56 %t0 = select i1 %icmp0, i32 %a, i32 %b 57 58 %icmp1 = icmp ule i32 %a, %b 59 %t1 = select i1 %icmp1, i32 %a, i32 %b 60 61 %ret0 = sub i32 %t0, %t1 62 store volatile i32 %ret0, i32 addrspace(5)*undef 63 %ret = add i32 %ret0, %c 64 65 store i32 %ret, i32 addrspace(1)* %out 66 ret void 67} 68 69; GCN-LABEL: {{^}}v_sad_u32_multi_use_add_pat1: 70; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 71define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 72 %icmp0 = icmp ugt i32 %a, %b 73 %t0 = select i1 %icmp0, i32 %a, i32 %b 74 75 %icmp1 = icmp ule i32 %a, %b 76 %t1 = select i1 %icmp1, i32 %a, i32 %b 77 78 %ret0 = sub i32 %t0, %t1 79 %ret = add i32 %ret0, %c 80 store volatile i32 %ret, i32 addrspace(5)*undef 81 store i32 %ret, i32 addrspace(1)* %out 82 ret void 83} 84 85; GCN-LABEL: {{^}}v_sad_u32_multi_use_max_pat1: 86; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 87define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 88 %icmp0 = icmp ugt i32 %a, %b 89 %t0 = select i1 %icmp0, i32 %a, i32 %b 90 store volatile i32 %t0, i32 addrspace(5)*undef 91 92 %icmp1 = icmp ule i32 %a, %b 93 %t1 = select i1 %icmp1, i32 %a, i32 %b 94 95 %ret0 = sub i32 %t0, %t1 96 %ret = add i32 %ret0, %c 97 98 store i32 %ret, i32 addrspace(1)* %out 99 ret void 100} 101 102; GCN-LABEL: {{^}}v_sad_u32_multi_use_min_pat1: 103; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 104define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 105 %icmp0 = icmp ugt i32 %a, %b 106 %t0 = select i1 %icmp0, i32 %a, i32 %b 107 108 %icmp1 = icmp ule i32 %a, %b 109 %t1 = select i1 %icmp1, i32 %a, i32 %b 110 111 store volatile i32 %t1, i32 addrspace(5)*undef 112 113 %ret0 = sub i32 %t0, %t1 114 %ret = add i32 %ret0, %c 115 116 store i32 %ret, i32 addrspace(1)* %out 117 ret void 118} 119 120; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat2: 121; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 122define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 123 %icmp0 = icmp ugt i32 %a, %b 124 %sub0 = sub i32 %a, %b 125 store volatile i32 %sub0, i32 addrspace(5)*undef 126 %sub1 = sub i32 %b, %a 127 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 128 129 %ret = add i32 %ret0, %c 130 131 store i32 %ret, i32 addrspace(1)* %out 132 ret void 133} 134 135; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2: 136; GCN-DAG: s_cmp_gt_u32 s{{[0-9]+}}, s{{[0-9]+}} 137; GCN-DAG: s_cselect_b64 vcc, 1, 0 138; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 139; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 140define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 141 %icmp0 = icmp ugt i32 %a, %b 142 %sub0 = sub i32 %a, %b 143 %sub1 = sub i32 %b, %a 144 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 145 store volatile i32 %ret0, i32 addrspace(5)*undef 146 147 %ret = add i32 %ret0, %c 148 149 store i32 %ret, i32 addrspace(1)* %out 150 ret void 151} 152 153; GCN-LABEL: {{^}}v_sad_u32_vector_pat1: 154; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 155; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 156; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 157; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 158define amdgpu_kernel void @v_sad_u32_vector_pat1(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 159 %icmp0 = icmp ugt <4 x i32> %a, %b 160 %t0 = select <4 x i1> %icmp0, <4 x i32> %a, <4 x i32> %b 161 162 %icmp1 = icmp ule <4 x i32> %a, %b 163 %t1 = select <4 x i1> %icmp1, <4 x i32> %a, <4 x i32> %b 164 165 %ret0 = sub <4 x i32> %t0, %t1 166 %ret = add <4 x i32> %ret0, %c 167 168 store <4 x i32> %ret, <4 x i32> addrspace(1)* %out 169 ret void 170} 171 172; GCN-LABEL: {{^}}v_sad_u32_vector_pat2: 173; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 174; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 175; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 176; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 177define amdgpu_kernel void @v_sad_u32_vector_pat2(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 178 %icmp0 = icmp ugt <4 x i32> %a, %b 179 %sub0 = sub <4 x i32> %a, %b 180 %sub1 = sub <4 x i32> %b, %a 181 %ret0 = select <4 x i1> %icmp0, <4 x i32> %sub0, <4 x i32> %sub1 182 183 %ret = add <4 x i32> %ret0, %c 184 185 store <4 x i32> %ret, <4 x i32> addrspace(1)* %out 186 ret void 187} 188 189; GCN-LABEL: {{^}}v_sad_u32_i16_pat1: 190; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 191define amdgpu_kernel void @v_sad_u32_i16_pat1(i16 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { 192 193 %icmp0 = icmp ugt i16 %a, %b 194 %t0 = select i1 %icmp0, i16 %a, i16 %b 195 196 %icmp1 = icmp ule i16 %a, %b 197 %t1 = select i1 %icmp1, i16 %a, i16 %b 198 199 %ret0 = sub i16 %t0, %t1 200 %ret = add i16 %ret0, %c 201 202 store i16 %ret, i16 addrspace(1)* %out 203 ret void 204} 205 206; GCN-LABEL: {{^}}v_sad_u32_i16_pat2: 207; GCN: v_sad_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 208define amdgpu_kernel void @v_sad_u32_i16_pat2(i16 addrspace(1)* %out) { 209 %a = load volatile i16, i16 addrspace(1)* undef 210 %b = load volatile i16, i16 addrspace(1)* undef 211 %c = load volatile i16, i16 addrspace(1)* undef 212 %icmp0 = icmp ugt i16 %a, %b 213 %sub0 = sub i16 %a, %b 214 %sub1 = sub i16 %b, %a 215 %ret0 = select i1 %icmp0, i16 %sub0, i16 %sub1 216 217 %ret = add i16 %ret0, %c 218 219 store i16 %ret, i16 addrspace(1)* %out 220 ret void 221} 222 223; GCN-LABEL: {{^}}v_sad_u32_i8_pat1: 224; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 225define amdgpu_kernel void @v_sad_u32_i8_pat1(i8 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { 226 %icmp0 = icmp ugt i8 %a, %b 227 %t0 = select i1 %icmp0, i8 %a, i8 %b 228 229 %icmp1 = icmp ule i8 %a, %b 230 %t1 = select i1 %icmp1, i8 %a, i8 %b 231 232 %ret0 = sub i8 %t0, %t1 233 %ret = add i8 %ret0, %c 234 235 store i8 %ret, i8 addrspace(1)* %out 236 ret void 237} 238 239; GCN-LABEL: {{^}}v_sad_u32_i8_pat2: 240; GCN: v_sad_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 241define amdgpu_kernel void @v_sad_u32_i8_pat2(i8 addrspace(1)* %out) { 242 %a = load volatile i8, i8 addrspace(1)* undef 243 %b = load volatile i8, i8 addrspace(1)* undef 244 %c = load volatile i8, i8 addrspace(1)* undef 245 %icmp0 = icmp ugt i8 %a, %b 246 %sub0 = sub i8 %a, %b 247 %sub1 = sub i8 %b, %a 248 %ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1 249 250 %ret = add i8 %ret0, %c 251 252 store i8 %ret, i8 addrspace(1)* %out 253 ret void 254} 255 256; GCN-LABEL: {{^}}s_sad_u32_i8_pat2: 257; GCN: s_load_dword 258; GCN-DAG: s_bfe_u32 259; GCN-DAG: s_sub_i32 260; GCN-DAG: s_and_b32 261; GCN-DAG: s_sub_i32 262; GCN-DAG: s_lshr_b32 263; GCN: v_add_i32_e32 264define amdgpu_kernel void @s_sad_u32_i8_pat2(i8 addrspace(1)* %out, i8 zeroext %a, i8 zeroext %b, i8 zeroext %c) { 265 %icmp0 = icmp ugt i8 %a, %b 266 %sub0 = sub i8 %a, %b 267 %sub1 = sub i8 %b, %a 268 %ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1 269 270 %ret = add i8 %ret0, %c 271 272 store i8 %ret, i8 addrspace(1)* %out 273 ret void 274} 275 276; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat1: 277; GCN: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 278; GCN: s_cmp_le_u32 s{{[0-9]+}}, s{{[0-9]+}} 279; GCN: s_cselect_b64 vcc, 1, 0 280; GCN: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 281; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 282define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { 283 %icmp0 = icmp ugt i32 %a, %b 284 %t0 = select i1 %icmp0, i32 %a, i32 %b 285 286 %icmp1 = icmp ule i32 %a, %b 287 %t1 = select i1 %icmp1, i32 %a, i32 %d 288 289 %ret0 = sub i32 %t0, %t1 290 %ret = add i32 %ret0, %c 291 292 store i32 %ret, i32 addrspace(1)* %out 293 ret void 294} 295 296; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat2: 297; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 298; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 299; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} 300define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { 301 %icmp0 = icmp ugt i32 %a, %b 302 %sub0 = sub i32 %a, %d 303 %sub1 = sub i32 %b, %a 304 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 305 306 %ret = add i32 %ret0, %c 307 308 store i32 %ret, i32 addrspace(1)* %out 309 ret void 310} 311 312