1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4; This should end with an no-op sequence of exec mask manipulations
5; Mask should be in original state after executed unreachable block
6
7; GCN-LABEL: {{^}}main:
8; GCN: s_cbranch_vccnz [[RET_BB:BB[0-9]+_[0-9]+]]
9
10; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
11; GCN-NEXT: s_xor_b64 [[XOR_EXEC:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_EXEC]]
12; GCN-NEXT: ; mask branch [[UNREACHABLE_BB:BB[0-9]+_[0-9]+]]
13
14; GCN: [[RET_BB]]:
15; GCN-NEXT: ; return
16
17; GCN-NEXT: [[UNREACHABLE_BB]]:
18; GCN-NEXT: s_or_b64 exec, exec, [[XOR_EXEC]]
19; GCN-NEXT: .Lfunc_end0
20define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, i32 addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
21main_body:
22  %p83 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
23  %p87 = fmul float undef, %p83
24  %p88 = fadd float %p87, undef
25  %p93 = fadd float %p88, undef
26  %p97 = fmul float %p93, undef
27  %p102 = fsub float %p97, undef
28  %p104 = fmul float %p102, undef
29  %p106 = fadd float 0.000000e+00, %p104
30  %p108 = fadd float undef, %p106
31  br i1 undef, label %ENDIF69, label %ELSE
32
33ELSE:                                             ; preds = %main_body
34  %p124 = fmul float %p108, %p108
35  %p125 = fsub float %p124, undef
36  %p126 = fcmp olt float %p125, 0.000000e+00
37  br i1 %p126, label %ENDIF69, label %ELSE41
38
39ELSE41:                                           ; preds = %ELSE
40  unreachable
41
42ENDIF69:                                          ; preds = %ELSE, %main_body
43  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef
44}
45
46; Function Attrs: nounwind readnone
47declare float @llvm.SI.load.const(<16 x i8>, i32) #1
48
49; Function Attrs: nounwind readnone
50declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
51
52; Function Attrs: nounwind readnone
53declare float @llvm.fabs.f32(float) #1
54
55; Function Attrs: nounwind readnone
56declare float @llvm.sqrt.f32(float) #1
57
58; Function Attrs: nounwind readnone
59declare float @llvm.floor.f32(float) #1
60
61attributes #0 = { "InitialPSInputAddr"="36983" }
62attributes #1 = { nounwind readnone }
63