1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4attributes #0 = { "ShaderType"="1" }
5
6declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
7
8; GCN-LABEL: {{^}}vgpr:
9; GCN: v_mov_b32_e32 v1, v0
10; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
11; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1
12; GCN: s_waitcnt expcnt(0)
13; GCN-NOT: s_endpgm
14define {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
15  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
16  %x = fadd float %3, 1.0
17  %a = insertvalue {float, float} undef, float %x, 0
18  %b = insertvalue {float, float} %a, float %3, 1
19  ret {float, float} %b
20}
21
22; GCN-LABEL: {{^}}vgpr_literal:
23; GCN: v_mov_b32_e32 v4, v0
24; GCN-DAG: v_mov_b32_e32 v0, 1.0
25; GCN-DAG: v_mov_b32_e32 v1, 2.0
26; GCN-DAG: v_mov_b32_e32 v2, 4.0
27; GCN-DAG: v_mov_b32_e32 v3, -1.0
28; GCN: exp 15, 0, 1, 1, 1, v4, v4, v4, v4
29; GCN: s_waitcnt expcnt(0)
30; GCN-NOT: s_endpgm
31define {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
32  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
33  ret {float, float, float, float} {float 1.0, float 2.0, float 4.0, float -1.0}
34}
35
36
37; GCN: .long 165580
38; GCN-NEXT: .long 562
39; GCN-NEXT: .long 165584
40; GCN-NEXT: .long 562
41; GCN-LABEL: {{^}}vgpr_ps_addr0:
42; GCN-NOT: v_mov_b32_e32 v0
43; GCN-NOT: v_mov_b32_e32 v1
44; GCN-NOT: v_mov_b32_e32 v2
45; GCN: v_mov_b32_e32 v3, v4
46; GCN: v_mov_b32_e32 v4, v6
47; GCN-NOT: s_endpgm
48attributes #1 = { "ShaderType"="0" "InitialPSInputAddr"="0" }
49define {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 {
50  %i0 = extractelement <2 x i32> %4, i32 0
51  %i1 = extractelement <2 x i32> %4, i32 1
52  %i2 = extractelement <2 x i32> %7, i32 0
53  %i3 = extractelement <2 x i32> %8, i32 0
54  %f0 = bitcast i32 %i0 to float
55  %f1 = bitcast i32 %i1 to float
56  %f2 = bitcast i32 %i2 to float
57  %f3 = bitcast i32 %i3 to float
58  %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
59  %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
60  %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
61  %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
62  %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
63  ret {float, float, float, float, float} %r4
64}
65
66
67; GCN: .long 165580
68; GCN-NEXT: .long 1
69; GCN-NEXT: .long 165584
70; GCN-NEXT: .long 1
71; GCN-LABEL: {{^}}ps_input_ena_no_inputs:
72; GCN: v_mov_b32_e32 v0, 1.0
73; GCN-NOT: s_endpgm
74define float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 {
75  ret float 1.0
76}
77
78
79; GCN: .long 165580
80; GCN-NEXT: .long 2081
81; GCN-NEXT: .long 165584
82; GCN-NEXT: .long 2081
83; GCN-LABEL: {{^}}ps_input_ena_pos_w:
84; GCN-DAG: v_mov_b32_e32 v0, v4
85; GCN-DAG: v_mov_b32_e32 v1, v2
86; GCN: v_mov_b32_e32 v2, v3
87; GCN-NOT: s_endpgm
88define {float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 {
89  %f = bitcast <2 x i32> %8 to <2 x float>
90  %s = insertvalue {float, <2 x float>} undef, float %14, 0
91  %s1 = insertvalue {float, <2 x float>} %s, <2 x float> %f, 1
92  ret {float, <2 x float>} %s1
93}
94
95
96; GCN: .long 165580
97; GCN-NEXT: .long 562
98; GCN-NEXT: .long 165584
99; GCN-NEXT: .long 563
100; GCN-LABEL: {{^}}vgpr_ps_addr1:
101; GCN-DAG: v_mov_b32_e32 v0, v2
102; GCN-DAG: v_mov_b32_e32 v1, v3
103; GCN: v_mov_b32_e32 v2, v4
104; GCN-DAG: v_mov_b32_e32 v3, v6
105; GCN-DAG: v_mov_b32_e32 v4, v8
106; GCN-NOT: s_endpgm
107attributes #2 = { "ShaderType"="0" "InitialPSInputAddr"="1" }
108define {float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #2 {
109  %i0 = extractelement <2 x i32> %4, i32 0
110  %i1 = extractelement <2 x i32> %4, i32 1
111  %i2 = extractelement <2 x i32> %7, i32 0
112  %i3 = extractelement <2 x i32> %8, i32 0
113  %f0 = bitcast i32 %i0 to float
114  %f1 = bitcast i32 %i1 to float
115  %f2 = bitcast i32 %i2 to float
116  %f3 = bitcast i32 %i3 to float
117  %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
118  %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
119  %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
120  %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
121  %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
122  ret {float, float, float, float, float} %r4
123}
124
125
126; GCN: .long 165580
127; GCN-NEXT: .long 562
128; GCN-NEXT: .long 165584
129; GCN-NEXT: .long 631
130; GCN-LABEL: {{^}}vgpr_ps_addr119:
131; GCN-DAG: v_mov_b32_e32 v0, v2
132; GCN-DAG: v_mov_b32_e32 v1, v3
133; GCN: v_mov_b32_e32 v2, v6
134; GCN: v_mov_b32_e32 v3, v8
135; GCN: v_mov_b32_e32 v4, v12
136; GCN-NOT: s_endpgm
137attributes #3 = { "ShaderType"="0" "InitialPSInputAddr"="119" }
138define {float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #3 {
139  %i0 = extractelement <2 x i32> %4, i32 0
140  %i1 = extractelement <2 x i32> %4, i32 1
141  %i2 = extractelement <2 x i32> %7, i32 0
142  %i3 = extractelement <2 x i32> %8, i32 0
143  %f0 = bitcast i32 %i0 to float
144  %f1 = bitcast i32 %i1 to float
145  %f2 = bitcast i32 %i2 to float
146  %f3 = bitcast i32 %i3 to float
147  %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
148  %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
149  %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
150  %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
151  %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
152  ret {float, float, float, float, float} %r4
153}
154
155
156; GCN: .long 165580
157; GCN-NEXT: .long 562
158; GCN-NEXT: .long 165584
159; GCN-NEXT: .long 946
160; GCN-LABEL: {{^}}vgpr_ps_addr418:
161; GCN-NOT: v_mov_b32_e32 v0
162; GCN-NOT: v_mov_b32_e32 v1
163; GCN-NOT: v_mov_b32_e32 v2
164; GCN: v_mov_b32_e32 v3, v4
165; GCN: v_mov_b32_e32 v4, v8
166; GCN-NOT: s_endpgm
167attributes #4 = { "ShaderType"="0" "InitialPSInputAddr"="418" }
168define {float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #4 {
169  %i0 = extractelement <2 x i32> %4, i32 0
170  %i1 = extractelement <2 x i32> %4, i32 1
171  %i2 = extractelement <2 x i32> %7, i32 0
172  %i3 = extractelement <2 x i32> %8, i32 0
173  %f0 = bitcast i32 %i0 to float
174  %f1 = bitcast i32 %i1 to float
175  %f2 = bitcast i32 %i2 to float
176  %f3 = bitcast i32 %i3 to float
177  %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
178  %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
179  %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
180  %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
181  %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
182  ret {float, float, float, float, float} %r4
183}
184
185
186; GCN-LABEL: {{^}}sgpr:
187; GCN: s_add_i32 s0, s3, 2
188; GCN: s_mov_b32 s2, s3
189; GCN-NOT: s_endpgm
190define {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
191  %x = add i32 %2, 2
192  %a = insertvalue {i32, i32, i32} undef, i32 %x, 0
193  %b = insertvalue {i32, i32, i32} %a, i32 %1, 1
194  %c = insertvalue {i32, i32, i32} %a, i32 %2, 2
195  ret {i32, i32, i32} %c
196}
197
198
199; GCN-LABEL: {{^}}sgpr_literal:
200; GCN: s_mov_b32 s0, 5
201; GCN-NOT: s_mov_b32 s0, s0
202; GCN-DAG: s_mov_b32 s1, 6
203; GCN-DAG: s_mov_b32 s2, 7
204; GCN-DAG: s_mov_b32 s3, 8
205; GCN-NOT: s_endpgm
206define {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
207  %x = add i32 %2, 2
208  ret {i32, i32, i32, i32} {i32 5, i32 6, i32 7, i32 8}
209}
210
211
212; GCN-LABEL: {{^}}both:
213; GCN: v_mov_b32_e32 v1, v0
214; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1
215; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
216; GCN-DAG: s_add_i32 s0, s3, 2
217; GCN-DAG: s_mov_b32 s1, s2
218; GCN: s_mov_b32 s2, s3
219; GCN: s_waitcnt expcnt(0)
220; GCN-NOT: s_endpgm
221define {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
222  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
223  %v = fadd float %3, 1.0
224  %s = add i32 %2, 2
225  %a0 = insertvalue {float, i32, float, i32, i32} undef, float %v, 0
226  %a1 = insertvalue {float, i32, float, i32, i32} %a0, i32 %s, 1
227  %a2 = insertvalue {float, i32, float, i32, i32} %a1, float %3, 2
228  %a3 = insertvalue {float, i32, float, i32, i32} %a2, i32 %1, 3
229  %a4 = insertvalue {float, i32, float, i32, i32} %a3, i32 %2, 4
230  ret {float, i32, float, i32, i32} %a4
231}
232
233
234; GCN-LABEL: {{^}}structure_literal:
235; GCN: v_mov_b32_e32 v3, v0
236; GCN-DAG: v_mov_b32_e32 v0, 1.0
237; GCN-DAG: s_mov_b32 s0, 2
238; GCN-DAG: s_mov_b32 s1, 3
239; GCN-DAG: v_mov_b32_e32 v1, 2.0
240; GCN-DAG: v_mov_b32_e32 v2, 4.0
241; GCN-DAG: exp 15, 0, 1, 1, 1, v3, v3, v3, v3
242define {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
243  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
244  ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3, <2 x float> <float 2.0, float 4.0>}}
245}
246