1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-pre-emit-peephole -amdgpu-skip-threshold=10 -verify-machineinstrs  %s -o - | FileCheck %s
3# Make sure mandatory skips are not removed around mode defs.
4# FIXME: -amdgpu-skip-threshold seems to be backwards.
5
6---
7
8name: need_skip_setreg_imm32_b32
9body: |
10  ; CHECK-LABEL: name: need_skip_setreg_imm32_b32
11  ; CHECK: bb.0:
12  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
13  ; CHECK-NEXT: {{  $}}
14  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
15  ; CHECK-NEXT: {{  $}}
16  ; CHECK-NEXT: bb.1:
17  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
18  ; CHECK-NEXT: {{  $}}
19  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
20  ; CHECK-NEXT:   S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode
21  ; CHECK-NEXT: {{  $}}
22  ; CHECK-NEXT: bb.2:
23  ; CHECK-NEXT:   S_ENDPGM 0
24  bb.0:
25    successors: %bb.1, %bb.2
26    S_CBRANCH_EXECZ %bb.2, implicit $exec
27
28  bb.1:
29    successors: %bb.2
30    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
31    S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode
32
33  bb.2:
34    S_ENDPGM 0
35...
36
37---
38
39name: need_skip_setreg_b32
40body: |
41  ; CHECK-LABEL: name: need_skip_setreg_b32
42  ; CHECK: bb.0:
43  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
44  ; CHECK-NEXT:   liveins: $sgpr0
45  ; CHECK-NEXT: {{  $}}
46  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
47  ; CHECK-NEXT: {{  $}}
48  ; CHECK-NEXT: bb.1:
49  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
50  ; CHECK-NEXT:   liveins: $sgpr0
51  ; CHECK-NEXT: {{  $}}
52  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
53  ; CHECK-NEXT:   S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode
54  ; CHECK-NEXT: {{  $}}
55  ; CHECK-NEXT: bb.2:
56  ; CHECK-NEXT:   S_ENDPGM 0
57  bb.0:
58    liveins: $sgpr0
59    successors: %bb.1, %bb.2
60    S_CBRANCH_EXECZ %bb.2, implicit $exec
61
62  bb.1:
63    liveins: $sgpr0
64    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
65    S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode
66
67  bb.2:
68    S_ENDPGM 0
69...
70
71---
72
73name: need_skip_denorm_mode
74body: |
75  ; CHECK-LABEL: name: need_skip_denorm_mode
76  ; CHECK: bb.0:
77  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
78  ; CHECK-NEXT: {{  $}}
79  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
80  ; CHECK-NEXT: {{  $}}
81  ; CHECK-NEXT: bb.1:
82  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
83  ; CHECK-NEXT: {{  $}}
84  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
85  ; CHECK-NEXT:   S_DENORM_MODE 3, implicit-def $mode, implicit $mode
86  ; CHECK-NEXT: {{  $}}
87  ; CHECK-NEXT: bb.2:
88  ; CHECK-NEXT:   S_ENDPGM 0
89  bb.0:
90    successors: %bb.1, %bb.2
91    S_CBRANCH_EXECZ %bb.2, implicit $exec
92
93  bb.1:
94    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
95    S_DENORM_MODE 3, implicit-def $mode, implicit $mode
96
97  bb.2:
98    S_ENDPGM 0
99...
100
101---
102
103name: need_skip_round_mode
104body: |
105  ; CHECK-LABEL: name: need_skip_round_mode
106  ; CHECK: bb.0:
107  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
108  ; CHECK-NEXT: {{  $}}
109  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
110  ; CHECK-NEXT: {{  $}}
111  ; CHECK-NEXT: bb.1:
112  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
113  ; CHECK-NEXT: {{  $}}
114  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
115  ; CHECK-NEXT:   S_ROUND_MODE 3, implicit-def $mode, implicit $mode
116  ; CHECK-NEXT: {{  $}}
117  ; CHECK-NEXT: bb.2:
118  ; CHECK-NEXT:   S_ENDPGM 0
119  bb.0:
120    successors: %bb.1, %bb.2
121    S_CBRANCH_EXECZ %bb.2, implicit $exec
122
123  bb.1:
124    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
125    S_ROUND_MODE 3, implicit-def $mode, implicit $mode
126
127  bb.2:
128    S_ENDPGM 0
129...
130
131---
132
133name: need_skip_writelane_b32
134body: |
135  ; CHECK-LABEL: name: need_skip_writelane_b32
136  ; CHECK: bb.0:
137  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
138  ; CHECK-NEXT: {{  $}}
139  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
140  ; CHECK-NEXT: {{  $}}
141  ; CHECK-NEXT: bb.1:
142  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
143  ; CHECK-NEXT: {{  $}}
144  ; CHECK-NEXT:   $sgpr0 = IMPLICIT_DEF
145  ; CHECK-NEXT:   $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
146  ; CHECK-NEXT: {{  $}}
147  ; CHECK-NEXT: bb.2:
148  ; CHECK-NEXT:   S_ENDPGM 0
149  bb.0:
150    successors: %bb.1, %bb.2
151    S_CBRANCH_EXECZ %bb.2, implicit $exec
152
153  bb.1:
154    successors: %bb.2
155    $sgpr0 = IMPLICIT_DEF
156    $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
157
158  bb.2:
159    S_ENDPGM 0
160...
161
162---
163name: need_skip_readlane_b32
164body: |
165  ; CHECK-LABEL: name: need_skip_readlane_b32
166  ; CHECK: bb.0:
167  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
168  ; CHECK-NEXT: {{  $}}
169  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
170  ; CHECK-NEXT: {{  $}}
171  ; CHECK-NEXT: bb.1:
172  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
173  ; CHECK-NEXT: {{  $}}
174  ; CHECK-NEXT:   $vgpr0 = IMPLICIT_DEF
175  ; CHECK-NEXT:   $sgpr0 = V_READLANE_B32 $vgpr0, 0
176  ; CHECK-NEXT: {{  $}}
177  ; CHECK-NEXT: bb.2:
178  ; CHECK-NEXT:   S_ENDPGM 0
179  bb.0:
180    successors: %bb.1, %bb.2
181    S_CBRANCH_EXECZ %bb.2, implicit $exec
182
183  bb.1:
184    successors: %bb.2
185    $vgpr0 = IMPLICIT_DEF
186    $sgpr0 = V_READLANE_B32 $vgpr0, 0
187
188  bb.2:
189    S_ENDPGM 0
190...
191