1; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC 2; RUN: opt -S -mtriple=r600-unknown-unknown-amdgiz -mcpu=redwood -amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s 3target datalayout = "A5" 4 5declare i32 @llvm.r600.read.tidig.x() nounwind readnone 6 7; FUNC-LABEL: {{^}}mova_same_clause: 8 9; R600: LDS_WRITE 10; R600: LDS_WRITE 11; R600: LDS_READ 12; R600: LDS_READ 13 14; OPT: call i32 @llvm.r600.read.local.size.y(), !range !0 15; OPT: call i32 @llvm.r600.read.local.size.z(), !range !0 16; OPT: call i32 @llvm.r600.read.tidig.x(), !range !1 17; OPT: call i32 @llvm.r600.read.tidig.y(), !range !1 18; OPT: call i32 @llvm.r600.read.tidig.z(), !range !1 19 20define amdgpu_kernel void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { 21entry: 22 %stack = alloca [5 x i32], align 4, addrspace(5) 23 %0 = load i32, i32 addrspace(1)* %in, align 4 24 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0 25 store i32 4, i32 addrspace(5)* %arrayidx1, align 4 26 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 27 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 28 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1 29 store i32 5, i32 addrspace(5)* %arrayidx3, align 4 30 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0 31 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4 32 store i32 %2, i32 addrspace(1)* %out, align 4 33 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1 34 %3 = load i32, i32 addrspace(5)* %arrayidx12 35 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 36 store i32 %3, i32 addrspace(1)* %arrayidx13 37 ret void 38} 39 40; This test checks that the stack offset is calculated correctly for structs. 41; All register loads/stores should be optimized away, so there shouldn't be 42; any MOVA instructions. 43; 44; XXX: This generated code has unnecessary MOVs, we should be able to optimize 45; this. 46 47; FUNC-LABEL: {{^}}multiple_structs: 48; R600-NOT: MOVA_INT 49%struct.point = type { i32, i32 } 50 51define amdgpu_kernel void @multiple_structs(i32 addrspace(1)* %out) #0 { 52entry: 53 %a = alloca %struct.point, addrspace(5) 54 %b = alloca %struct.point, addrspace(5) 55 %a.x.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0 56 %a.y.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 1 57 %b.x.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0 58 %b.y.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 1 59 store i32 0, i32 addrspace(5)* %a.x.ptr 60 store i32 1, i32 addrspace(5)* %a.y.ptr 61 store i32 2, i32 addrspace(5)* %b.x.ptr 62 store i32 3, i32 addrspace(5)* %b.y.ptr 63 %a.indirect.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0 64 %b.indirect.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0 65 %a.indirect = load i32, i32 addrspace(5)* %a.indirect.ptr 66 %b.indirect = load i32, i32 addrspace(5)* %b.indirect.ptr 67 %0 = add i32 %a.indirect, %b.indirect 68 store i32 %0, i32 addrspace(1)* %out 69 ret void 70} 71 72; Test direct access of a private array inside a loop. The private array 73; loads and stores should be lowered to copies, so there shouldn't be any 74; MOVA instructions. 75 76; FUNC-LABEL: {{^}}direct_loop: 77; R600-NOT: MOVA_INT 78 79define amdgpu_kernel void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 80entry: 81 %prv_array_const = alloca [2 x i32], addrspace(5) 82 %prv_array = alloca [2 x i32], addrspace(5) 83 %a = load i32, i32 addrspace(1)* %in 84 %b_src_ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 85 %b = load i32, i32 addrspace(1)* %b_src_ptr 86 %a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0 87 store i32 %a, i32 addrspace(5)* %a_dst_ptr 88 %b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 1 89 store i32 %b, i32 addrspace(5)* %b_dst_ptr 90 br label %for.body 91 92for.body: 93 %inc = phi i32 [0, %entry], [%count, %for.body] 94 %x_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0 95 %x = load i32, i32 addrspace(5)* %x_ptr 96 %y_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0 97 %y = load i32, i32 addrspace(5)* %y_ptr 98 %xy = add i32 %x, %y 99 store i32 %xy, i32 addrspace(5)* %y_ptr 100 %count = add i32 %inc, 1 101 %done = icmp eq i32 %count, 4095 102 br i1 %done, label %for.end, label %for.body 103 104for.end: 105 %value_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0 106 %value = load i32, i32 addrspace(5)* %value_ptr 107 store i32 %value, i32 addrspace(1)* %out 108 ret void 109} 110 111; FUNC-LABEL: {{^}}short_array: 112 113; R600: MOVA_INT 114define amdgpu_kernel void @short_array(i32 addrspace(1)* %out, i32 %index) #0 { 115entry: 116 %0 = alloca [2 x i16], addrspace(5) 117 %1 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 0 118 %2 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 1 119 store i16 0, i16 addrspace(5)* %1 120 store i16 1, i16 addrspace(5)* %2 121 %3 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 %index 122 %4 = load i16, i16 addrspace(5)* %3 123 %5 = sext i16 %4 to i32 124 store i32 %5, i32 addrspace(1)* %out 125 ret void 126} 127 128; FUNC-LABEL: {{^}}char_array: 129 130; R600: MOVA_INT 131define amdgpu_kernel void @char_array(i32 addrspace(1)* %out, i32 %index) #0 { 132entry: 133 %0 = alloca [2 x i8], addrspace(5) 134 %1 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 0 135 %2 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 1 136 store i8 0, i8 addrspace(5)* %1 137 store i8 1, i8 addrspace(5)* %2 138 %3 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 %index 139 %4 = load i8, i8 addrspace(5)* %3 140 %5 = sext i8 %4 to i32 141 store i32 %5, i32 addrspace(1)* %out 142 ret void 143 144} 145 146; Make sure we don't overwrite workitem information with private memory 147 148; FUNC-LABEL: {{^}}work_item_info: 149; R600-NOT: MOV T0.X 150; Additional check in case the move ends up in the last slot 151; R600-NOT: MOV * TO.X 152define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) #0 { 153entry: 154 %0 = alloca [2 x i32], addrspace(5) 155 %1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0 156 %2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1 157 store i32 0, i32 addrspace(5)* %1 158 store i32 1, i32 addrspace(5)* %2 159 %3 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in 160 %4 = load i32, i32 addrspace(5)* %3 161 %5 = call i32 @llvm.r600.read.tidig.x() 162 %6 = add i32 %4, %5 163 store i32 %6, i32 addrspace(1)* %out 164 ret void 165} 166 167; Test that two stack objects are not stored in the same register 168; The second stack object should be in T3.X 169; FUNC-LABEL: {{^}}no_overlap: 170; R600_CHECK: MOV 171; R600_CHECK: [[CHAN:[XYZW]]]+ 172; R600-NOT: [[CHAN]]+ 173define amdgpu_kernel void @no_overlap(i32 addrspace(1)* %out, i32 %in) #0 { 174entry: 175 %0 = alloca [3 x i8], align 1, addrspace(5) 176 %1 = alloca [2 x i8], align 1, addrspace(5) 177 %2 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 0 178 %3 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 1 179 %4 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 2 180 %5 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 0 181 %6 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 1 182 store i8 0, i8 addrspace(5)* %2 183 store i8 1, i8 addrspace(5)* %3 184 store i8 2, i8 addrspace(5)* %4 185 store i8 1, i8 addrspace(5)* %5 186 store i8 0, i8 addrspace(5)* %6 187 %7 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 %in 188 %8 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 %in 189 %9 = load i8, i8 addrspace(5)* %7 190 %10 = load i8, i8 addrspace(5)* %8 191 %11 = add i8 %9, %10 192 %12 = sext i8 %11 to i32 193 store i32 %12, i32 addrspace(1)* %out 194 ret void 195} 196 197define amdgpu_kernel void @char_array_array(i32 addrspace(1)* %out, i32 %index) #0 { 198entry: 199 %alloca = alloca [2 x [2 x i8]], addrspace(5) 200 %gep0 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 0 201 %gep1 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 1 202 store i8 0, i8 addrspace(5)* %gep0 203 store i8 1, i8 addrspace(5)* %gep1 204 %gep2 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index 205 %load = load i8, i8 addrspace(5)* %gep2 206 %sext = sext i8 %load to i32 207 store i32 %sext, i32 addrspace(1)* %out 208 ret void 209} 210 211define amdgpu_kernel void @i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { 212entry: 213 %alloca = alloca [2 x [2 x i32]], addrspace(5) 214 %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0 215 %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1 216 store i32 0, i32 addrspace(5)* %gep0 217 store i32 1, i32 addrspace(5)* %gep1 218 %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index 219 %load = load i32, i32 addrspace(5)* %gep2 220 store i32 %load, i32 addrspace(1)* %out 221 ret void 222} 223 224define amdgpu_kernel void @i64_array_array(i64 addrspace(1)* %out, i32 %index) #0 { 225entry: 226 %alloca = alloca [2 x [2 x i64]], addrspace(5) 227 %gep0 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 0 228 %gep1 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 1 229 store i64 0, i64 addrspace(5)* %gep0 230 store i64 1, i64 addrspace(5)* %gep1 231 %gep2 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index 232 %load = load i64, i64 addrspace(5)* %gep2 233 store i64 %load, i64 addrspace(1)* %out 234 ret void 235} 236 237%struct.pair32 = type { i32, i32 } 238 239define amdgpu_kernel void @struct_array_array(i32 addrspace(1)* %out, i32 %index) #0 { 240entry: 241 %alloca = alloca [2 x [2 x %struct.pair32]], addrspace(5) 242 %gep0 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0, i32 1 243 %gep1 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1, i32 1 244 store i32 0, i32 addrspace(5)* %gep0 245 store i32 1, i32 addrspace(5)* %gep1 246 %gep2 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index, i32 0 247 %load = load i32, i32 addrspace(5)* %gep2 248 store i32 %load, i32 addrspace(1)* %out 249 ret void 250} 251 252define amdgpu_kernel void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) #0 { 253entry: 254 %alloca = alloca [2 x %struct.pair32], addrspace(5) 255 %gep0 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 0, i32 1 256 %gep1 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 1, i32 0 257 store i32 0, i32 addrspace(5)* %gep0 258 store i32 1, i32 addrspace(5)* %gep1 259 %gep2 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 %index, i32 0 260 %load = load i32, i32 addrspace(5)* %gep2 261 store i32 %load, i32 addrspace(1)* %out 262 ret void 263} 264 265define amdgpu_kernel void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind { 266entry: 267 %tmp = alloca [2 x i32], addrspace(5) 268 %tmp1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0 269 %tmp2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1 270 store i32 0, i32 addrspace(5)* %tmp1 271 store i32 1, i32 addrspace(5)* %tmp2 272 %cmp = icmp eq i32 %in, 0 273 %sel = select i1 %cmp, i32 addrspace(5)* %tmp1, i32 addrspace(5)* %tmp2 274 %load = load i32, i32 addrspace(5)* %sel 275 store i32 %load, i32 addrspace(1)* %out 276 ret void 277} 278 279; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it 280; finds one, it should stop trying to promote. 281 282; FUNC-LABEL: ptrtoint: 283; SI-NOT: ds_write 284; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen 285; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; 286define amdgpu_kernel void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { 287 %alloca = alloca [16 x i32], addrspace(5) 288 %tmp0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a 289 store i32 5, i32 addrspace(5)* %tmp0 290 %tmp1 = ptrtoint [16 x i32] addrspace(5)* %alloca to i32 291 %tmp2 = add i32 %tmp1, 5 292 %tmp3 = inttoptr i32 %tmp2 to i32 addrspace(5)* 293 %tmp4 = getelementptr inbounds i32, i32 addrspace(5)* %tmp3, i32 %b 294 %tmp5 = load i32, i32 addrspace(5)* %tmp4 295 store i32 %tmp5, i32 addrspace(1)* %out 296 ret void 297} 298 299; OPT: !0 = !{i32 0, i32 257} 300; OPT: !1 = !{i32 0, i32 256} 301 302attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,2" } 303