1; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}test_membound:
4; GCN: MemoryBound: 1
5; GCN: WaveLimiterHint : 1
6define amdgpu_kernel void @test_membound(<4 x i32> addrspace(1)* nocapture readonly %arg, <4 x i32> addrspace(1)* nocapture %arg1) {
7bb:
8  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
9  %tmp2 = zext i32 %tmp to i64
10  %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
11  %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
12  %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
13  store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
14  %tmp6 = add nuw nsw i64 %tmp2, 1
15  %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
16  %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
17  %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
18  store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
19  %tmp10 = add nuw nsw i64 %tmp2, 2
20  %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
21  %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
22  %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
23  store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
24  %tmp14 = add nuw nsw i64 %tmp2, 3
25  %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
26  %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
27  %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
28  store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
29  ret void
30}
31
32; GCN-LABEL: {{^}}test_large_stride:
33; GCN: MemoryBound: 0
34; GCN: WaveLimiterHint : 1
35define amdgpu_kernel void @test_large_stride(i32 addrspace(1)* nocapture %arg) {
36bb:
37  %tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 4096
38  %tmp1 = load i32, i32 addrspace(1)* %tmp, align 4
39  %mul1 = mul i32 %tmp1, %tmp1
40  %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
41  store i32 %mul1, i32 addrspace(1)* %tmp2, align 4
42  %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 8192
43  %tmp4 = load i32, i32 addrspace(1)* %tmp3, align 4
44  %mul4 = mul i32 %tmp4, %tmp4
45  %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
46  store i32 %mul4, i32 addrspace(1)* %tmp5, align 4
47  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 12288
48  %tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
49  %mul7 = mul i32 %tmp7, %tmp7
50  %tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
51  store i32 %mul7, i32 addrspace(1)* %tmp8, align 4
52  ret void
53}
54
55; GCN-LABEL: {{^}}test_indirect:
56; GCN: MemoryBound: 0
57; GCN: WaveLimiterHint : 1
58define amdgpu_kernel void @test_indirect(i32 addrspace(1)* nocapture %arg) {
59bb:
60  %tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
61  %tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
62  %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
63  %tmp3 = bitcast i32 addrspace(1)* %arg to <4 x i32> addrspace(1)*
64  %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 4
65  %tmp5 = extractelement <4 x i32> %tmp4, i32 0
66  %tmp6 = sext i32 %tmp5 to i64
67  %tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp6
68  %tmp8 = load i32, i32 addrspace(1)* %tmp7, align 4
69  store i32 %tmp8, i32 addrspace(1)* %arg, align 4
70  %tmp9 = extractelement <4 x i32> %tmp4, i32 1
71  %tmp10 = sext i32 %tmp9 to i64
72  %tmp11 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp10
73  %tmp12 = load i32, i32 addrspace(1)* %tmp11, align 4
74  store i32 %tmp12, i32 addrspace(1)* %tmp, align 4
75  %tmp13 = extractelement <4 x i32> %tmp4, i32 2
76  %tmp14 = sext i32 %tmp13 to i64
77  %tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp14
78  %tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4
79  store i32 %tmp16, i32 addrspace(1)* %tmp1, align 4
80  %tmp17 = extractelement <4 x i32> %tmp4, i32 3
81  %tmp18 = sext i32 %tmp17 to i64
82  %tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18
83  %tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
84  store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4
85  ret void
86}
87
88; GCN-LABEL: {{^}}test_indirect_through_phi:
89; MemoryBound: 0
90; WaveLimiterHint : 0
91define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) {
92bb:
93  %load = load float, float addrspace(1)* %arg, align 8
94  %load.f = bitcast float %load to i32
95  %n = tail call i32 @llvm.amdgcn.workitem.id.x()
96  br label %bb1
97
98bb1:                                              ; preds = %bb1, %bb
99  %phi = phi i32 [ %load.f, %bb ], [ %and2, %bb1 ]
100  %ind = phi i32 [ 0, %bb ], [ %inc2, %bb1 ]
101  %and1 = and i32 %phi, %n
102  %gep = getelementptr inbounds float, float addrspace(1)* %arg, i32 %and1
103  store float %load, float addrspace(1)* %gep, align 4
104  %inc1 = add nsw i32 %phi, 1310720
105  %and2 = and i32 %inc1, %n
106  %inc2 = add nuw nsw i32 %ind, 1
107  %cmp = icmp eq i32 %inc2, 1024
108  br i1 %cmp, label %bb2, label %bb1
109
110bb2:                                              ; preds = %bb1
111  ret void
112}
113
114declare i32 @llvm.amdgcn.workitem.id.x()
115