1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
2; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX90A %s
3
4; GCN-LABEL: {{^}}fadd_v2_vv:
5; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
6; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
7define amdgpu_kernel void @fadd_v2_vv(<2 x float> addrspace(1)* %a) {
8  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
9  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
10  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
11  %add = fadd <2 x float> %load, %load
12  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
13  ret void
14}
15
16; GCN-LABEL: {{^}}fadd_v2_vs:
17; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
18; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
19define amdgpu_kernel void @fadd_v2_vs(<2 x float> addrspace(1)* %a, <2 x float> %x) {
20  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
21  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
22  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
23  %add = fadd <2 x float> %load, %x
24  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
25  ret void
26}
27
28; GCN-LABEL: {{^}}fadd_v4_vs:
29; GFX900-COUNT-4: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
30; GFX90A-COUNT-2: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
31define amdgpu_kernel void @fadd_v4_vs(<4 x float> addrspace(1)* %a, <4 x float> %x) {
32  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
33  %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %a, i32 %id
34  %load = load <4 x float>, <4 x float> addrspace(1)* %gep, align 16
35  %add = fadd <4 x float> %load, %x
36  store <4 x float> %add, <4 x float> addrspace(1)* %gep, align 16
37  ret void
38}
39
40; GCN-LABEL: {{^}}fadd_v32_vs:
41; GFX900-COUNT-32: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
42; GFX90A-COUNT-16: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
43define amdgpu_kernel void @fadd_v32_vs(<32 x float> addrspace(1)* %a, <32 x float> %x) {
44  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
45  %gep = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %a, i32 %id
46  %load = load <32 x float>, <32 x float> addrspace(1)* %gep, align 128
47  %add = fadd <32 x float> %load, %x
48  store <32 x float> %add, <32 x float> addrspace(1)* %gep, align 128
49  ret void
50}
51
52; GCN-LABEL: {{^}}fadd_v2_v_imm:
53; GCN:            s_mov_b32 s[[K:[0-9]+]], 0x42c80000
54; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}}
55; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}}
56define amdgpu_kernel void @fadd_v2_v_imm(<2 x float> addrspace(1)* %a) {
57  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
58  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
59  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
60  %add = fadd <2 x float> %load, <float 100.0, float 100.0>
61  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
62  ret void
63}
64
65; GCN-LABEL: {{^}}fadd_v2_v_v_splat:
66; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v0
67; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[0:1] op_sel_hi:[1,0]{{$}}
68define amdgpu_kernel void @fadd_v2_v_v_splat(<2 x float> addrspace(1)* %a) {
69  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
70  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
71  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
72  %fid = bitcast i32 %id to float
73  %tmp1 = insertelement <2 x float> undef, float %fid, i64 0
74  %k = insertelement <2 x float> %tmp1, float %fid, i64 1
75  %add = fadd <2 x float> %load, %k
76  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
77  ret void
78}
79
80; GCN-LABEL: {{^}}fadd_v2_v_lit_splat:
81; GFX900-COUNT-2: v_add_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
82; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 1.0 op_sel_hi:[1,0]{{$}}
83define amdgpu_kernel void @fadd_v2_v_lit_splat(<2 x float> addrspace(1)* %a) {
84  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
85  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
86  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
87  %add = fadd <2 x float> %load, <float 1.0, float 1.0>
88  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
89  ret void
90}
91
92; GCN-LABEL: {{^}}fadd_v2_v_lit_hi0:
93; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
94; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
95; GFX90A-DAG: s_mov_b32 s[[HI:[0-9]+]], 0
96; GFX90A-DAG: s_mov_b32 s[[LO:[0-9]+]], 1.0
97; GFX90A:     v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[LO]]:[[HI]]]{{$}}
98define amdgpu_kernel void @fadd_v2_v_lit_hi0(<2 x float> addrspace(1)* %a) {
99  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
100  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
101  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
102  %add = fadd <2 x float> %load, <float 1.0, float 0.0>
103  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
104  ret void
105}
106
107; GCN-LABEL: {{^}}fadd_v2_v_lit_lo0:
108; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
109; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
110; GFX90A-DAG: s_mov_b32 s[[LO:[0-9]+]], 0
111; GFX90A-DAG: s_mov_b32 s[[HI:[0-9]+]], 1.0
112; GFX90A:     v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[LO]]:[[HI]]]{{$}}
113define amdgpu_kernel void @fadd_v2_v_lit_lo0(<2 x float> addrspace(1)* %a) {
114  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
115  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
116  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
117  %add = fadd <2 x float> %load, <float 0.0, float 1.0>
118  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
119  ret void
120}
121
122; GCN-LABEL: {{^}}fadd_v2_v_unfoldable_lit:
123; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
124; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
125; GFX90A-DAG: s_mov_b32 s{{[0-9]+}}, 1.0
126; GFX90A-DAG: s_mov_b32 s{{[0-9]+}}, 2.0
127; GFX90A:     v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
128define amdgpu_kernel void @fadd_v2_v_unfoldable_lit(<2 x float> addrspace(1)* %a) {
129  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
130  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
131  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
132  %add = fadd <2 x float> %load, <float 1.0, float 2.0>
133  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
134  ret void
135}
136
137; GCN-LABEL: {{^}}fadd_v2_v_fneg:
138; GFX900-COUNT-2: v_subrev_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
139; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]{{$}}
140define amdgpu_kernel void @fadd_v2_v_fneg(<2 x float> addrspace(1)* %a, float %x) {
141  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
142  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
143  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
144  %fneg = fsub float -0.0, %x
145  %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
146  %k = insertelement <2 x float> %tmp1, float %fneg, i64 1
147  %add = fadd <2 x float> %load, %k
148  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
149  ret void
150}
151
152; GCN-LABEL: {{^}}fadd_v2_v_fneg_lo:
153; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
154; GFX900-DAG: v_subrev_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
155; GFX90A:     v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] op_sel_hi:[1,0] neg_lo:[0,1]{{$}}
156define amdgpu_kernel void @fadd_v2_v_fneg_lo(<2 x float> addrspace(1)* %a, float %x) {
157  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
158  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
159  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
160  %fneg = fsub float -0.0, %x
161  %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
162  %k = insertelement <2 x float> %tmp1, float %x, i64 1
163  %add = fadd <2 x float> %load, %k
164  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
165  ret void
166}
167
168; GCN-LABEL: {{^}}fadd_v2_v_fneg_hi:
169; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
170; GFX900-DAG: v_subrev_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
171; GFX90A:     v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] op_sel_hi:[1,0] neg_hi:[0,1]{{$}}
172define amdgpu_kernel void @fadd_v2_v_fneg_hi(<2 x float> addrspace(1)* %a, float %x) {
173  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
174  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
175  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
176  %fneg = fsub float -0.0, %x
177  %tmp1 = insertelement <2 x float> undef, float %x, i64 0
178  %k = insertelement <2 x float> %tmp1, float %fneg, i64 1
179  %add = fadd <2 x float> %load, %k
180  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
181  ret void
182}
183
184; GCN-LABEL: {{^}}fadd_v2_v_fneg_lo2:
185; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
186; GFX900-DAG: v_subrev_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
187; GFX90A:     v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] neg_lo:[0,1]{{$}}
188define amdgpu_kernel void @fadd_v2_v_fneg_lo2(<2 x float> addrspace(1)* %a, float %x, float %y) {
189  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
190  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
191  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
192  %fneg = fsub float -0.0, %x
193  %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
194  %k = insertelement <2 x float> %tmp1, float %y, i64 1
195  %add = fadd <2 x float> %load, %k
196  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
197  ret void
198}
199
200; GCN-LABEL: {{^}}fadd_v2_v_fneg_hi2:
201; GFX900-DAG: v_add_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
202; GFX900-DAG: v_subrev_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
203; GFX90A:     v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] op_sel:[0,1] op_sel_hi:[1,0] neg_hi:[0,1]{{$}}
204define amdgpu_kernel void @fadd_v2_v_fneg_hi2(<2 x float> addrspace(1)* %a, float %x, float %y) {
205  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
206  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
207  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
208  %fneg = fsub float -0.0, %x
209  %tmp1 = insertelement <2 x float> undef, float %y, i64 0
210  %k = insertelement <2 x float> %tmp1, float %fneg, i64 1
211  %add = fadd <2 x float> %load, %k
212  store <2 x float> %add, <2 x float> addrspace(1)* %gep, align 8
213  ret void
214}
215
216; GCN-LABEL: {{^}}fmul_v2_vv:
217; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
218; GFX90A:         v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
219define amdgpu_kernel void @fmul_v2_vv(<2 x float> addrspace(1)* %a) {
220  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
221  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
222  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
223  %mul = fmul <2 x float> %load, %load
224  store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
225  ret void
226}
227
228; GCN-LABEL: {{^}}fmul_v2_vs:
229; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
230; GFX90A:         v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
231define amdgpu_kernel void @fmul_v2_vs(<2 x float> addrspace(1)* %a, <2 x float> %x) {
232  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
233  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
234  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
235  %mul = fmul <2 x float> %load, %x
236  store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
237  ret void
238}
239
240; GCN-LABEL: {{^}}fmul_v4_vs:
241; GFX900-COUNT-4: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
242; GFX90A-COUNT-2: v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
243define amdgpu_kernel void @fmul_v4_vs(<4 x float> addrspace(1)* %a, <4 x float> %x) {
244  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
245  %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %a, i32 %id
246  %load = load <4 x float>, <4 x float> addrspace(1)* %gep, align 16
247  %mul = fmul <4 x float> %load, %x
248  store <4 x float> %mul, <4 x float> addrspace(1)* %gep, align 16
249  ret void
250}
251
252; GCN-LABEL: {{^}}fmul_v32_vs:
253; GFX900-COUNT-32: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
254; GFX90A-COUNT-16: v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
255define amdgpu_kernel void @fmul_v32_vs(<32 x float> addrspace(1)* %a, <32 x float> %x) {
256  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
257  %gep = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %a, i32 %id
258  %load = load <32 x float>, <32 x float> addrspace(1)* %gep, align 128
259  %mul = fmul <32 x float> %load, %x
260  store <32 x float> %mul, <32 x float> addrspace(1)* %gep, align 128
261  ret void
262}
263
264; GCN-LABEL: {{^}}fmul_v2_v_imm:
265; GCN:            s_mov_b32 s[[K:[0-9]+]], 0x42c80000
266; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, s[[K]], v{{[0-9]+}}
267; GFX90A:         v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[K]]:{{[0-9:]+}}] op_sel_hi:[1,0]{{$}}
268define amdgpu_kernel void @fmul_v2_v_imm(<2 x float> addrspace(1)* %a) {
269  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
270  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
271  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
272  %mul = fmul <2 x float> %load, <float 100.0, float 100.0>
273  store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
274  ret void
275}
276
277; GCN-LABEL: {{^}}fmul_v2_v_v_splat:
278; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v0
279; GFX90A:         v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[0:1] op_sel_hi:[1,0]{{$}}
280define amdgpu_kernel void @fmul_v2_v_v_splat(<2 x float> addrspace(1)* %a) {
281  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
282  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
283  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
284  %fid = bitcast i32 %id to float
285  %tmp1 = insertelement <2 x float> undef, float %fid, i64 0
286  %k = insertelement <2 x float> %tmp1, float %fid, i64 1
287  %mul = fmul <2 x float> %load, %k
288  store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
289  ret void
290}
291
292; GCN-LABEL: {{^}}fmul_v2_v_lit_splat:
293; GFX900-COUNT-2: v_mul_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
294; GFX90A:         v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4.0 op_sel_hi:[1,0]{{$}}
295define amdgpu_kernel void @fmul_v2_v_lit_splat(<2 x float> addrspace(1)* %a) {
296  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
297  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
298  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
299  %mul = fmul <2 x float> %load, <float 4.0, float 4.0>
300  store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
301  ret void
302}
303
304; GCN-LABEL: {{^}}fmul_v2_v_unfoldable_lit:
305; GFX900-DAG: v_mul_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
306; GFX900-DAG: v_mul_f32_e32 v{{[0-9]+}}, 0x40400000, v{{[0-9]+}}
307; GFX90A-DAG: s_mov_b32 s{{[0-9]+}}, 4.0
308; GFX90A-DAG: s_mov_b32 s{{[0-9]+}}, 0x40400000
309; GFX90A:     v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
310define amdgpu_kernel void @fmul_v2_v_unfoldable_lit(<2 x float> addrspace(1)* %a) {
311  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
312  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
313  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
314  %mul = fmul <2 x float> %load, <float 4.0, float 3.0>
315  store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
316  ret void
317}
318
319; GCN-LABEL: {{^}}fmul_v2_v_fneg:
320; GFX900-COUNT-2: v_mul_f32_e64 v{{[0-9]+}}, v{{[0-9]+}}, -s{{[0-9]+}}
321; GFX90A:         v_pk_mul_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]{{$}}
322define amdgpu_kernel void @fmul_v2_v_fneg(<2 x float> addrspace(1)* %a, float %x) {
323  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
324  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
325  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
326  %fneg = fsub float -0.0, %x
327  %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
328  %k = insertelement <2 x float> %tmp1, float %fneg, i64 1
329  %mul = fmul <2 x float> %load, %k
330  store <2 x float> %mul, <2 x float> addrspace(1)* %gep, align 8
331  ret void
332}
333
334; GCN-LABEL: {{^}}fma_v2_vv:
335; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
336; GFX90A:         v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
337define amdgpu_kernel void @fma_v2_vv(<2 x float> addrspace(1)* %a) {
338  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
339  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
340  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
341  %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> %load, <2 x float> %load)
342  store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
343  ret void
344}
345
346; GCN-LABEL: {{^}}fma_v2_vs:
347; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
348; GFX90A:         v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
349define amdgpu_kernel void @fma_v2_vs(<2 x float> addrspace(1)* %a, <2 x float> %x) {
350  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
351  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
352  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
353  %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> %x, <2 x float> %x)
354  store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
355  ret void
356}
357
358; GCN-LABEL: {{^}}fma_v4_vs:
359; GFX900-COUNT-4: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
360; GFX90A-COUNT-2: v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
361define amdgpu_kernel void @fma_v4_vs(<4 x float> addrspace(1)* %a, <4 x float> %x) {
362  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
363  %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %a, i32 %id
364  %load = load <4 x float>, <4 x float> addrspace(1)* %gep, align 16
365  %fma = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %load, <4 x float> %x, <4 x float> %x)
366  store <4 x float> %fma, <4 x float> addrspace(1)* %gep, align 16
367  ret void
368}
369
370; GCN-LABEL: {{^}}fma_v32_vs:
371; GFX900-COUNT-32: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
372; GFX90A-COUNT-16: v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
373define amdgpu_kernel void @fma_v32_vs(<32 x float> addrspace(1)* %a, <32 x float> %x) {
374  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
375  %gep = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %a, i32 %id
376  %load = load <32 x float>, <32 x float> addrspace(1)* %gep, align 128
377  %fma = tail call <32 x float> @llvm.fma.v32f32(<32 x float> %load, <32 x float> %x, <32 x float> %x)
378  store <32 x float> %fma, <32 x float> addrspace(1)* %gep, align 128
379  ret void
380}
381
382; GCN-LABEL: {{^}}fma_v2_v_imm:
383; GCN-DAG:        s_mov_b32 s[[K1:[0-9]+]], 0x42c80000
384; GCN-DAG:        v_mov_b32_e32 v[[K2:[0-9]+]], 0x43480000
385; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, s[[K1]], v[[K2]]
386; GFX90A:         v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{\[}}[[K1]]:{{[0-9:]+}}], v{{\[}}[[K2]]:{{[0-9:]+}}] op_sel_hi:[1,0,0]{{$}}
387define amdgpu_kernel void @fma_v2_v_imm(<2 x float> addrspace(1)* %a) {
388  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
389  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
390  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
391  %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> <float 100.0, float 100.0>, <2 x float> <float 200.0, float 200.0>)
392  store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
393  ret void
394}
395
396; GCN-LABEL: {{^}}fma_v2_v_v_splat:
397; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, v0, v0
398; GFX90A:         v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[0:1], v[0:1] op_sel_hi:[1,0,0]{{$}}
399define amdgpu_kernel void @fma_v2_v_v_splat(<2 x float> addrspace(1)* %a) {
400  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
401  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
402  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
403  %fid = bitcast i32 %id to float
404  %tmp1 = insertelement <2 x float> undef, float %fid, i64 0
405  %k = insertelement <2 x float> %tmp1, float %fid, i64 1
406  %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> %k, <2 x float> %k)
407  store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
408  ret void
409}
410
411; GCN-LABEL: {{^}}fma_v2_v_lit_splat:
412; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, 4.0, 1.0
413; GFX90A:         v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4.0, 1.0 op_sel_hi:[1,0,0]{{$}}
414define amdgpu_kernel void @fma_v2_v_lit_splat(<2 x float> addrspace(1)* %a) {
415  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
416  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
417  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
418  %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> <float 4.0, float 4.0>, <2 x float> <float 1.0, float 1.0>)
419  store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
420  ret void
421}
422
423; GCN-LABEL: {{^}}fma_v2_v_unfoldable_lit:
424; GCN-DAG:    s_mov_b32 s{{[0-9]+}}, 0x40400000
425; GFX900-DAG: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, 4.0, 1.0
426; GFX900-DAG: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}, 2.0
427; GFX90A-DAG: s_mov_b32 s{{[0-9]+}}, 4.0
428; GFX90A-DAG: v_mov_b32_e32 v{{[0-9]+}}, 1.0
429; GFX90A-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0
430; GFX90A:     v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}], v[{{[0-9:]+}}]{{$}}
431define amdgpu_kernel void @fma_v2_v_unfoldable_lit(<2 x float> addrspace(1)* %a) {
432  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
433  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
434  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
435  %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> <float 4.0, float 3.0>, <2 x float> <float 1.0, float 2.0>)
436  store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
437  ret void
438}
439
440; GCN-LABEL: {{^}}fma_v2_v_fneg:
441; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, -s{{[0-9]+}}, -s{{[0-9]+}}
442; GFX90A:         v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}], s[{{[0-9:]+}}] op_sel_hi:[1,0,0] neg_lo:[0,1,1] neg_hi:[0,1,1]{{$}}
443define amdgpu_kernel void @fma_v2_v_fneg(<2 x float> addrspace(1)* %a, float %x) {
444  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
445  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
446  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
447  %fneg = fsub float -0.0, %x
448  %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
449  %k = insertelement <2 x float> %tmp1, float %fneg, i64 1
450  %fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> %k, <2 x float> %k)
451  store <2 x float> %fma, <2 x float> addrspace(1)* %gep, align 8
452  ret void
453}
454
455; GCN-LABEL: {{^}}add_vector_neg_bitcast_scalar_lo:
456; GFX900-COUNT-2: v_sub_f32_e32
457; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]
458define amdgpu_kernel void @add_vector_neg_bitcast_scalar_lo(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %lds, float addrspace(3)* %arg2) {
459bb:
460  %vec0 = load volatile <2 x float>, <2 x float> addrspace(3)* %lds, align 4
461  %scalar0 = load volatile float, float addrspace(3)* %arg2, align 4
462  %neg.scalar0 = fsub float -0.0, %scalar0
463
464  %neg.scalar0.vec = insertelement <2 x float> undef, float %neg.scalar0, i32 0
465  %neg.scalar0.broadcast = shufflevector <2 x float> %neg.scalar0.vec, <2 x float> undef, <2 x i32> zeroinitializer
466
467  %result = fadd <2 x float> %vec0, %neg.scalar0.broadcast
468  store <2 x float> %result, <2 x float> addrspace(1)* %out, align 4
469  ret void
470}
471
472; GCN-LABEL: {{^}}fma_vector_vector_neg_scalar_lo_scalar_hi:
473; GFX900-COUNT-2: v_fma_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}
474; GFX90A:         v_pk_fma_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] neg_lo:[0,0,1] neg_hi:[0,0,1]
475define amdgpu_kernel void @fma_vector_vector_neg_scalar_lo_scalar_hi(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %lds, float addrspace(3)* %arg2) {
476bb:
477  %lds.gep1 = getelementptr inbounds <2 x float>, <2 x float> addrspace(3)* %lds, i32 1
478  %arg2.gep = getelementptr inbounds float, float addrspace(3)* %arg2, i32 2
479
480  %vec0 = load volatile <2 x float>, <2 x float> addrspace(3)* %lds, align 4
481  %vec1 = load volatile <2 x float>, <2 x float> addrspace(3)* %lds.gep1, align 4
482
483  %scalar0 = load volatile float, float addrspace(3)* %arg2, align 4
484  %scalar1 = load volatile float, float addrspace(3)* %arg2.gep, align 4
485
486  %vec.ins0 = insertelement <2 x float> undef, float %scalar0, i32 0
487  %vec2 = insertelement <2 x float> %vec.ins0, float %scalar1, i32 1
488  %neg.vec2 = fsub <2 x float> <float -0.0, float -0.0>, %vec2
489
490  %result = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %neg.vec2)
491  store <2 x float> %result, <2 x float> addrspace(1)* %out, align 4
492  ret void
493}
494
495; GCN-LABEL: {{^}}shuffle_add_f32:
496; GFX900-COUNT-2: v_add_f32_e32
497; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] op_sel:[0,1] op_sel_hi:[1,0]{{$}}
498define amdgpu_kernel void @shuffle_add_f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %lds) #0 {
499bb:
500  %vec0 = load volatile <2 x float>, <2 x float> addrspace(3)* %lds, align 8
501  %lds.gep1 = getelementptr inbounds <2 x float>, <2 x float> addrspace(3)* %lds, i32 1
502  %vec1 = load volatile <2 x float>, <2 x float> addrspace(3)* %lds.gep1, align 8
503  %vec1.swap = shufflevector <2 x float> %vec1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
504  %result = fadd <2 x float> %vec0, %vec1.swap
505  store <2 x float> %result, <2 x float> addrspace(1)* %out, align 8
506  ret void
507}
508
509; GCN-LABEL: {{^}}shuffle_neg_add_f32:
510; GFX900-COUNT-2: v_sub_f32_e32
511; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]{{$}}
512define amdgpu_kernel void @shuffle_neg_add_f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %lds) #0 {
513bb:
514  %vec0 = load volatile <2 x float>, <2 x float> addrspace(3)* %lds, align 8
515  %lds.gep1 = getelementptr inbounds <2 x float>, <2 x float> addrspace(3)* %lds, i32 1
516  %f32 = load volatile float, float addrspace(3)* undef, align 8
517  %vec1 = load volatile <2 x float>, <2 x float> addrspace(3)* %lds.gep1, align 8
518  %vec1.neg = fsub <2 x float> <float -0.0, float -0.0>, %vec1
519  %vec1.neg.swap = shufflevector <2 x float> %vec1.neg, <2 x float> undef, <2 x i32> <i32 1, i32 0>
520  %result = fadd <2 x float> %vec0, %vec1.neg.swap
521  store <2 x float> %result, <2 x float> addrspace(1)* %out, align 8
522  ret void
523}
524
525; GCN-LABEL: {{^}}fadd_fadd_fsub:
526; GFX900: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, 0
527; GFX900: v_add_f32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
528; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 0 op_sel_hi:[1,0]
529; GFX90A: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0 op_sel_hi:[1,0]
530define amdgpu_kernel void @fadd_fadd_fsub(<2 x float> %arg) {
531bb:
532  %i12 = fadd <2 x float> zeroinitializer, %arg
533  %shift8 = shufflevector <2 x float> %i12, <2 x float> undef, <2 x i32> <i32 1, i32 undef>
534  %i13 = fadd <2 x float> zeroinitializer, %shift8
535  %i14 = shufflevector <2 x float> %arg, <2 x float> %i13, <2 x i32> <i32 0, i32 2>
536  %i15 = fsub <2 x float> %i14, zeroinitializer
537  store <2 x float> %i15, <2 x float>* undef
538  ret void
539}
540
541; GCN-LABEL: {{^}}fadd_shuffle_v4:
542; GFX900-COUNT-4: v_add_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
543; GFX90A-COUNT-2: v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] op_sel_hi:[1,0]
544define amdgpu_kernel void @fadd_shuffle_v4(<4 x float> addrspace(1)* %arg) {
545bb:
546  %tid = call i32 @llvm.amdgcn.workitem.id.x()
547  %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %arg, i32 %tid
548  %in.1 = load <4 x float>, <4 x float> addrspace(1)* %gep
549  %shuf = shufflevector <4 x float> %in.1, <4 x float> undef, <4 x i32> zeroinitializer
550  %add.1 = fadd <4 x float> %in.1, %shuf
551  store <4 x float> %add.1, <4 x float> addrspace(1)* %gep
552  ret void
553}
554
555; GCN-LABEL: {{^}}fneg_v2f32_vec:
556; GFX900:         s_brev_b32 [[SIGN:s[0-9]+]], 1
557; GFX900-COUNT-2: v_xor_b32_e32 v{{[0-9]+}}, [[SIGN]], v{{[0-9]+}}
558; GFX90A:         v_pk_add_f32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0 neg_lo:[1,1] neg_hi:[1,1]{{$}}
559define amdgpu_kernel void @fneg_v2f32_vec(<2 x float> addrspace(1)* %a) {
560  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
561  %gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %a, i32 %id
562  %load = load <2 x float>, <2 x float> addrspace(1)* %gep, align 8
563  %fneg = fsub <2 x float> <float -0.0, float -0.0>, %load
564  store <2 x float> %fneg, <2 x float> addrspace(1)* %gep, align 8
565  ret void
566}
567
568; GCN-LABEL: {{^}}fneg_v2f32_scalar:
569; GCN:         s_brev_b32 [[SIGN:s[0-9]+]], 1
570; GCN-COUNT-2: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[SIGN]]
571define amdgpu_kernel void @fneg_v2f32_scalar(<2 x float> addrspace(1)* %a, <2 x float> %x) {
572  %fneg = fsub <2 x float> <float -0.0, float -0.0>, %x
573  store <2 x float> %fneg, <2 x float> addrspace(1)* %a, align 8
574  ret void
575}
576
577declare i32 @llvm.amdgcn.workitem.id.x()
578declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)
579declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
580declare <32 x float> @llvm.fma.v32f32(<32 x float>, <32 x float>, <32 x float>)
581