1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5
6; ===================================================================================
7; V_OR3_B32
8; ===================================================================================
9
10define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) {
11; VI-LABEL: or3:
12; VI:       ; %bb.0:
13; VI-NEXT:    v_or_b32_e32 v0, v0, v1
14; VI-NEXT:    v_or_b32_e32 v0, v0, v2
15; VI-NEXT:    ; return to shader part epilog
16;
17; GFX9-LABEL: or3:
18; GFX9:       ; %bb.0:
19; GFX9-NEXT:    v_or3_b32 v0, v0, v1, v2
20; GFX9-NEXT:    ; return to shader part epilog
21;
22; GFX10-LABEL: or3:
23; GFX10:       ; %bb.0:
24; GFX10-NEXT:    v_or3_b32 v0, v0, v1, v2
25; GFX10-NEXT:    ; implicit-def: $vcc_hi
26; GFX10-NEXT:    ; return to shader part epilog
27  %x = or i32 %a, %b
28  %result = or i32 %x, %c
29  %bc = bitcast i32 %result to float
30  ret float %bc
31}
32
33; ThreeOp instruction variant not used due to Constant Bus Limitations
34; TODO: with reassociation it is possible to replace a v_or_b32_e32 with an s_or_b32
35define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
36; VI-LABEL: or3_vgpr_a:
37; VI:       ; %bb.0:
38; VI-NEXT:    v_or_b32_e32 v0, s2, v0
39; VI-NEXT:    v_or_b32_e32 v0, s3, v0
40; VI-NEXT:    ; return to shader part epilog
41;
42; GFX9-LABEL: or3_vgpr_a:
43; GFX9:       ; %bb.0:
44; GFX9-NEXT:    v_or_b32_e32 v0, s2, v0
45; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
46; GFX9-NEXT:    ; return to shader part epilog
47;
48; GFX10-LABEL: or3_vgpr_a:
49; GFX10:       ; %bb.0:
50; GFX10-NEXT:    v_or3_b32 v0, v0, s2, s3
51; GFX10-NEXT:    ; implicit-def: $vcc_hi
52; GFX10-NEXT:    ; return to shader part epilog
53  %x = or i32 %a, %b
54  %result = or i32 %x, %c
55  %bc = bitcast i32 %result to float
56  ret float %bc
57}
58
59define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
60; VI-LABEL: or3_vgpr_all2:
61; VI:       ; %bb.0:
62; VI-NEXT:    v_or_b32_e32 v1, v1, v2
63; VI-NEXT:    v_or_b32_e32 v0, v0, v1
64; VI-NEXT:    ; return to shader part epilog
65;
66; GFX9-LABEL: or3_vgpr_all2:
67; GFX9:       ; %bb.0:
68; GFX9-NEXT:    v_or3_b32 v0, v1, v2, v0
69; GFX9-NEXT:    ; return to shader part epilog
70;
71; GFX10-LABEL: or3_vgpr_all2:
72; GFX10:       ; %bb.0:
73; GFX10-NEXT:    v_or3_b32 v0, v1, v2, v0
74; GFX10-NEXT:    ; implicit-def: $vcc_hi
75; GFX10-NEXT:    ; return to shader part epilog
76  %x = or i32 %b, %c
77  %result = or i32 %a, %x
78  %bc = bitcast i32 %result to float
79  ret float %bc
80}
81
82define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
83; VI-LABEL: or3_vgpr_bc:
84; VI:       ; %bb.0:
85; VI-NEXT:    v_or_b32_e32 v0, s2, v0
86; VI-NEXT:    v_or_b32_e32 v0, v0, v1
87; VI-NEXT:    ; return to shader part epilog
88;
89; GFX9-LABEL: or3_vgpr_bc:
90; GFX9:       ; %bb.0:
91; GFX9-NEXT:    v_or3_b32 v0, s2, v0, v1
92; GFX9-NEXT:    ; return to shader part epilog
93;
94; GFX10-LABEL: or3_vgpr_bc:
95; GFX10:       ; %bb.0:
96; GFX10-NEXT:    v_or3_b32 v0, s2, v0, v1
97; GFX10-NEXT:    ; implicit-def: $vcc_hi
98; GFX10-NEXT:    ; return to shader part epilog
99  %x = or i32 %a, %b
100  %result = or i32 %x, %c
101  %bc = bitcast i32 %result to float
102  ret float %bc
103}
104
105define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
106; VI-LABEL: or3_vgpr_const:
107; VI:       ; %bb.0:
108; VI-NEXT:    v_or_b32_e32 v0, v1, v0
109; VI-NEXT:    v_or_b32_e32 v0, 64, v0
110; VI-NEXT:    ; return to shader part epilog
111;
112; GFX9-LABEL: or3_vgpr_const:
113; GFX9:       ; %bb.0:
114; GFX9-NEXT:    v_or3_b32 v0, v1, v0, 64
115; GFX9-NEXT:    ; return to shader part epilog
116;
117; GFX10-LABEL: or3_vgpr_const:
118; GFX10:       ; %bb.0:
119; GFX10-NEXT:    v_or3_b32 v0, v1, v0, 64
120; GFX10-NEXT:    ; implicit-def: $vcc_hi
121; GFX10-NEXT:    ; return to shader part epilog
122  %x = or i32 64, %b
123  %result = or i32 %x, %a
124  %bc = bitcast i32 %result to float
125  ret float %bc
126}
127