1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4
5; ===================================================================================
6; V_OR3_B32
7; ===================================================================================
8
9define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) {
10; VI-LABEL: or3:
11; VI:       ; %bb.0:
12; VI-NEXT:    v_or_b32_e32 v0, v0, v1
13; VI-NEXT:    v_or_b32_e32 v0, v0, v2
14; VI-NEXT:    ; return to shader part epilog
15;
16; GFX9-LABEL: or3:
17; GFX9:       ; %bb.0:
18; GFX9-NEXT:    v_or3_b32 v0, v0, v1, v2
19; GFX9-NEXT:    ; return to shader part epilog
20  %x = or i32 %a, %b
21  %result = or i32 %x, %c
22  %bc = bitcast i32 %result to float
23  ret float %bc
24}
25
26; ThreeOp instruction variant not used due to Constant Bus Limitations
27; TODO: with reassociation it is possible to replace a v_or_b32_e32 with an s_or_b32
28define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
29; VI-LABEL: or3_vgpr_a:
30; VI:       ; %bb.0:
31; VI-NEXT:    v_or_b32_e32 v0, s2, v0
32; VI-NEXT:    v_or_b32_e32 v0, s3, v0
33; VI-NEXT:    ; return to shader part epilog
34;
35; GFX9-LABEL: or3_vgpr_a:
36; GFX9:       ; %bb.0:
37; GFX9-NEXT:    v_or_b32_e32 v0, s2, v0
38; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
39; GFX9-NEXT:    ; return to shader part epilog
40  %x = or i32 %a, %b
41  %result = or i32 %x, %c
42  %bc = bitcast i32 %result to float
43  ret float %bc
44}
45
46define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
47; VI-LABEL: or3_vgpr_all2:
48; VI:       ; %bb.0:
49; VI-NEXT:    v_or_b32_e32 v1, v1, v2
50; VI-NEXT:    v_or_b32_e32 v0, v0, v1
51; VI-NEXT:    ; return to shader part epilog
52;
53; GFX9-LABEL: or3_vgpr_all2:
54; GFX9:       ; %bb.0:
55; GFX9-NEXT:    v_or3_b32 v0, v1, v2, v0
56; GFX9-NEXT:    ; return to shader part epilog
57  %x = or i32 %b, %c
58  %result = or i32 %a, %x
59  %bc = bitcast i32 %result to float
60  ret float %bc
61}
62
63define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
64; VI-LABEL: or3_vgpr_bc:
65; VI:       ; %bb.0:
66; VI-NEXT:    v_or_b32_e32 v0, s2, v0
67; VI-NEXT:    v_or_b32_e32 v0, v0, v1
68; VI-NEXT:    ; return to shader part epilog
69;
70; GFX9-LABEL: or3_vgpr_bc:
71; GFX9:       ; %bb.0:
72; GFX9-NEXT:    v_or3_b32 v0, s2, v0, v1
73; GFX9-NEXT:    ; return to shader part epilog
74  %x = or i32 %a, %b
75  %result = or i32 %x, %c
76  %bc = bitcast i32 %result to float
77  ret float %bc
78}
79
80define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
81; VI-LABEL: or3_vgpr_const:
82; VI:       ; %bb.0:
83; VI-NEXT:    v_or_b32_e32 v0, v1, v0
84; VI-NEXT:    v_or_b32_e32 v0, 64, v0
85; VI-NEXT:    ; return to shader part epilog
86;
87; GFX9-LABEL: or3_vgpr_const:
88; GFX9:       ; %bb.0:
89; GFX9-NEXT:    v_or3_b32 v0, v1, v0, 64
90; GFX9-NEXT:    ; return to shader part epilog
91  %x = or i32 64, %b
92  %result = or i32 %x, %a
93  %bc = bitcast i32 %result to float
94  ret float %bc
95}
96