1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}negated_cond:
4; GCN: BB0_1:
5; GCN:   v_cmp_eq_u32_e64 [[CC:[^,]+]],
6; GCN: BB0_2:
7; GCN-NOT: v_cndmask_b32
8; GCN-NOT: v_cmp
9; GCN:   s_andn2_b64 vcc, exec, [[CC]]
10; GCN:   s_cbranch_vccnz BB0_4
11define amdgpu_kernel void @negated_cond(i32 addrspace(1)* %arg1) {
12bb:
13  br label %bb1
14
15bb1:
16  %tmp1 = load i32, i32 addrspace(1)* %arg1
17  %tmp2 = icmp eq i32 %tmp1, 0
18  br label %bb2
19
20bb2:
21  %tmp3 = phi i32 [ 0, %bb1 ], [ %tmp6, %bb4 ]
22  %tmp4 = shl i32 %tmp3, 5
23  br i1 %tmp2, label %bb3, label %bb4
24
25bb3:
26  %tmp5 = add i32 %tmp4, 1
27  br label %bb4
28
29bb4:
30  %tmp6 = phi i32 [ %tmp5, %bb3 ], [ %tmp4, %bb2 ]
31  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp6
32  store i32 0, i32 addrspace(1)* %gep
33  %tmp7 = icmp eq i32 %tmp6, 32
34  br i1 %tmp7, label %bb1, label %bb2
35}
36
37; GCN-LABEL: {{^}}negated_cond_dominated_blocks:
38; GCN:   v_cmp_eq_u32_e64 [[CC:[^,]+]],
39; GCN: BB1_1:
40; GCN-NOT: v_cndmask_b32
41; GCN-NOT: v_cmp
42; GCN:   s_andn2_b64 vcc, exec, [[CC]]
43; GCN:   s_cbranch_vccz BB1_3
44define amdgpu_kernel void @negated_cond_dominated_blocks(i32 addrspace(1)* %arg1) {
45bb:
46  br label %bb2
47
48bb2:
49  %tmp1 = load i32, i32 addrspace(1)* %arg1
50  %tmp2 = icmp eq i32 %tmp1, 0
51  br label %bb4
52
53bb3:
54  ret void
55
56bb4:
57  %tmp3 = phi i32 [ 0, %bb2 ], [ %tmp7, %bb7 ]
58  %tmp4 = shl i32 %tmp3, 5
59  br i1 %tmp2, label %bb5, label %bb6
60
61bb5:
62  %tmp5 = add i32 %tmp4, 1
63  br label %bb7
64
65bb6:
66  %tmp6 = add i32 %tmp3, 1
67  br label %bb7
68
69bb7:
70  %tmp7 = phi i32 [ %tmp5, %bb5 ], [ %tmp6, %bb6 ]
71  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp7
72  store i32 0, i32 addrspace(1)* %gep
73  %tmp8 = icmp eq i32 %tmp7, 32
74  br i1 %tmp8, label %bb3, label %bb4
75}
76