1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=DEFAULTSIZE,MUBUF %s
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -amdgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=ASSUME1024,MUBUF %s
4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=DEFAULTSIZE,FLATSCR %s
5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -amdgpu-enable-flat-scratch -amdgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=ASSUME1024,FLATSCR %s
6
7; FIXME: Generated test checks do not check metadata at the end of the
8; function, so this also includes manually added checks.
9
10; Test that we can select a statically sized alloca outside of the
11; entry block.
12
13; FIXME: FunctionLoweringInfo unhelpfully doesn't preserve an
14; alignment less than the stack alignment.
15define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) {
16; MUBUF-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
17; MUBUF:       ; %bb.0: ; %entry
18; MUBUF-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
19; MUBUF-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
20; MUBUF-NEXT:    s_add_u32 s0, s0, s9
21; MUBUF-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x8
22; MUBUF-NEXT:    s_addc_u32 s1, s1, 0
23; MUBUF-NEXT:    s_movk_i32 s32, 0x400
24; MUBUF-NEXT:    s_mov_b32 s33, 0
25; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
26; MUBUF-NEXT:    s_cmp_lg_u32 s8, 0
27; MUBUF-NEXT:    s_cbranch_scc1 BB0_3
28; MUBUF-NEXT:  ; %bb.1: ; %bb.0
29; MUBUF-NEXT:    s_cmp_lg_u32 s9, 0
30; MUBUF-NEXT:    s_cbranch_scc1 BB0_3
31; MUBUF-NEXT:  ; %bb.2: ; %bb.1
32; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
33; MUBUF-NEXT:    s_lshl_b32 s7, s10, 2
34; MUBUF-NEXT:    s_mov_b32 s32, s6
35; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
36; MUBUF-NEXT:    v_mov_b32_e32 v1, 0
37; MUBUF-NEXT:    v_mov_b32_e32 v3, 1
38; MUBUF-NEXT:    s_add_i32 s6, s6, s7
39; MUBUF-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
40; MUBUF-NEXT:    buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
41; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
42; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
43; MUBUF-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
44; MUBUF-NEXT:    s_waitcnt vmcnt(0)
45; MUBUF-NEXT:    v_add_u32_e32 v0, v2, v0
46; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
47; MUBUF-NEXT:    global_store_dword v1, v0, s[4:5]
48; MUBUF-NEXT:  BB0_3: ; %bb.2
49; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
50; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
51; MUBUF-NEXT:    s_waitcnt vmcnt(0)
52; MUBUF-NEXT:    s_endpgm
53;
54; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
55; FLATSCR:       ; %bb.0: ; %entry
56; FLATSCR-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
57; FLATSCR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x8
58; FLATSCR-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
59; FLATSCR-NEXT:    s_mov_b32 s32, 16
60; FLATSCR-NEXT:    s_mov_b32 s33, 0
61; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
62; FLATSCR-NEXT:    s_cmp_lg_u32 s4, 0
63; FLATSCR-NEXT:    s_cbranch_scc1 BB0_3
64; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
65; FLATSCR-NEXT:    s_cmp_lg_u32 s5, 0
66; FLATSCR-NEXT:    s_cbranch_scc1 BB0_3
67; FLATSCR-NEXT:  ; %bb.2: ; %bb.1
68; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
69; FLATSCR-NEXT:    v_mov_b32_e32 v1, 0
70; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
71; FLATSCR-NEXT:    s_lshl_b32 s3, s6, 2
72; FLATSCR-NEXT:    s_mov_b32 s32, s2
73; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[1:2], s2
74; FLATSCR-NEXT:    s_add_i32 s2, s2, s3
75; FLATSCR-NEXT:    scratch_load_dword v2, off, s2
76; FLATSCR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
77; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
78; FLATSCR-NEXT:    v_add_u32_e32 v0, v2, v0
79; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
80; FLATSCR-NEXT:    global_store_dword v1, v0, s[0:1]
81; FLATSCR-NEXT:  BB0_3: ; %bb.2
82; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
83; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
84; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
85; FLATSCR-NEXT:    s_endpgm
86
87entry:
88  %cond0 = icmp eq i32 %arg.cond0, 0
89  br i1 %cond0, label %bb.0, label %bb.2
90
91bb.0:
92  %alloca = alloca [16 x i32], align 4, addrspace(5)
93  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
94  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
95  %cond1 = icmp eq i32 %arg.cond1, 0
96  br i1 %cond1, label %bb.1, label %bb.2
97
98bb.1:
99  ; Use the alloca outside of the defining block.
100  store i32 0, i32 addrspace(5)* %gep0
101  store i32 1, i32 addrspace(5)* %gep1
102  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
103  %load = load i32, i32 addrspace(5)* %gep2
104  %tid = call i32 @llvm.amdgcn.workitem.id.x()
105  %add = add i32 %load, %tid
106  store i32 %add, i32 addrspace(1)* %out
107  br label %bb.2
108
109bb.2:
110  store volatile i32 0, i32 addrspace(1)* undef
111  ret void
112}
113; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4112
114; DEFAULTSIZE: ; ScratchSize: 4112
115
116; ASSUME1024: .amdhsa_private_segment_fixed_size 1040
117; ASSUME1024: ; ScratchSize: 1040
118
119define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(i32 addrspace(1)* %out, i32 %arg.cond, i32 %in) {
120; MUBUF-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
121; MUBUF:       ; %bb.0: ; %entry
122; MUBUF-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
123; MUBUF-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
124; MUBUF-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
125; MUBUF-NEXT:    s_add_u32 s0, s0, s9
126; MUBUF-NEXT:    s_addc_u32 s1, s1, 0
127; MUBUF-NEXT:    s_movk_i32 s32, 0x1000
128; MUBUF-NEXT:    s_mov_b32 s33, 0
129; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
130; MUBUF-NEXT:    s_cmp_lg_u32 s6, 0
131; MUBUF-NEXT:    s_cbranch_scc1 BB1_2
132; MUBUF-NEXT:  ; %bb.1: ; %bb.0
133; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
134; MUBUF-NEXT:    s_and_b32 s6, s6, 0xfffff000
135; MUBUF-NEXT:    s_lshl_b32 s7, s7, 2
136; MUBUF-NEXT:    s_mov_b32 s32, s6
137; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
138; MUBUF-NEXT:    v_mov_b32_e32 v1, 0
139; MUBUF-NEXT:    v_mov_b32_e32 v3, 1
140; MUBUF-NEXT:    s_add_i32 s6, s6, s7
141; MUBUF-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
142; MUBUF-NEXT:    buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
143; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
144; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
145; MUBUF-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
146; MUBUF-NEXT:    s_waitcnt vmcnt(0)
147; MUBUF-NEXT:    v_add_u32_e32 v0, v2, v0
148; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
149; MUBUF-NEXT:    global_store_dword v1, v0, s[4:5]
150; MUBUF-NEXT:  BB1_2: ; %bb.1
151; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
152; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
153; MUBUF-NEXT:    s_waitcnt vmcnt(0)
154; MUBUF-NEXT:    s_endpgm
155;
156; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
157; FLATSCR:       ; %bb.0: ; %entry
158; FLATSCR-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
159; FLATSCR-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
160; FLATSCR-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x8
161; FLATSCR-NEXT:    s_mov_b32 s32, 64
162; FLATSCR-NEXT:    s_mov_b32 s33, 0
163; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
164; FLATSCR-NEXT:    s_cmp_lg_u32 s2, 0
165; FLATSCR-NEXT:    s_cbranch_scc1 BB1_2
166; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
167; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
168; FLATSCR-NEXT:    s_and_b32 s2, s2, 0xfffff000
169; FLATSCR-NEXT:    v_mov_b32_e32 v1, 0
170; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
171; FLATSCR-NEXT:    s_lshl_b32 s3, s3, 2
172; FLATSCR-NEXT:    s_mov_b32 s32, s2
173; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[1:2], s2
174; FLATSCR-NEXT:    s_add_i32 s2, s2, s3
175; FLATSCR-NEXT:    scratch_load_dword v2, off, s2
176; FLATSCR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
177; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
178; FLATSCR-NEXT:    v_add_u32_e32 v0, v2, v0
179; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
180; FLATSCR-NEXT:    global_store_dword v1, v0, s[0:1]
181; FLATSCR-NEXT:  BB1_2: ; %bb.1
182; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
183; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
184; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
185; FLATSCR-NEXT:    s_endpgm
186entry:
187  %cond = icmp eq i32 %arg.cond, 0
188  br i1 %cond, label %bb.0, label %bb.1
189
190bb.0:
191  %alloca = alloca [16 x i32], align 64, addrspace(5)
192  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
193  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
194  store i32 0, i32 addrspace(5)* %gep0
195  store i32 1, i32 addrspace(5)* %gep1
196  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
197  %load = load i32, i32 addrspace(5)* %gep2
198  %tid = call i32 @llvm.amdgcn.workitem.id.x()
199  %add = add i32 %load, %tid
200  store i32 %add, i32 addrspace(1)* %out
201  br label %bb.1
202
203bb.1:
204  store volatile i32 0, i32 addrspace(1)* undef
205  ret void
206}
207
208; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4160
209; DEFAULTSIZE: ; ScratchSize: 4160
210
211; ASSUME1024: .amdhsa_private_segment_fixed_size 1088
212; ASSUME1024: ; ScratchSize: 1088
213
214
215define void @func_non_entry_block_static_alloca_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) {
216; MUBUF-LABEL: func_non_entry_block_static_alloca_align4:
217; MUBUF:       ; %bb.0: ; %entry
218; MUBUF-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
219; MUBUF-NEXT:    s_mov_b32 s7, s33
220; MUBUF-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
221; MUBUF-NEXT:    s_mov_b32 s33, s32
222; MUBUF-NEXT:    s_addk_i32 s32, 0x400
223; MUBUF-NEXT:    s_and_saveexec_b64 s[4:5], vcc
224; MUBUF-NEXT:    s_cbranch_execz BB2_3
225; MUBUF-NEXT:  ; %bb.1: ; %bb.0
226; MUBUF-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
227; MUBUF-NEXT:    s_and_b64 exec, exec, vcc
228; MUBUF-NEXT:    s_cbranch_execz BB2_3
229; MUBUF-NEXT:  ; %bb.2: ; %bb.1
230; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
231; MUBUF-NEXT:    v_mov_b32_e32 v2, 0
232; MUBUF-NEXT:    v_mov_b32_e32 v3, s6
233; MUBUF-NEXT:    buffer_store_dword v2, v3, s[0:3], 0 offen
234; MUBUF-NEXT:    v_mov_b32_e32 v2, 1
235; MUBUF-NEXT:    buffer_store_dword v2, v3, s[0:3], 0 offen offset:4
236; MUBUF-NEXT:    v_lshl_add_u32 v2, v4, 2, s6
237; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
238; MUBUF-NEXT:    v_and_b32_e32 v3, 0x3ff, v5
239; MUBUF-NEXT:    s_mov_b32 s32, s6
240; MUBUF-NEXT:    s_waitcnt vmcnt(0)
241; MUBUF-NEXT:    v_add_u32_e32 v2, v2, v3
242; MUBUF-NEXT:    global_store_dword v[0:1], v2, off
243; MUBUF-NEXT:  BB2_3: ; %bb.2
244; MUBUF-NEXT:    s_or_b64 exec, exec, s[4:5]
245; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
246; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
247; MUBUF-NEXT:    s_waitcnt vmcnt(0)
248; MUBUF-NEXT:    s_addk_i32 s32, 0xfc00
249; MUBUF-NEXT:    s_mov_b32 s33, s7
250; MUBUF-NEXT:    s_setpc_b64 s[30:31]
251;
252; FLATSCR-LABEL: func_non_entry_block_static_alloca_align4:
253; FLATSCR:       ; %bb.0: ; %entry
254; FLATSCR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
255; FLATSCR-NEXT:    s_mov_b32 s3, s33
256; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
257; FLATSCR-NEXT:    s_mov_b32 s33, s32
258; FLATSCR-NEXT:    s_add_i32 s32, s32, 16
259; FLATSCR-NEXT:    s_and_saveexec_b64 s[0:1], vcc
260; FLATSCR-NEXT:    s_cbranch_execz BB2_3
261; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
262; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
263; FLATSCR-NEXT:    s_and_b64 exec, exec, vcc
264; FLATSCR-NEXT:    s_cbranch_execz BB2_3
265; FLATSCR-NEXT:  ; %bb.2: ; %bb.1
266; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
267; FLATSCR-NEXT:    v_mov_b32_e32 v2, 0
268; FLATSCR-NEXT:    v_mov_b32_e32 v3, 1
269; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[2:3], s2
270; FLATSCR-NEXT:    v_lshl_add_u32 v2, v4, 2, s2
271; FLATSCR-NEXT:    scratch_load_dword v2, v2, off
272; FLATSCR-NEXT:    v_and_b32_e32 v3, 0x3ff, v5
273; FLATSCR-NEXT:    s_mov_b32 s32, s2
274; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
275; FLATSCR-NEXT:    v_add_u32_e32 v2, v2, v3
276; FLATSCR-NEXT:    global_store_dword v[0:1], v2, off
277; FLATSCR-NEXT:  BB2_3: ; %bb.2
278; FLATSCR-NEXT:    s_or_b64 exec, exec, s[0:1]
279; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
280; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
281; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
282; FLATSCR-NEXT:    s_add_i32 s32, s32, -16
283; FLATSCR-NEXT:    s_mov_b32 s33, s3
284; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
285
286entry:
287  %cond0 = icmp eq i32 %arg.cond0, 0
288  br i1 %cond0, label %bb.0, label %bb.2
289
290bb.0:
291  %alloca = alloca [16 x i32], align 4, addrspace(5)
292  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
293  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
294  %cond1 = icmp eq i32 %arg.cond1, 0
295  br i1 %cond1, label %bb.1, label %bb.2
296
297bb.1:
298  ; Use the alloca outside of the defining block.
299  store i32 0, i32 addrspace(5)* %gep0
300  store i32 1, i32 addrspace(5)* %gep1
301  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
302  %load = load i32, i32 addrspace(5)* %gep2
303  %tid = call i32 @llvm.amdgcn.workitem.id.x()
304  %add = add i32 %load, %tid
305  store i32 %add, i32 addrspace(1)* %out
306  br label %bb.2
307
308bb.2:
309  store volatile i32 0, i32 addrspace(1)* undef
310  ret void
311}
312
313define void @func_non_entry_block_static_alloca_align64(i32 addrspace(1)* %out, i32 %arg.cond, i32 %in) {
314; MUBUF-LABEL: func_non_entry_block_static_alloca_align64:
315; MUBUF:       ; %bb.0: ; %entry
316; MUBUF-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
317; MUBUF-NEXT:    s_mov_b32 s7, s33
318; MUBUF-NEXT:    s_add_i32 s33, s32, 0xfc0
319; MUBUF-NEXT:    s_and_b32 s33, s33, 0xfffff000
320; MUBUF-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
321; MUBUF-NEXT:    s_addk_i32 s32, 0x2000
322; MUBUF-NEXT:    s_and_saveexec_b64 s[4:5], vcc
323; MUBUF-NEXT:    s_cbranch_execz BB3_2
324; MUBUF-NEXT:  ; %bb.1: ; %bb.0
325; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
326; MUBUF-NEXT:    s_and_b32 s6, s6, 0xfffff000
327; MUBUF-NEXT:    v_mov_b32_e32 v2, 0
328; MUBUF-NEXT:    v_mov_b32_e32 v5, s6
329; MUBUF-NEXT:    buffer_store_dword v2, v5, s[0:3], 0 offen
330; MUBUF-NEXT:    v_mov_b32_e32 v2, 1
331; MUBUF-NEXT:    buffer_store_dword v2, v5, s[0:3], 0 offen offset:4
332; MUBUF-NEXT:    v_lshl_add_u32 v2, v3, 2, s6
333; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
334; MUBUF-NEXT:    v_and_b32_e32 v3, 0x3ff, v4
335; MUBUF-NEXT:    s_mov_b32 s32, s6
336; MUBUF-NEXT:    s_waitcnt vmcnt(0)
337; MUBUF-NEXT:    v_add_u32_e32 v2, v2, v3
338; MUBUF-NEXT:    global_store_dword v[0:1], v2, off
339; MUBUF-NEXT:  BB3_2: ; %bb.1
340; MUBUF-NEXT:    s_or_b64 exec, exec, s[4:5]
341; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
342; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
343; MUBUF-NEXT:    s_waitcnt vmcnt(0)
344; MUBUF-NEXT:    s_addk_i32 s32, 0xe000
345; MUBUF-NEXT:    s_mov_b32 s33, s7
346; MUBUF-NEXT:    s_setpc_b64 s[30:31]
347;
348; FLATSCR-LABEL: func_non_entry_block_static_alloca_align64:
349; FLATSCR:       ; %bb.0: ; %entry
350; FLATSCR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
351; FLATSCR-NEXT:    s_mov_b32 s3, s33
352; FLATSCR-NEXT:    s_add_i32 s33, s32, 63
353; FLATSCR-NEXT:    s_andn2_b32 s33, s33, 63
354; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
355; FLATSCR-NEXT:    s_addk_i32 s32, 0x80
356; FLATSCR-NEXT:    s_and_saveexec_b64 s[0:1], vcc
357; FLATSCR-NEXT:    s_cbranch_execz BB3_2
358; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
359; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
360; FLATSCR-NEXT:    s_and_b32 s2, s2, 0xfffff000
361; FLATSCR-NEXT:    v_mov_b32_e32 v5, 0
362; FLATSCR-NEXT:    v_mov_b32_e32 v6, 1
363; FLATSCR-NEXT:    v_lshl_add_u32 v2, v3, 2, s2
364; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[5:6], s2
365; FLATSCR-NEXT:    scratch_load_dword v2, v2, off
366; FLATSCR-NEXT:    v_and_b32_e32 v3, 0x3ff, v4
367; FLATSCR-NEXT:    s_mov_b32 s32, s2
368; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
369; FLATSCR-NEXT:    v_add_u32_e32 v2, v2, v3
370; FLATSCR-NEXT:    global_store_dword v[0:1], v2, off
371; FLATSCR-NEXT:  BB3_2: ; %bb.1
372; FLATSCR-NEXT:    s_or_b64 exec, exec, s[0:1]
373; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
374; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
375; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
376; FLATSCR-NEXT:    s_addk_i32 s32, 0xff80
377; FLATSCR-NEXT:    s_mov_b32 s33, s3
378; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
379entry:
380  %cond = icmp eq i32 %arg.cond, 0
381  br i1 %cond, label %bb.0, label %bb.1
382
383bb.0:
384  %alloca = alloca [16 x i32], align 64, addrspace(5)
385  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
386  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
387  store i32 0, i32 addrspace(5)* %gep0
388  store i32 1, i32 addrspace(5)* %gep1
389  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
390  %load = load i32, i32 addrspace(5)* %gep2
391  %tid = call i32 @llvm.amdgcn.workitem.id.x()
392  %add = add i32 %load, %tid
393  store i32 %add, i32 addrspace(1)* %out
394  br label %bb.1
395
396bb.1:
397  store volatile i32 0, i32 addrspace(1)* undef
398  ret void
399}
400
401declare i32 @llvm.amdgcn.workitem.id.x() #0
402
403attributes #0 = { nounwind readnone speculatable }
404