1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=DEFAULTSIZE,MUBUF %s
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -amdgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=ASSUME1024,MUBUF %s
4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=DEFAULTSIZE,FLATSCR %s
5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -amdgpu-enable-flat-scratch -amdgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=ASSUME1024,FLATSCR %s
6
7; FIXME: Generated test checks do not check metadata at the end of the
8; function, so this also includes manually added checks.
9
10; Test that we can select a statically sized alloca outside of the
11; entry block.
12
13; FIXME: FunctionLoweringInfo unhelpfully doesn't preserve an
14; alignment less than the stack alignment.
15define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) {
16; MUBUF-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
17; MUBUF:       ; %bb.0: ; %entry
18; MUBUF-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
19; MUBUF-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
20; MUBUF-NEXT:    s_add_u32 s0, s0, s9
21; MUBUF-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x8
22; MUBUF-NEXT:    s_addc_u32 s1, s1, 0
23; MUBUF-NEXT:    s_movk_i32 s32, 0x400
24; MUBUF-NEXT:    s_mov_b32 s33, 0
25; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
26; MUBUF-NEXT:    s_cmp_lg_u32 s8, 0
27; MUBUF-NEXT:    s_cbranch_scc1 BB0_3
28; MUBUF-NEXT:  ; %bb.1: ; %bb.0
29; MUBUF-NEXT:    s_cmp_lg_u32 s9, 0
30; MUBUF-NEXT:    s_cbranch_scc1 BB0_3
31; MUBUF-NEXT:  ; %bb.2: ; %bb.1
32; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
33; MUBUF-NEXT:    s_lshl_b32 s7, s10, 2
34; MUBUF-NEXT:    s_mov_b32 s32, s6
35; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
36; MUBUF-NEXT:    v_mov_b32_e32 v1, 0
37; MUBUF-NEXT:    v_mov_b32_e32 v3, 1
38; MUBUF-NEXT:    s_add_i32 s6, s6, s7
39; MUBUF-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
40; MUBUF-NEXT:    buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
41; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
42; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
43; MUBUF-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
44; MUBUF-NEXT:    s_waitcnt vmcnt(0)
45; MUBUF-NEXT:    v_add_u32_e32 v0, v2, v0
46; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
47; MUBUF-NEXT:    global_store_dword v1, v0, s[4:5]
48; MUBUF-NEXT:  BB0_3: ; %bb.2
49; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
50; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
51; MUBUF-NEXT:    s_waitcnt vmcnt(0)
52; MUBUF-NEXT:    s_endpgm
53;
54; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
55; FLATSCR:       ; %bb.0: ; %entry
56; FLATSCR-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
57; FLATSCR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x8
58; FLATSCR-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
59; FLATSCR-NEXT:    s_mov_b32 s32, 16
60; FLATSCR-NEXT:    s_mov_b32 s33, 0
61; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
62; FLATSCR-NEXT:    s_cmp_lg_u32 s4, 0
63; FLATSCR-NEXT:    s_cbranch_scc1 BB0_3
64; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
65; FLATSCR-NEXT:    s_cmp_lg_u32 s5, 0
66; FLATSCR-NEXT:    s_cbranch_scc1 BB0_3
67; FLATSCR-NEXT:  ; %bb.2: ; %bb.1
68; FLATSCR-NEXT:    s_mov_b32 s2, s32
69; FLATSCR-NEXT:    s_add_i32 s3, s2, 0x1000
70; FLATSCR-NEXT:    v_mov_b32_e32 v1, 0
71; FLATSCR-NEXT:    s_add_u32 s2, s2, 0x1000
72; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
73; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[1:2], s2
74; FLATSCR-NEXT:    s_lshl_b32 s2, s6, 2
75; FLATSCR-NEXT:    s_mov_b32 s32, s3
76; FLATSCR-NEXT:    s_add_i32 s3, s3, s2
77; FLATSCR-NEXT:    scratch_load_dword v2, off, s3
78; FLATSCR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
79; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
80; FLATSCR-NEXT:    v_add_u32_e32 v0, v2, v0
81; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
82; FLATSCR-NEXT:    global_store_dword v1, v0, s[0:1]
83; FLATSCR-NEXT:  BB0_3: ; %bb.2
84; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
85; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
86; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
87; FLATSCR-NEXT:    s_endpgm
88
89entry:
90  %cond0 = icmp eq i32 %arg.cond0, 0
91  br i1 %cond0, label %bb.0, label %bb.2
92
93bb.0:
94  %alloca = alloca [16 x i32], align 4, addrspace(5)
95  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
96  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
97  %cond1 = icmp eq i32 %arg.cond1, 0
98  br i1 %cond1, label %bb.1, label %bb.2
99
100bb.1:
101  ; Use the alloca outside of the defining block.
102  store i32 0, i32 addrspace(5)* %gep0
103  store i32 1, i32 addrspace(5)* %gep1
104  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
105  %load = load i32, i32 addrspace(5)* %gep2
106  %tid = call i32 @llvm.amdgcn.workitem.id.x()
107  %add = add i32 %load, %tid
108  store i32 %add, i32 addrspace(1)* %out
109  br label %bb.2
110
111bb.2:
112  store volatile i32 0, i32 addrspace(1)* undef
113  ret void
114}
115; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4112
116; DEFAULTSIZE: ; ScratchSize: 4112
117
118; ASSUME1024: .amdhsa_private_segment_fixed_size 1040
119; ASSUME1024: ; ScratchSize: 1040
120
121define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(i32 addrspace(1)* %out, i32 %arg.cond, i32 %in) {
122; MUBUF-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
123; MUBUF:       ; %bb.0: ; %entry
124; MUBUF-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
125; MUBUF-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
126; MUBUF-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
127; MUBUF-NEXT:    s_add_u32 s0, s0, s9
128; MUBUF-NEXT:    s_addc_u32 s1, s1, 0
129; MUBUF-NEXT:    s_movk_i32 s32, 0x1000
130; MUBUF-NEXT:    s_mov_b32 s33, 0
131; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
132; MUBUF-NEXT:    s_cmp_lg_u32 s6, 0
133; MUBUF-NEXT:    s_cbranch_scc1 BB1_2
134; MUBUF-NEXT:  ; %bb.1: ; %bb.0
135; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
136; MUBUF-NEXT:    s_and_b32 s6, s6, 0xfffff000
137; MUBUF-NEXT:    s_lshl_b32 s7, s7, 2
138; MUBUF-NEXT:    s_mov_b32 s32, s6
139; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
140; MUBUF-NEXT:    v_mov_b32_e32 v1, 0
141; MUBUF-NEXT:    v_mov_b32_e32 v3, 1
142; MUBUF-NEXT:    s_add_i32 s6, s6, s7
143; MUBUF-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
144; MUBUF-NEXT:    buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
145; MUBUF-NEXT:    v_mov_b32_e32 v2, s6
146; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
147; MUBUF-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
148; MUBUF-NEXT:    s_waitcnt vmcnt(0)
149; MUBUF-NEXT:    v_add_u32_e32 v0, v2, v0
150; MUBUF-NEXT:    s_waitcnt lgkmcnt(0)
151; MUBUF-NEXT:    global_store_dword v1, v0, s[4:5]
152; MUBUF-NEXT:  BB1_2: ; %bb.1
153; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
154; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
155; MUBUF-NEXT:    s_waitcnt vmcnt(0)
156; MUBUF-NEXT:    s_endpgm
157;
158; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
159; FLATSCR:       ; %bb.0: ; %entry
160; FLATSCR-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
161; FLATSCR-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
162; FLATSCR-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x8
163; FLATSCR-NEXT:    s_mov_b32 s32, 64
164; FLATSCR-NEXT:    s_mov_b32 s33, 0
165; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
166; FLATSCR-NEXT:    s_cmp_lg_u32 s2, 0
167; FLATSCR-NEXT:    s_cbranch_scc1 BB1_2
168; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
169; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
170; FLATSCR-NEXT:    s_and_b32 s2, s2, 0xfffff000
171; FLATSCR-NEXT:    v_mov_b32_e32 v1, 0
172; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
173; FLATSCR-NEXT:    s_lshl_b32 s3, s3, 2
174; FLATSCR-NEXT:    s_mov_b32 s32, s2
175; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[1:2], s2
176; FLATSCR-NEXT:    s_add_i32 s2, s2, s3
177; FLATSCR-NEXT:    scratch_load_dword v2, off, s2
178; FLATSCR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
179; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
180; FLATSCR-NEXT:    v_add_u32_e32 v0, v2, v0
181; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
182; FLATSCR-NEXT:    global_store_dword v1, v0, s[0:1]
183; FLATSCR-NEXT:  BB1_2: ; %bb.1
184; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
185; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
186; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
187; FLATSCR-NEXT:    s_endpgm
188entry:
189  %cond = icmp eq i32 %arg.cond, 0
190  br i1 %cond, label %bb.0, label %bb.1
191
192bb.0:
193  %alloca = alloca [16 x i32], align 64, addrspace(5)
194  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
195  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
196  store i32 0, i32 addrspace(5)* %gep0
197  store i32 1, i32 addrspace(5)* %gep1
198  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
199  %load = load i32, i32 addrspace(5)* %gep2
200  %tid = call i32 @llvm.amdgcn.workitem.id.x()
201  %add = add i32 %load, %tid
202  store i32 %add, i32 addrspace(1)* %out
203  br label %bb.1
204
205bb.1:
206  store volatile i32 0, i32 addrspace(1)* undef
207  ret void
208}
209
210; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4160
211; DEFAULTSIZE: ; ScratchSize: 4160
212
213; ASSUME1024: .amdhsa_private_segment_fixed_size 1088
214; ASSUME1024: ; ScratchSize: 1088
215
216
217define void @func_non_entry_block_static_alloca_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) {
218; MUBUF-LABEL: func_non_entry_block_static_alloca_align4:
219; MUBUF:       ; %bb.0: ; %entry
220; MUBUF-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
221; MUBUF-NEXT:    s_mov_b32 s7, s33
222; MUBUF-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
223; MUBUF-NEXT:    s_mov_b32 s33, s32
224; MUBUF-NEXT:    s_add_u32 s32, s32, 0x400
225; MUBUF-NEXT:    s_and_saveexec_b64 s[4:5], vcc
226; MUBUF-NEXT:    s_cbranch_execz BB2_3
227; MUBUF-NEXT:  ; %bb.1: ; %bb.0
228; MUBUF-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
229; MUBUF-NEXT:    s_and_b64 exec, exec, vcc
230; MUBUF-NEXT:    s_cbranch_execz BB2_3
231; MUBUF-NEXT:  ; %bb.2: ; %bb.1
232; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
233; MUBUF-NEXT:    v_mov_b32_e32 v2, 0
234; MUBUF-NEXT:    v_mov_b32_e32 v3, s6
235; MUBUF-NEXT:    buffer_store_dword v2, v3, s[0:3], 0 offen
236; MUBUF-NEXT:    v_mov_b32_e32 v2, 1
237; MUBUF-NEXT:    buffer_store_dword v2, v3, s[0:3], 0 offen offset:4
238; MUBUF-NEXT:    v_lshl_add_u32 v2, v4, 2, s6
239; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
240; MUBUF-NEXT:    v_and_b32_e32 v3, 0x3ff, v5
241; MUBUF-NEXT:    s_mov_b32 s32, s6
242; MUBUF-NEXT:    s_waitcnt vmcnt(0)
243; MUBUF-NEXT:    v_add_u32_e32 v2, v2, v3
244; MUBUF-NEXT:    global_store_dword v[0:1], v2, off
245; MUBUF-NEXT:  BB2_3: ; %bb.2
246; MUBUF-NEXT:    s_or_b64 exec, exec, s[4:5]
247; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
248; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
249; MUBUF-NEXT:    s_waitcnt vmcnt(0)
250; MUBUF-NEXT:    s_sub_u32 s32, s32, 0x400
251; MUBUF-NEXT:    s_mov_b32 s33, s7
252; MUBUF-NEXT:    s_setpc_b64 s[30:31]
253;
254; FLATSCR-LABEL: func_non_entry_block_static_alloca_align4:
255; FLATSCR:       ; %bb.0: ; %entry
256; FLATSCR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
257; FLATSCR-NEXT:    s_mov_b32 s4, s33
258; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
259; FLATSCR-NEXT:    s_mov_b32 s33, s32
260; FLATSCR-NEXT:    s_add_u32 s32, s32, 16
261; FLATSCR-NEXT:    s_and_saveexec_b64 s[0:1], vcc
262; FLATSCR-NEXT:    s_cbranch_execz BB2_3
263; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
264; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
265; FLATSCR-NEXT:    s_and_b64 exec, exec, vcc
266; FLATSCR-NEXT:    s_cbranch_execz BB2_3
267; FLATSCR-NEXT:  ; %bb.2: ; %bb.1
268; FLATSCR-NEXT:    s_mov_b32 s2, s32
269; FLATSCR-NEXT:    s_add_i32 s3, s2, 0x1000
270; FLATSCR-NEXT:    s_add_u32 s2, s2, 0x1000
271; FLATSCR-NEXT:    v_mov_b32_e32 v2, 0
272; FLATSCR-NEXT:    v_mov_b32_e32 v3, 1
273; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[2:3], s2
274; FLATSCR-NEXT:    v_lshl_add_u32 v2, v4, 2, s3
275; FLATSCR-NEXT:    scratch_load_dword v2, v2, off
276; FLATSCR-NEXT:    v_and_b32_e32 v3, 0x3ff, v5
277; FLATSCR-NEXT:    s_mov_b32 s32, s3
278; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
279; FLATSCR-NEXT:    v_add_u32_e32 v2, v2, v3
280; FLATSCR-NEXT:    global_store_dword v[0:1], v2, off
281; FLATSCR-NEXT:  BB2_3: ; %bb.2
282; FLATSCR-NEXT:    s_or_b64 exec, exec, s[0:1]
283; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
284; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
285; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
286; FLATSCR-NEXT:    s_sub_u32 s32, s32, 16
287; FLATSCR-NEXT:    s_mov_b32 s33, s4
288; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
289
290entry:
291  %cond0 = icmp eq i32 %arg.cond0, 0
292  br i1 %cond0, label %bb.0, label %bb.2
293
294bb.0:
295  %alloca = alloca [16 x i32], align 4, addrspace(5)
296  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
297  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
298  %cond1 = icmp eq i32 %arg.cond1, 0
299  br i1 %cond1, label %bb.1, label %bb.2
300
301bb.1:
302  ; Use the alloca outside of the defining block.
303  store i32 0, i32 addrspace(5)* %gep0
304  store i32 1, i32 addrspace(5)* %gep1
305  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
306  %load = load i32, i32 addrspace(5)* %gep2
307  %tid = call i32 @llvm.amdgcn.workitem.id.x()
308  %add = add i32 %load, %tid
309  store i32 %add, i32 addrspace(1)* %out
310  br label %bb.2
311
312bb.2:
313  store volatile i32 0, i32 addrspace(1)* undef
314  ret void
315}
316
317define void @func_non_entry_block_static_alloca_align64(i32 addrspace(1)* %out, i32 %arg.cond, i32 %in) {
318; MUBUF-LABEL: func_non_entry_block_static_alloca_align64:
319; MUBUF:       ; %bb.0: ; %entry
320; MUBUF-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
321; MUBUF-NEXT:    s_mov_b32 s7, s33
322; MUBUF-NEXT:    s_add_u32 s33, s32, 0xfc0
323; MUBUF-NEXT:    s_and_b32 s33, s33, 0xfffff000
324; MUBUF-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
325; MUBUF-NEXT:    s_add_u32 s32, s32, 0x2000
326; MUBUF-NEXT:    s_and_saveexec_b64 s[4:5], vcc
327; MUBUF-NEXT:    s_cbranch_execz BB3_2
328; MUBUF-NEXT:  ; %bb.1: ; %bb.0
329; MUBUF-NEXT:    s_add_i32 s6, s32, 0x1000
330; MUBUF-NEXT:    s_and_b32 s6, s6, 0xfffff000
331; MUBUF-NEXT:    v_mov_b32_e32 v2, 0
332; MUBUF-NEXT:    v_mov_b32_e32 v5, s6
333; MUBUF-NEXT:    buffer_store_dword v2, v5, s[0:3], 0 offen
334; MUBUF-NEXT:    v_mov_b32_e32 v2, 1
335; MUBUF-NEXT:    buffer_store_dword v2, v5, s[0:3], 0 offen offset:4
336; MUBUF-NEXT:    v_lshl_add_u32 v2, v3, 2, s6
337; MUBUF-NEXT:    buffer_load_dword v2, v2, s[0:3], 0 offen
338; MUBUF-NEXT:    v_and_b32_e32 v3, 0x3ff, v4
339; MUBUF-NEXT:    s_mov_b32 s32, s6
340; MUBUF-NEXT:    s_waitcnt vmcnt(0)
341; MUBUF-NEXT:    v_add_u32_e32 v2, v2, v3
342; MUBUF-NEXT:    global_store_dword v[0:1], v2, off
343; MUBUF-NEXT:  BB3_2: ; %bb.1
344; MUBUF-NEXT:    s_or_b64 exec, exec, s[4:5]
345; MUBUF-NEXT:    v_mov_b32_e32 v0, 0
346; MUBUF-NEXT:    global_store_dword v[0:1], v0, off
347; MUBUF-NEXT:    s_waitcnt vmcnt(0)
348; MUBUF-NEXT:    s_sub_u32 s32, s32, 0x2000
349; MUBUF-NEXT:    s_mov_b32 s33, s7
350; MUBUF-NEXT:    s_setpc_b64 s[30:31]
351;
352; FLATSCR-LABEL: func_non_entry_block_static_alloca_align64:
353; FLATSCR:       ; %bb.0: ; %entry
354; FLATSCR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
355; FLATSCR-NEXT:    s_mov_b32 s3, s33
356; FLATSCR-NEXT:    s_add_u32 s33, s32, 63
357; FLATSCR-NEXT:    s_andn2_b32 s33, s33, 63
358; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
359; FLATSCR-NEXT:    s_add_u32 s32, s32, 0x80
360; FLATSCR-NEXT:    s_and_saveexec_b64 s[0:1], vcc
361; FLATSCR-NEXT:    s_cbranch_execz BB3_2
362; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
363; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
364; FLATSCR-NEXT:    s_and_b32 s2, s2, 0xfffff000
365; FLATSCR-NEXT:    v_mov_b32_e32 v5, 0
366; FLATSCR-NEXT:    v_mov_b32_e32 v6, 1
367; FLATSCR-NEXT:    v_lshl_add_u32 v2, v3, 2, s2
368; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[5:6], s2
369; FLATSCR-NEXT:    scratch_load_dword v2, v2, off
370; FLATSCR-NEXT:    v_and_b32_e32 v3, 0x3ff, v4
371; FLATSCR-NEXT:    s_mov_b32 s32, s2
372; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
373; FLATSCR-NEXT:    v_add_u32_e32 v2, v2, v3
374; FLATSCR-NEXT:    global_store_dword v[0:1], v2, off
375; FLATSCR-NEXT:  BB3_2: ; %bb.1
376; FLATSCR-NEXT:    s_or_b64 exec, exec, s[0:1]
377; FLATSCR-NEXT:    v_mov_b32_e32 v0, 0
378; FLATSCR-NEXT:    global_store_dword v[0:1], v0, off
379; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
380; FLATSCR-NEXT:    s_sub_u32 s32, s32, 0x80
381; FLATSCR-NEXT:    s_mov_b32 s33, s3
382; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
383entry:
384  %cond = icmp eq i32 %arg.cond, 0
385  br i1 %cond, label %bb.0, label %bb.1
386
387bb.0:
388  %alloca = alloca [16 x i32], align 64, addrspace(5)
389  %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
390  %gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
391  store i32 0, i32 addrspace(5)* %gep0
392  store i32 1, i32 addrspace(5)* %gep1
393  %gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
394  %load = load i32, i32 addrspace(5)* %gep2
395  %tid = call i32 @llvm.amdgcn.workitem.id.x()
396  %add = add i32 %load, %tid
397  store i32 %add, i32 addrspace(1)* %out
398  br label %bb.1
399
400bb.1:
401  store volatile i32 0, i32 addrspace(1)* undef
402  ret void
403}
404
405declare i32 @llvm.amdgcn.workitem.id.x() #0
406
407attributes #0 = { nounwind readnone speculatable }
408