1; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s
2; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4; After structurizing, there are 3 levels of loops. The i1 phi
5; conditions mutually depend on each other, so it isn't safe to delete
6; the condition that appears to have no uses until the loop is
7; completely processed.
8
9
10; IR-LABEL: @reduced_nested_loop_conditions(
11
12; IR: bb5:
13; IR-NEXT: %phi.broken = phi i64 [ %3, %bb10 ], [ 0, %bb ]
14; IR-NEXT: %tmp6 = phi i32 [ 0, %bb ], [ %tmp11, %bb10 ]
15; IR-NEXT: %tmp7 = icmp eq i32 %tmp6, 1
16; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %tmp7)
17; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0
18; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1
19; IR-NEXT: br i1 %1, label %bb8, label %Flow
20
21; IR: bb8:
22; IR-NEXT: br label %bb13
23
24; IR: bb10:
25; IR-NEXT: %tmp11 = phi i32 [ %6, %Flow ]
26; IR-NEXT: %tmp12 = phi i1 [ %5, %Flow ]
27; IR-NEXT: %3 = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %tmp12, i64 %phi.broken)
28; IR-NEXT: %4 = call i1 @llvm.amdgcn.loop.i64(i64 %3)
29; IR-NEXT: br i1 %4, label %bb23, label %bb5
30
31; IR: Flow:
32; IR-NEXT: %5 = phi i1 [ %tmp22, %bb4 ], [ true, %bb5 ]
33; IR-NEXT: %6 = phi i32 [ %tmp21, %bb4 ], [ undef, %bb5 ]
34; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %2)
35; IR-NEXT: br label %bb10
36
37; IR: bb13:
38; IR-NEXT: %tmp14 = phi i1 [ %tmp22, %bb3 ], [ true, %bb8 ]
39; IR-NEXT: %tmp15 = bitcast i64 %tmp2 to <2 x i32>
40; IR-NEXT: br i1 %tmp14, label %bb16, label %bb20
41
42; IR: bb16:
43; IR-NEXT: %tmp17 = extractelement <2 x i32> %tmp15, i64 1
44; IR-NEXT: %tmp18 = getelementptr inbounds i32, i32 addrspace(3)* undef, i32 %tmp17
45; IR-NEXT: %tmp19 = load volatile i32, i32 addrspace(3)* %tmp18
46; IR-NEXT: br label %bb20
47
48; IR: bb20:
49; IR-NEXT: %tmp21 = phi i32 [ %tmp19, %bb16 ], [ 0, %bb13 ]
50; IR-NEXT: %tmp22 = phi i1 [ false, %bb16 ], [ %tmp14, %bb13 ]
51; IR-NEXT: br label %bb9
52
53; IR: bb23:
54; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %3)
55; IR-NEXT: ret void
56
57; GCN-LABEL: {{^}}reduced_nested_loop_conditions:
58
59; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
60; GCN-NEXT: s_cbranch_scc0
61
62; FIXME: Should fold to unconditional branch?
63; GCN: ; implicit-def
64; GCN: s_cbranch_vccnz
65
66; GCN: ds_read_b32
67
68; GCN: [[BB9:BB[0-9]+_[0-9]+]]: ; %bb9
69; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
70; GCN-NEXT: s_cbranch_vccnz [[BB9]]
71define amdgpu_kernel void @reduced_nested_loop_conditions(i64 addrspace(3)* nocapture %arg) #0 {
72bb:
73  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #1
74  %tmp1 = getelementptr inbounds i64, i64 addrspace(3)* %arg, i32 %tmp
75  %tmp2 = load volatile i64, i64 addrspace(3)* %tmp1
76  br label %bb5
77
78bb3:                                              ; preds = %bb9
79  br i1 true, label %bb4, label %bb13
80
81bb4:                                              ; preds = %bb3
82  br label %bb10
83
84bb5:                                              ; preds = %bb10, %bb
85  %tmp6 = phi i32 [ 0, %bb ], [ %tmp11, %bb10 ]
86  %tmp7 = icmp eq i32 %tmp6, 1
87  br i1 %tmp7, label %bb8, label %bb10
88
89bb8:                                              ; preds = %bb5
90  br label %bb13
91
92bb9:                                              ; preds = %bb20, %bb9
93  br i1 false, label %bb3, label %bb9
94
95bb10:                                             ; preds = %bb5, %bb4
96  %tmp11 = phi i32 [ %tmp21, %bb4 ], [ undef, %bb5 ]
97  %tmp12 = phi i1 [ %tmp22, %bb4 ], [ true, %bb5 ]
98  br i1 %tmp12, label %bb23, label %bb5
99
100bb13:                                             ; preds = %bb8, %bb3
101  %tmp14 = phi i1 [ %tmp22, %bb3 ], [ true, %bb8 ]
102  %tmp15 = bitcast i64 %tmp2 to <2 x i32>
103  br i1 %tmp14, label %bb16, label %bb20
104
105bb16:                                             ; preds = %bb13
106  %tmp17 = extractelement <2 x i32> %tmp15, i64 1
107  %tmp18 = getelementptr inbounds i32, i32 addrspace(3)* undef, i32 %tmp17
108  %tmp19 = load volatile i32, i32 addrspace(3)* %tmp18
109  br label %bb20
110
111bb20:                                             ; preds = %bb16, %bb13
112  %tmp21 = phi i32 [ %tmp19, %bb16 ], [ 0, %bb13 ]
113  %tmp22 = phi i1 [ false, %bb16 ], [ %tmp14, %bb13 ]
114  br label %bb9
115
116bb23:                                             ; preds = %bb10
117  ret void
118}
119
120; Earlier version of above, before a run of the structurizer.
121; IR-LABEL: @nested_loop_conditions(
122
123; IR: Flow3:
124; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %21)
125; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %14)
126; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0
127; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1
128; IR-NEXT: br i1 %1, label %bb4.bb13_crit_edge, label %Flow4
129
130; IR: Flow4:
131; IR-NEXT: %3 = phi i1 [ true, %bb4.bb13_crit_edge ], [ false, %Flow3 ]
132; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %2)
133; IR-NEXT: br label %Flow
134
135; IR: Flow:
136; IR-NEXT:  %4 = phi i1 [ %3, %Flow4 ], [ true, %bb ]
137; IR-NEXT:  %5 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %4)
138; IR-NEXT:  %6 = extractvalue { i1, i64 } %5, 0
139; IR-NEXT:  %7 = extractvalue { i1, i64 } %5, 1
140; IR-NEXT:  br i1 %6, label %bb13, label %bb31
141
142; IR: bb14:
143; IR: %tmp15 = icmp eq i32 %tmp1037, 1
144; IR-NEXT: %8 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %tmp15)
145
146; IR: Flow1:
147; IR-NEXT: %11 = phi <4 x i32> [ %tmp9, %bb21 ], [ undef, %bb14 ]
148; IR-NEXT: %12 = phi i32 [ %tmp10, %bb21 ], [ undef, %bb14 ]
149; IR-NEXT: %13 = phi i1 [ %18, %bb21 ], [ true, %bb14 ]
150; IR-NEXT: %14 = phi i1 [ %18, %bb21 ], [ false, %bb14 ]
151; IR-NEXT: %15 = phi i1 [ false, %bb21 ], [ true, %bb14 ]
152; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %10)
153; IR-NEXT: %16 = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %13, i64 %phi.broken)
154; IR-NEXT: %17 = call i1 @llvm.amdgcn.loop.i64(i64 %16)
155; IR-NEXT: br i1 %17, label %Flow2, label %bb14
156
157; IR: bb21:
158; IR: %tmp12 = icmp slt i32 %tmp11, 9
159; IR-NEXT: %18 = xor i1 %tmp12, true
160; IR-NEXT: br label %Flow1
161
162; IR: Flow2:
163; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %16)
164; IR-NEXT: %19 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %15)
165; IR-NEXT: %20 = extractvalue { i1, i64 } %19, 0
166; IR-NEXT: %21 = extractvalue { i1, i64 } %19, 1
167; IR-NEXT: br i1 %20, label %bb31.loopexit, label %Flow3
168
169; IR: bb31:
170; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %7)
171; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef
172; IR-NEXT: ret void
173
174
175; GCN-LABEL: {{^}}nested_loop_conditions:
176
177; GCN: v_cmp_lt_i32_e32 vcc, 8, v
178; GCN: s_and_b64 vcc, exec, vcc
179; GCN: s_cbranch_vccnz [[BB31:BB[0-9]+_[0-9]+]]
180
181; GCN: [[BB14:BB[0-9]+_[0-9]+]]: ; %bb14
182; GCN: v_cmp_ne_u32_e32 vcc, 1, v
183; GCN-NEXT: s_and_b64 vcc, exec, vcc
184; GCN-NEXT: s_cbranch_vccnz [[BB31]]
185
186; GCN: [[BB18:BB[0-9]+_[0-9]+]]: ; %bb18
187; GCN: buffer_load_dword
188; GCN: v_cmp_lt_i32_e32 vcc, 8, v
189; GCN-NEXT: s_and_b64 vcc, exec, vcc
190; GCN-NEXT: s_cbranch_vccnz [[BB18]]
191
192; GCN: buffer_load_dword
193; GCN: buffer_load_dword
194; GCN: v_cmp_gt_i32_e32 vcc, 9
195; GCN-NEXT: s_and_b64 vcc, exec, vcc
196; GCN-NEXT: s_cbranch_vccnz [[BB14]]
197
198; GCN: [[BB31]]:
199; GCN: buffer_store_dword
200; GCN: s_endpgm
201define amdgpu_kernel void @nested_loop_conditions(i64 addrspace(1)* nocapture %arg) #0 {
202bb:
203  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #1
204  %tmp1 = zext i32 %tmp to i64
205  %tmp2 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp1
206  %tmp3 = load i64, i64 addrspace(1)* %tmp2, align 16
207  %tmp932 = load <4 x i32>, <4 x i32> addrspace(1)* undef, align 16
208  %tmp1033 = extractelement <4 x i32> %tmp932, i64 0
209  %tmp1134 = load volatile i32, i32 addrspace(1)* undef
210  %tmp1235 = icmp slt i32 %tmp1134, 9
211  br i1 %tmp1235, label %bb14.lr.ph, label %bb13
212
213bb14.lr.ph:                                       ; preds = %bb
214  br label %bb14
215
216bb4.bb13_crit_edge:                               ; preds = %bb21
217  br label %bb13
218
219bb13:                                             ; preds = %bb4.bb13_crit_edge, %bb
220  br label %bb31
221
222bb14:                                             ; preds = %bb21, %bb14.lr.ph
223  %tmp1037 = phi i32 [ %tmp1033, %bb14.lr.ph ], [ %tmp10, %bb21 ]
224  %tmp936 = phi <4 x i32> [ %tmp932, %bb14.lr.ph ], [ %tmp9, %bb21 ]
225  %tmp15 = icmp eq i32 %tmp1037, 1
226  br i1 %tmp15, label %bb16, label %bb31.loopexit
227
228bb16:                                             ; preds = %bb14
229  %tmp17 = bitcast i64 %tmp3 to <2 x i32>
230  br label %bb18
231
232bb18:                                             ; preds = %bb18, %bb16
233  %tmp19 = load volatile i32, i32 addrspace(1)* undef
234  %tmp20 = icmp slt i32 %tmp19, 9
235  br i1 %tmp20, label %bb21, label %bb18
236
237bb21:                                             ; preds = %bb18
238  %tmp22 = extractelement <2 x i32> %tmp17, i64 1
239  %tmp23 = lshr i32 %tmp22, 16
240  %tmp24 = select i1 undef, i32 undef, i32 %tmp23
241  %tmp25 = uitofp i32 %tmp24 to float
242  %tmp26 = fmul float %tmp25, 0x3EF0001000000000
243  %tmp27 = fsub float %tmp26, undef
244  %tmp28 = fcmp olt float %tmp27, 5.000000e-01
245  %tmp29 = select i1 %tmp28, i64 1, i64 2
246  %tmp30 = extractelement <4 x i32> %tmp936, i64 %tmp29
247  %tmp7 = zext i32 %tmp30 to i64
248  %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %tmp7
249  %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
250  %tmp10 = extractelement <4 x i32> %tmp9, i64 0
251  %tmp11 = load volatile i32, i32 addrspace(1)* undef
252  %tmp12 = icmp slt i32 %tmp11, 9
253  br i1 %tmp12, label %bb14, label %bb4.bb13_crit_edge
254
255bb31.loopexit:                                    ; preds = %bb14
256  br label %bb31
257
258bb31:                                             ; preds = %bb31.loopexit, %bb13
259  store volatile i32 0, i32 addrspace(1)* undef
260  ret void
261}
262
263declare i32 @llvm.amdgcn.workitem.id.x() #1
264
265attributes #0 = { nounwind }
266attributes #1 = { nounwind readnone }
267