1; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s
2; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4; After structurizing, there are 3 levels of loops. The i1 phi
5; conditions mutually depend on each other, so it isn't safe to delete
6; the condition that appears to have no uses until the loop is
7; completely processed.
8
9
10; IR-LABEL: @reduced_nested_loop_conditions(
11
12; IR: bb5:
13; IR-NEXT: %phi.broken = phi i64 [ %loop.phi, %bb10 ], [ 0, %bb ]
14; IR-NEXT: %tmp6 = phi i32 [ 0, %bb ], [ %tmp11, %bb10 ]
15; IR-NEXT: %tmp7 = icmp eq i32 %tmp6, 1
16; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %tmp7)
17; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0
18; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1
19; IR-NEXT: br i1 %1, label %bb8, label %Flow
20
21; IR: bb8:
22; IR-NEXT: %3 = call i64 @llvm.amdgcn.break(i64 %phi.broken)
23; IR-NEXT: br label %bb13
24
25; IR: bb10:
26; IR-NEXT: %loop.phi = phi i64 [ %6, %Flow ]
27; IR-NEXT: %tmp11 = phi i32 [ %5, %Flow ]
28; IR-NEXT: %4 = call i1 @llvm.amdgcn.loop(i64 %loop.phi)
29; IR-NEXT: br i1 %4, label %bb23, label %bb5
30
31; IR: Flow:
32; IR-NEXT: %loop.phi1 = phi i64 [ %loop.phi2, %bb4 ], [ %phi.broken, %bb5 ]
33; IR-NEXT: %5 = phi i32 [ %tmp21, %bb4 ], [ undef, %bb5 ]
34; IR-NEXT: %6 = call i64 @llvm.amdgcn.else.break(i64 %2, i64 %loop.phi1)
35; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %2)
36; IR-NEXT: br label %bb10
37
38; IR: bb13:
39; IR-NEXT: %loop.phi3 = phi i64 [ %loop.phi4, %bb3 ], [ %3, %bb8 ]
40; IR-NEXT: %tmp14 = phi i1 [ false, %bb3 ], [ true, %bb8 ]
41; IR-NEXT: %tmp15 = bitcast i64 %tmp2 to <2 x i32>
42; IR-NEXT: br i1 %tmp14, label %bb16, label %bb20
43
44; IR: bb16:
45; IR-NEXT: %tmp17 = extractelement <2 x i32> %tmp15, i64 1
46; IR-NEXT: %tmp18 = getelementptr inbounds i32, i32 addrspace(3)* undef, i32 %tmp17
47; IR-NEXT: %tmp19 = load volatile i32, i32 addrspace(3)* %tmp18
48; IR-NEXT: br label %bb20
49
50; IR: bb20:
51; IR-NEXT: %loop.phi4 = phi i64 [ %phi.broken, %bb16 ], [ %phi.broken, %bb13 ]
52; IR-NEXT: %loop.phi2 = phi i64 [ %phi.broken, %bb16 ], [ %loop.phi3, %bb13 ]
53; IR-NEXT: %tmp21 = phi i32 [ %tmp19, %bb16 ], [ 0, %bb13 ]
54; IR-NEXT: br label %bb9
55
56; IR: bb23:
57; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %loop.phi)
58; IR-NEXT: ret void
59
60; GCN-LABEL: {{^}}reduced_nested_loop_conditions:
61
62; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 1
63; GCN-NEXT: s_cbranch_scc1
64
65; FIXME: Should fold to unconditional branch?
66; GCN: s_mov_b64 vcc, -1
67; GCN-NEXT: ; implicit-def
68; GCN: s_cbranch_vccz
69
70; GCN: ds_read_b32
71
72; GCN: [[BB9:BB[0-9]+_[0-9]+]]: ; %bb9
73; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
74; GCN-NEXT: s_branch [[BB9]]
75define amdgpu_kernel void @reduced_nested_loop_conditions(i64 addrspace(3)* nocapture %arg) #0 {
76bb:
77  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #1
78  %tmp1 = getelementptr inbounds i64, i64 addrspace(3)* %arg, i32 %tmp
79  %tmp2 = load volatile i64, i64 addrspace(3)* %tmp1
80  br label %bb5
81
82bb3:                                              ; preds = %bb9
83  br i1 true, label %bb4, label %bb13
84
85bb4:                                              ; preds = %bb3
86  br label %bb10
87
88bb5:                                              ; preds = %bb10, %bb
89  %tmp6 = phi i32 [ 0, %bb ], [ %tmp11, %bb10 ]
90  %tmp7 = icmp eq i32 %tmp6, 1
91  br i1 %tmp7, label %bb8, label %bb10
92
93bb8:                                              ; preds = %bb5
94  br label %bb13
95
96bb9:                                              ; preds = %bb20, %bb9
97  br i1 false, label %bb3, label %bb9
98
99bb10:                                             ; preds = %bb5, %bb4
100  %tmp11 = phi i32 [ %tmp21, %bb4 ], [ undef, %bb5 ]
101  %tmp12 = phi i1 [ %tmp22, %bb4 ], [ true, %bb5 ]
102  br i1 %tmp12, label %bb23, label %bb5
103
104bb13:                                             ; preds = %bb8, %bb3
105  %tmp14 = phi i1 [ %tmp22, %bb3 ], [ true, %bb8 ]
106  %tmp15 = bitcast i64 %tmp2 to <2 x i32>
107  br i1 %tmp14, label %bb16, label %bb20
108
109bb16:                                             ; preds = %bb13
110  %tmp17 = extractelement <2 x i32> %tmp15, i64 1
111  %tmp18 = getelementptr inbounds i32, i32 addrspace(3)* undef, i32 %tmp17
112  %tmp19 = load volatile i32, i32 addrspace(3)* %tmp18
113  br label %bb20
114
115bb20:                                             ; preds = %bb16, %bb13
116  %tmp21 = phi i32 [ %tmp19, %bb16 ], [ 0, %bb13 ]
117  %tmp22 = phi i1 [ false, %bb16 ], [ %tmp14, %bb13 ]
118  br label %bb9
119
120bb23:                                             ; preds = %bb10
121  ret void
122}
123
124; Earlier version of above, before a run of the structurizer.
125; IR-LABEL: @nested_loop_conditions(
126
127; IR: Flow7:
128; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %17)
129; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %15)
130; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0
131; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1
132; IR-NEXT: br i1 %1, label %bb4.bb13_crit_edge, label %Flow8
133
134; IR: Flow1:
135; IR-NEXT: %loop.phi = phi i64 [ %loop.phi9, %Flow6 ], [ %phi.broken, %bb14 ]
136; IR-NEXT: %13 = phi <4 x i32> [ %29, %Flow6 ], [ undef, %bb14 ]
137; IR-NEXT: %14 = phi i32 [ %30, %Flow6 ], [ undef, %bb14 ]
138; IR-NEXT: %15 = phi i1 [ %31, %Flow6 ], [ false, %bb14 ]
139; IR-NEXT: %16 = phi i1 [ false, %Flow6 ], [ %8, %bb14 ]
140; IR-NEXT: %17 = call i64 @llvm.amdgcn.else.break(i64 %11, i64 %loop.phi)
141; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %11)
142; IR-NEXT: %18 = call i1 @llvm.amdgcn.loop(i64 %17)
143; IR-NEXT: br i1 %18, label %Flow7, label %bb14
144
145; IR: Flow2:
146; IR-NEXT: %loop.phi10 = phi i64 [ %loop.phi11, %Flow5 ], [ %12, %bb16 ]
147; IR-NEXT: %19 = phi <4 x i32> [ %29, %Flow5 ], [ undef, %bb16 ]
148; IR-NEXT: %20 = phi i32 [ %30, %Flow5 ], [ undef, %bb16 ]
149; IR-NEXT: %21 = phi i1 [ %31, %Flow5 ], [ false, %bb16 ]
150; IR-NEXT: %22 = phi i1 [ false, %Flow5 ], [ false, %bb16 ]
151; IR-NEXT: %23 = phi i1 [ false, %Flow5 ], [ %8, %bb16 ]
152; IR-NEXT: %24 = call { i1, i64 } @llvm.amdgcn.if(i1 %23)
153; IR-NEXT: %25 = extractvalue { i1, i64 } %24, 0
154; IR-NEXT: %26 = extractvalue { i1, i64 } %24, 1
155; IR-NEXT: br i1 %25, label %bb21, label %Flow3
156
157; IR: bb21:
158; IR: %tmp12 = icmp slt i32 %tmp11, 9
159; IR-NEXT: %27 = xor i1 %tmp12, true
160; IR-NEXT: %28 = call i64 @llvm.amdgcn.if.break(i1 %27, i64 %phi.broken)
161; IR-NEXT: br label %Flow3
162
163; IR: Flow3:
164; IR-NEXT: %loop.phi11 = phi i64 [ %phi.broken, %bb21 ], [ %phi.broken, %Flow2 ]
165; IR-NEXT: %loop.phi9 = phi i64 [ %28, %bb21 ], [ %loop.phi10, %Flow2 ]
166; IR-NEXT: %29 = phi <4 x i32> [ %tmp9, %bb21 ], [ %19, %Flow2 ]
167; IR-NEXT: %30 = phi i32 [ %tmp10, %bb21 ], [ %20, %Flow2 ]
168; IR-NEXT: %31 = phi i1 [ %27, %bb21 ], [ %21, %Flow2 ]
169; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %26)
170; IR-NEXT: br i1 %22, label %bb31.loopexit, label %Flow4
171
172; IR: bb31:
173; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %7)
174; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef
175; IR-NEXT: ret void
176
177
178; GCN-LABEL: {{^}}nested_loop_conditions:
179
180; GCN: v_cmp_lt_i32_e32 vcc, 8, v
181; GCN: s_and_b64 vcc, exec, vcc
182; GCN: s_cbranch_vccnz [[BB31:BB[0-9]+_[0-9]+]]
183
184; GCN: [[BB14:BB[0-9]+_[0-9]+]]: ; %bb14
185; GCN: v_cmp_ne_u32_e32 vcc, 1, v
186; GCN-NEXT: s_and_b64 vcc, exec, vcc
187; GCN-NEXT: s_cbranch_vccnz [[BB31]]
188
189; GCN: [[BB18:BB[0-9]+_[0-9]+]]: ; %bb18
190; GCN: buffer_load_dword
191; GCN: v_cmp_lt_i32_e32 vcc, 8, v
192; GCN-NEXT: s_and_b64 vcc, exec, vcc
193; GCN-NEXT: s_cbranch_vccnz [[BB18]]
194
195; GCN: buffer_load_dword
196; GCN: buffer_load_dword
197; GCN: v_cmp_gt_i32_e32 vcc, 9
198; GCN-NEXT: s_and_b64 vcc, exec, vcc
199; GCN-NEXT: s_cbranch_vccnz [[BB14]]
200
201; GCN: [[BB31]]:
202; GCN: buffer_store_dword
203; GCN: s_endpgm
204define amdgpu_kernel void @nested_loop_conditions(i64 addrspace(1)* nocapture %arg) #0 {
205bb:
206  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #1
207  %tmp1 = zext i32 %tmp to i64
208  %tmp2 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp1
209  %tmp3 = load i64, i64 addrspace(1)* %tmp2, align 16
210  %tmp932 = load <4 x i32>, <4 x i32> addrspace(1)* undef, align 16
211  %tmp1033 = extractelement <4 x i32> %tmp932, i64 0
212  %tmp1134 = load volatile i32, i32 addrspace(1)* undef
213  %tmp1235 = icmp slt i32 %tmp1134, 9
214  br i1 %tmp1235, label %bb14.lr.ph, label %bb13
215
216bb14.lr.ph:                                       ; preds = %bb
217  br label %bb14
218
219bb4.bb13_crit_edge:                               ; preds = %bb21
220  br label %bb13
221
222bb13:                                             ; preds = %bb4.bb13_crit_edge, %bb
223  br label %bb31
224
225bb14:                                             ; preds = %bb21, %bb14.lr.ph
226  %tmp1037 = phi i32 [ %tmp1033, %bb14.lr.ph ], [ %tmp10, %bb21 ]
227  %tmp936 = phi <4 x i32> [ %tmp932, %bb14.lr.ph ], [ %tmp9, %bb21 ]
228  %tmp15 = icmp eq i32 %tmp1037, 1
229  br i1 %tmp15, label %bb16, label %bb31.loopexit
230
231bb16:                                             ; preds = %bb14
232  %tmp17 = bitcast i64 %tmp3 to <2 x i32>
233  br label %bb18
234
235bb18:                                             ; preds = %bb18, %bb16
236  %tmp19 = load volatile i32, i32 addrspace(1)* undef
237  %tmp20 = icmp slt i32 %tmp19, 9
238  br i1 %tmp20, label %bb21, label %bb18
239
240bb21:                                             ; preds = %bb18
241  %tmp22 = extractelement <2 x i32> %tmp17, i64 1
242  %tmp23 = lshr i32 %tmp22, 16
243  %tmp24 = select i1 undef, i32 undef, i32 %tmp23
244  %tmp25 = uitofp i32 %tmp24 to float
245  %tmp26 = fmul float %tmp25, 0x3EF0001000000000
246  %tmp27 = fsub float %tmp26, undef
247  %tmp28 = fcmp olt float %tmp27, 5.000000e-01
248  %tmp29 = select i1 %tmp28, i64 1, i64 2
249  %tmp30 = extractelement <4 x i32> %tmp936, i64 %tmp29
250  %tmp7 = zext i32 %tmp30 to i64
251  %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %tmp7
252  %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
253  %tmp10 = extractelement <4 x i32> %tmp9, i64 0
254  %tmp11 = load volatile i32, i32 addrspace(1)* undef
255  %tmp12 = icmp slt i32 %tmp11, 9
256  br i1 %tmp12, label %bb14, label %bb4.bb13_crit_edge
257
258bb31.loopexit:                                    ; preds = %bb14
259  br label %bb31
260
261bb31:                                             ; preds = %bb31.loopexit, %bb13
262  store volatile i32 0, i32 addrspace(1)* undef
263  ret void
264}
265
266declare i32 @llvm.amdgcn.workitem.id.x() #1
267
268attributes #0 = { nounwind }
269attributes #1 = { nounwind readnone }
270