1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
5
6; FUNC-LABEL: {{^}}test_smul24_i32:
7; GCN-NOT: bfe
8; GCN: v_mul_i32_i24
9
10; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
11; EG: MULLO_INT
12
13; Make sure we are not masking the inputs
14; CM-NOT: AND
15; CM: MUL_INT24
16define void @test_smul24_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
17entry:
18  %a.shl = shl i32 %a, 8
19  %a.24 = ashr i32 %a.shl, 8
20  %b.shl = shl i32 %b, 8
21  %b.24 = ashr i32 %b.shl, 8
22  %mul24 = mul i32 %a.24, %b.24
23  store i32 %mul24, i32 addrspace(1)* %out
24  ret void
25}
26
27; FUNC-LABEL: {{^}}test_smulhi24_i64:
28; GCN-NOT: bfe
29; GCN-NOT: ashr
30; GCN: v_mul_hi_i32_i24_e32 [[RESULT:v[0-9]+]],
31; GCN-NEXT: buffer_store_dword [[RESULT]]
32
33; EG: ASHR
34; EG: ASHR
35; EG: MULHI_INT
36
37; CM-NOT: ASHR
38; CM: MULHI_INT24
39; CM: MULHI_INT24
40; CM: MULHI_INT24
41; CM: MULHI_INT24
42define void @test_smulhi24_i64(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
43entry:
44  %a.shl = shl i32 %a, 8
45  %a.24 = ashr i32 %a.shl, 8
46  %b.shl = shl i32 %b, 8
47  %b.24 = ashr i32 %b.shl, 8
48  %a.24.i64 = sext i32 %a.24 to i64
49  %b.24.i64 = sext i32 %b.24 to i64
50  %mul48 = mul i64 %a.24.i64, %b.24.i64
51  %mul48.hi = lshr i64 %mul48, 32
52  %mul24hi = trunc i64 %mul48.hi to i32
53  store i32 %mul24hi, i32 addrspace(1)* %out
54  ret void
55}
56
57; This requires handling of the original 64-bit mul node to eliminate
58; unnecessary extension instructions because after legalization they
59; will not be removed by SimplifyDemandedBits because there are
60; multiple uses by the separate mul and mulhi.
61
62; FUNC-LABEL: {{^}}test_smul24_i64:
63; GCN: s_load_dword s
64; GCN: s_load_dword s
65
66; GCN-NOT: bfe
67; GCN-NOT: ashr
68
69; GCN-DAG: v_mul_hi_i32_i24_e32
70; GCN-DAG: v_mul_i32_i24_e32
71
72; GCN: buffer_store_dwordx2
73define void @test_smul24_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
74  %shl.i = shl i32 %a, 8
75  %shr.i = ashr i32 %shl.i, 8
76  %conv.i = sext i32 %shr.i to i64
77  %shl1.i = shl i32 %b, 8
78  %shr2.i = ashr i32 %shl1.i, 8
79  %conv3.i = sext i32 %shr2.i to i64
80  %mul.i = mul i64 %conv3.i, %conv.i
81  store i64 %mul.i, i64 addrspace(1)* %out
82  ret void
83}
84
85; FUNC-LABEL: {{^}}test_smul24_i64_square:
86; GCN: s_load_dword [[A:s[0-9]+]]
87; GCN-DAG: v_mul_hi_i32_i24_e64 v{{[0-9]+}}, [[A]], [[A]]
88; GCN-DAG: v_mul_i32_i24_e64 v{{[0-9]+}}, [[A]], [[A]]
89; GCN: buffer_store_dwordx2
90define void @test_smul24_i64_square(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
91  %shl.i = shl i32 %a, 8
92  %shr.i = ashr i32 %shl.i, 8
93  %conv.i = sext i32 %shr.i to i64
94  %mul.i = mul i64 %conv.i, %conv.i
95  store i64 %mul.i, i64 addrspace(1)* %out
96  ret void
97}
98
99; FUNC-LABEL: {{^}}test_smul24_i33:
100; GCN: s_load_dword s
101; GCN: s_load_dword s
102
103; GCN-NOT: and
104; GCN-NOT: lshr
105
106; GCN-DAG: v_mul_i32_i24_e32
107; GCN-DAG: v_mul_hi_i32_i24_e32
108; SI: v_lshl_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, 31
109; SI: v_ashr_i64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, 31
110
111; VI: v_lshlrev_b64 v{{\[[0-9]+:[0-9]+\]}}, 31, v{{\[[0-9]+:[0-9]+\]}}
112; VI: v_ashrrev_i64 v{{\[[0-9]+:[0-9]+\]}}, 31, v{{\[[0-9]+:[0-9]+\]}}
113
114; GCN: buffer_store_dwordx2
115define void @test_smul24_i33(i64 addrspace(1)* %out, i33 %a, i33 %b) #0 {
116entry:
117  %a.shl = shl i33 %a, 9
118  %a.24 = ashr i33 %a.shl, 9
119  %b.shl = shl i33 %b, 9
120  %b.24 = ashr i33 %b.shl, 9
121  %mul24 = mul i33 %a.24, %b.24
122  %ext = sext i33 %mul24 to i64
123  store i64 %ext, i64 addrspace(1)* %out
124  ret void
125}
126
127; FUNC-LABEL: {{^}}test_smulhi24_i33:
128; SI: s_load_dword s
129; SI: s_load_dword s
130
131; SI-NOT: bfe
132
133; SI: v_mul_hi_i32_i24_e32 v[[MUL_HI:[0-9]+]],
134; SI-NEXT: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
135; SI-NEXT: buffer_store_dword v[[HI]]
136define void @test_smulhi24_i33(i32 addrspace(1)* %out, i33 %a, i33 %b) {
137entry:
138  %tmp0 = shl i33 %a, 9
139  %a_24 = ashr i33 %tmp0, 9
140  %tmp1 = shl i33 %b, 9
141  %b_24 = ashr i33 %tmp1, 9
142  %tmp2 = mul i33 %a_24, %b_24
143  %hi = lshr i33 %tmp2, 32
144  %trunc = trunc i33 %hi to i32
145
146  store i32 %trunc, i32 addrspace(1)* %out
147  ret void
148}
149
150; GCN-LABEL: {{^}}simplify_i24_crash:
151; GCN: v_mul_i32_i24_e32 v[[VAL_LO:[0-9]+]]
152; GCN: v_mov_b32_e32 v[[VAL_HI:[0-9]+]], v[[VAL_LO]]
153; GCN: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
154define void @simplify_i24_crash(<2 x i32> addrspace(1)* %out, i32 %arg0, <2 x i32> %arg1, <2 x i32> %arg2) {
155bb:
156  %cmp = icmp eq i32 %arg0, 0
157  br i1 %cmp, label %bb11, label %bb7
158
159bb11:
160  %tmp14 = shufflevector <2 x i32> %arg1, <2 x i32> undef, <2 x i32> zeroinitializer
161  %tmp16 = shufflevector <2 x i32> %arg2, <2 x i32> undef, <2 x i32> zeroinitializer
162  %tmp17 = shl <2 x i32> %tmp14, <i32 8, i32 8>
163  %tmp18 = ashr <2 x i32> %tmp17, <i32 8, i32 8>
164  %tmp19 = shl <2 x i32> %tmp16, <i32 8, i32 8>
165  %tmp20 = ashr <2 x i32> %tmp19, <i32 8, i32 8>
166  %tmp21 = mul <2 x i32> %tmp18, %tmp20
167  store <2 x i32> %tmp21, <2 x i32> addrspace(1)* %out
168  br label %bb7
169
170bb7:
171  ret void
172
173}
174attributes #0 = { nounwind }
175