1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx1030 -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SCRATCH %s
4
5define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
6; GCN-LABEL: vector_clause:
7; GCN:       ; %bb.0: ; %bb
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
9; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
10; GCN-NEXT:    v_lshlrev_b32_e32 v16, 4, v0
11; GCN-NEXT:    s_waitcnt lgkmcnt(0)
12; GCN-NEXT:    global_load_dwordx4 v[0:3], v16, s[2:3]
13; GCN-NEXT:    global_load_dwordx4 v[4:7], v16, s[2:3] offset:16
14; GCN-NEXT:    global_load_dwordx4 v[8:11], v16, s[2:3] offset:32
15; GCN-NEXT:    global_load_dwordx4 v[12:15], v16, s[2:3] offset:48
16; GCN-NEXT:    s_waitcnt vmcnt(3)
17; GCN-NEXT:    global_store_dwordx4 v16, v[0:3], s[4:5]
18; GCN-NEXT:    s_waitcnt vmcnt(3)
19; GCN-NEXT:    global_store_dwordx4 v16, v[4:7], s[4:5] offset:16
20; GCN-NEXT:    s_waitcnt vmcnt(3)
21; GCN-NEXT:    global_store_dwordx4 v16, v[8:11], s[4:5] offset:32
22; GCN-NEXT:    s_waitcnt vmcnt(3)
23; GCN-NEXT:    global_store_dwordx4 v16, v[12:15], s[4:5] offset:48
24; GCN-NEXT:    s_endpgm
25;
26; GCN-SCRATCH-LABEL: vector_clause:
27; GCN-SCRATCH:       ; %bb.0: ; %bb
28; GCN-SCRATCH-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
29; GCN-SCRATCH-NEXT:    v_lshlrev_b32_e32 v16, 4, v0
30; GCN-SCRATCH-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
31; GCN-SCRATCH-NEXT:    s_waitcnt lgkmcnt(0)
32; GCN-SCRATCH-NEXT:    s_clause 0x3
33; GCN-SCRATCH-NEXT:    global_load_dwordx4 v[0:3], v16, s[2:3]
34; GCN-SCRATCH-NEXT:    global_load_dwordx4 v[4:7], v16, s[2:3] offset:16
35; GCN-SCRATCH-NEXT:    global_load_dwordx4 v[8:11], v16, s[2:3] offset:32
36; GCN-SCRATCH-NEXT:    global_load_dwordx4 v[12:15], v16, s[2:3] offset:48
37; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(3)
38; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[0:3], s[0:1]
39; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(2)
40; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
41; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(1)
42; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
43; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
44; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
45; GCN-SCRATCH-NEXT:    s_endpgm
46bb:
47  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
48  %tmp2 = zext i32 %tmp to i64
49  %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
50  %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
51  %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
52  %tmp6 = add nuw nsw i64 %tmp2, 1
53  %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
54  %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
55  %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
56  %tmp10 = add nuw nsw i64 %tmp2, 2
57  %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
58  %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
59  %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
60  %tmp14 = add nuw nsw i64 %tmp2, 3
61  %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
62  %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
63  %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
64  store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
65  store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
66  store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
67  store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
68  ret void
69}
70
71define amdgpu_kernel void @scalar_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
72; GCN-LABEL: scalar_clause:
73; GCN:       ; %bb.0: ; %bb
74; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
75; GCN-NEXT:    s_load_dwordx2 s[16:17], s[0:1], 0x2c
76; GCN-NEXT:    v_mov_b32_e32 v12, 0
77; GCN-NEXT:    s_waitcnt lgkmcnt(0)
78; GCN-NEXT:    s_load_dwordx4 s[0:3], s[12:13], 0x0
79; GCN-NEXT:    s_load_dwordx4 s[4:7], s[12:13], 0x10
80; GCN-NEXT:    s_load_dwordx4 s[8:11], s[12:13], 0x20
81; GCN-NEXT:    s_nop 0
82; GCN-NEXT:    s_load_dwordx4 s[12:15], s[12:13], 0x30
83; GCN-NEXT:    s_waitcnt lgkmcnt(0)
84; GCN-NEXT:    v_mov_b32_e32 v0, s0
85; GCN-NEXT:    v_mov_b32_e32 v1, s1
86; GCN-NEXT:    v_mov_b32_e32 v2, s2
87; GCN-NEXT:    v_mov_b32_e32 v3, s3
88; GCN-NEXT:    v_mov_b32_e32 v4, s4
89; GCN-NEXT:    v_mov_b32_e32 v8, s8
90; GCN-NEXT:    v_mov_b32_e32 v5, s5
91; GCN-NEXT:    v_mov_b32_e32 v6, s6
92; GCN-NEXT:    v_mov_b32_e32 v7, s7
93; GCN-NEXT:    v_mov_b32_e32 v9, s9
94; GCN-NEXT:    v_mov_b32_e32 v10, s10
95; GCN-NEXT:    v_mov_b32_e32 v11, s11
96; GCN-NEXT:    global_store_dwordx4 v12, v[0:3], s[16:17]
97; GCN-NEXT:    global_store_dwordx4 v12, v[4:7], s[16:17] offset:16
98; GCN-NEXT:    global_store_dwordx4 v12, v[8:11], s[16:17] offset:32
99; GCN-NEXT:    v_mov_b32_e32 v0, s12
100; GCN-NEXT:    v_mov_b32_e32 v1, s13
101; GCN-NEXT:    v_mov_b32_e32 v2, s14
102; GCN-NEXT:    v_mov_b32_e32 v3, s15
103; GCN-NEXT:    global_store_dwordx4 v12, v[0:3], s[16:17] offset:48
104; GCN-NEXT:    s_endpgm
105;
106; GCN-SCRATCH-LABEL: scalar_clause:
107; GCN-SCRATCH:       ; %bb.0: ; %bb
108; GCN-SCRATCH-NEXT:    s_clause 0x1
109; GCN-SCRATCH-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
110; GCN-SCRATCH-NEXT:    s_load_dwordx2 s[16:17], s[0:1], 0x2c
111; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v16, 0
112; GCN-SCRATCH-NEXT:    s_waitcnt lgkmcnt(0)
113; GCN-SCRATCH-NEXT:    s_clause 0x3
114; GCN-SCRATCH-NEXT:    s_load_dwordx4 s[0:3], s[12:13], 0x0
115; GCN-SCRATCH-NEXT:    s_load_dwordx4 s[4:7], s[12:13], 0x10
116; GCN-SCRATCH-NEXT:    s_load_dwordx4 s[8:11], s[12:13], 0x20
117; GCN-SCRATCH-NEXT:    s_load_dwordx4 s[12:15], s[12:13], 0x30
118; GCN-SCRATCH-NEXT:    s_waitcnt lgkmcnt(0)
119; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v0, s0
120; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v1, s1
121; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v2, s2
122; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v3, s3
123; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v4, s4
124; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v5, s5
125; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v6, s6
126; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v7, s7
127; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v8, s8
128; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v9, s9
129; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v10, s10
130; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v11, s11
131; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v12, s12
132; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v13, s13
133; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v14, s14
134; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v15, s15
135; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[0:3], s[16:17]
136; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
137; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
138; GCN-SCRATCH-NEXT:    global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
139; GCN-SCRATCH-NEXT:    s_endpgm
140bb:
141  %tmp = load <4 x i32>, <4 x i32> addrspace(1)* %arg, align 16
142  %tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 1
143  %tmp3 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp2, align 16
144  %tmp4 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 1
145  %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 2
146  %tmp6 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp5, align 16
147  %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 2
148  %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 3
149  %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
150  %tmp10 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 3
151  store <4 x i32> %tmp, <4 x i32> addrspace(1)* %arg1, align 16
152  store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %tmp4, align 16
153  store <4 x i32> %tmp6, <4 x i32> addrspace(1)* %tmp7, align 16
154  store <4 x i32> %tmp9, <4 x i32> addrspace(1)* %tmp10, align 16
155  ret void
156}
157
158define void @mubuf_clause(<4 x i32> addrspace(5)* noalias nocapture readonly %arg, <4 x i32> addrspace(5)* noalias nocapture %arg1) {
159; GCN-LABEL: mubuf_clause:
160; GCN:       ; %bb.0: ; %bb
161; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
162; GCN-NEXT:    v_and_b32_e32 v2, 0x3ff, v31
163; GCN-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
164; GCN-NEXT:    v_add_u32_e32 v0, v0, v2
165; GCN-NEXT:    buffer_load_dword v3, v0, s[0:3], 0 offen offset:12
166; GCN-NEXT:    buffer_load_dword v4, v0, s[0:3], 0 offen offset:8
167; GCN-NEXT:    buffer_load_dword v5, v0, s[0:3], 0 offen offset:4
168; GCN-NEXT:    buffer_load_dword v6, v0, s[0:3], 0 offen
169; GCN-NEXT:    buffer_load_dword v7, v0, s[0:3], 0 offen offset:28
170; GCN-NEXT:    buffer_load_dword v8, v0, s[0:3], 0 offen offset:24
171; GCN-NEXT:    buffer_load_dword v9, v0, s[0:3], 0 offen offset:20
172; GCN-NEXT:    buffer_load_dword v10, v0, s[0:3], 0 offen offset:16
173; GCN-NEXT:    buffer_load_dword v11, v0, s[0:3], 0 offen offset:44
174; GCN-NEXT:    buffer_load_dword v12, v0, s[0:3], 0 offen offset:40
175; GCN-NEXT:    buffer_load_dword v13, v0, s[0:3], 0 offen offset:36
176; GCN-NEXT:    buffer_load_dword v14, v0, s[0:3], 0 offen offset:32
177; GCN-NEXT:    buffer_load_dword v15, v0, s[0:3], 0 offen offset:60
178; GCN-NEXT:    buffer_load_dword v16, v0, s[0:3], 0 offen offset:56
179; GCN-NEXT:    buffer_load_dword v17, v0, s[0:3], 0 offen offset:52
180; GCN-NEXT:    s_nop 0
181; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen offset:48
182; GCN-NEXT:    v_add_u32_e32 v1, v1, v2
183; GCN-NEXT:    s_waitcnt vmcnt(15)
184; GCN-NEXT:    buffer_store_dword v3, v1, s[0:3], 0 offen offset:12
185; GCN-NEXT:    s_waitcnt vmcnt(15)
186; GCN-NEXT:    buffer_store_dword v4, v1, s[0:3], 0 offen offset:8
187; GCN-NEXT:    s_waitcnt vmcnt(15)
188; GCN-NEXT:    buffer_store_dword v5, v1, s[0:3], 0 offen offset:4
189; GCN-NEXT:    s_waitcnt vmcnt(15)
190; GCN-NEXT:    buffer_store_dword v6, v1, s[0:3], 0 offen
191; GCN-NEXT:    s_waitcnt vmcnt(15)
192; GCN-NEXT:    buffer_store_dword v7, v1, s[0:3], 0 offen offset:28
193; GCN-NEXT:    s_waitcnt vmcnt(15)
194; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen offset:24
195; GCN-NEXT:    s_waitcnt vmcnt(15)
196; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen offset:20
197; GCN-NEXT:    s_waitcnt vmcnt(15)
198; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen offset:16
199; GCN-NEXT:    s_waitcnt vmcnt(15)
200; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen offset:44
201; GCN-NEXT:    s_waitcnt vmcnt(15)
202; GCN-NEXT:    buffer_store_dword v12, v1, s[0:3], 0 offen offset:40
203; GCN-NEXT:    s_waitcnt vmcnt(15)
204; GCN-NEXT:    buffer_store_dword v13, v1, s[0:3], 0 offen offset:36
205; GCN-NEXT:    s_waitcnt vmcnt(15)
206; GCN-NEXT:    buffer_store_dword v14, v1, s[0:3], 0 offen offset:32
207; GCN-NEXT:    s_waitcnt vmcnt(15)
208; GCN-NEXT:    buffer_store_dword v15, v1, s[0:3], 0 offen offset:60
209; GCN-NEXT:    s_waitcnt vmcnt(15)
210; GCN-NEXT:    buffer_store_dword v16, v1, s[0:3], 0 offen offset:56
211; GCN-NEXT:    s_waitcnt vmcnt(15)
212; GCN-NEXT:    buffer_store_dword v17, v1, s[0:3], 0 offen offset:52
213; GCN-NEXT:    s_waitcnt vmcnt(15)
214; GCN-NEXT:    buffer_store_dword v0, v1, s[0:3], 0 offen offset:48
215; GCN-NEXT:    s_waitcnt vmcnt(0)
216; GCN-NEXT:    s_setpc_b64 s[30:31]
217;
218; GCN-SCRATCH-LABEL: mubuf_clause:
219; GCN-SCRATCH:       ; %bb.0: ; %bb
220; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
221; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
222; GCN-SCRATCH-NEXT:    v_and_b32_e32 v2, 0x3ff, v31
223; GCN-SCRATCH-NEXT:    v_lshlrev_b32_e32 v18, 4, v2
224; GCN-SCRATCH-NEXT:    v_add_nc_u32_e32 v0, v0, v18
225; GCN-SCRATCH-NEXT:    s_clause 0x3
226; GCN-SCRATCH-NEXT:    scratch_load_dwordx4 v[2:5], v0, off
227; GCN-SCRATCH-NEXT:    scratch_load_dwordx4 v[6:9], v0, off offset:16
228; GCN-SCRATCH-NEXT:    scratch_load_dwordx4 v[10:13], v0, off offset:32
229; GCN-SCRATCH-NEXT:    scratch_load_dwordx4 v[14:17], v0, off offset:48
230; GCN-SCRATCH-NEXT:    v_add_nc_u32_e32 v0, v1, v18
231; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(3)
232; GCN-SCRATCH-NEXT:    scratch_store_dwordx4 v0, v[2:5], off
233; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(2)
234; GCN-SCRATCH-NEXT:    scratch_store_dwordx4 v0, v[6:9], off offset:16
235; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(1)
236; GCN-SCRATCH-NEXT:    scratch_store_dwordx4 v0, v[10:13], off offset:32
237; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
238; GCN-SCRATCH-NEXT:    scratch_store_dwordx4 v0, v[14:17], off offset:48
239; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
240; GCN-SCRATCH-NEXT:    s_setpc_b64 s[30:31]
241bb:
242  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
243  %tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp
244  %tmp3 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp2, align 16
245  %tmp4 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp
246  %tmp5 = add nuw nsw i32 %tmp, 1
247  %tmp6 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp5
248  %tmp7 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp6, align 16
249  %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp5
250  %tmp9 = add nuw nsw i32 %tmp, 2
251  %tmp10 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp9
252  %tmp11 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp10, align 16
253  %tmp12 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp9
254  %tmp13 = add nuw nsw i32 %tmp, 3
255  %tmp14 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp13
256  %tmp15 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp14, align 16
257  %tmp16 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp13
258  store <4 x i32> %tmp3, <4 x i32> addrspace(5)* %tmp4, align 16
259  store <4 x i32> %tmp7, <4 x i32> addrspace(5)* %tmp8, align 16
260  store <4 x i32> %tmp11, <4 x i32> addrspace(5)* %tmp12, align 16
261  store <4 x i32> %tmp15, <4 x i32> addrspace(5)* %tmp16, align 16
262  ret void
263}
264
265define amdgpu_kernel void @vector_clause_indirect(i64 addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture readnone %arg1, <4 x i32> addrspace(1)* noalias nocapture %arg2) {
266; GCN-LABEL: vector_clause_indirect:
267; GCN:       ; %bb.0: ; %bb
268; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
269; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
270; GCN-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
271; GCN-NEXT:    s_waitcnt lgkmcnt(0)
272; GCN-NEXT:    global_load_dwordx2 v[8:9], v0, s[2:3]
273; GCN-NEXT:    s_waitcnt vmcnt(0)
274; GCN-NEXT:    global_load_dwordx4 v[0:3], v[8:9], off
275; GCN-NEXT:    global_load_dwordx4 v[4:7], v[8:9], off offset:16
276; GCN-NEXT:    v_mov_b32_e32 v8, 0
277; GCN-NEXT:    s_waitcnt vmcnt(1)
278; GCN-NEXT:    global_store_dwordx4 v8, v[0:3], s[4:5]
279; GCN-NEXT:    s_waitcnt vmcnt(1)
280; GCN-NEXT:    global_store_dwordx4 v8, v[4:7], s[4:5] offset:16
281; GCN-NEXT:    s_endpgm
282;
283; GCN-SCRATCH-LABEL: vector_clause_indirect:
284; GCN-SCRATCH:       ; %bb.0: ; %bb
285; GCN-SCRATCH-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
286; GCN-SCRATCH-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
287; GCN-SCRATCH-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
288; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v8, 0
289; GCN-SCRATCH-NEXT:    s_waitcnt lgkmcnt(0)
290; GCN-SCRATCH-NEXT:    global_load_dwordx2 v[4:5], v0, s[2:3]
291; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
292; GCN-SCRATCH-NEXT:    s_clause 0x1
293; GCN-SCRATCH-NEXT:    global_load_dwordx4 v[0:3], v[4:5], off
294; GCN-SCRATCH-NEXT:    global_load_dwordx4 v[4:7], v[4:5], off offset:16
295; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(1)
296; GCN-SCRATCH-NEXT:    global_store_dwordx4 v8, v[0:3], s[0:1]
297; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
298; GCN-SCRATCH-NEXT:    global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
299; GCN-SCRATCH-NEXT:    s_endpgm
300bb:
301  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
302  %tmp3 = zext i32 %tmp to i64
303  %tmp4 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp3
304  %tmp5 = bitcast i64 addrspace(1)* %tmp4 to <4 x i32> addrspace(1)* addrspace(1)*
305  %tmp6 = load <4 x i32> addrspace(1)*, <4 x i32> addrspace(1)* addrspace(1)* %tmp5, align 8
306  %tmp7 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp6, align 16
307  %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %tmp6, i64 1
308  %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
309  store <4 x i32> %tmp7, <4 x i32> addrspace(1)* %arg2, align 16
310  %tmp10 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg2, i64 1
311  store <4 x i32> %tmp9, <4 x i32> addrspace(1)* %tmp10, align 16
312  ret void
313}
314
315define void @load_global_d16_hi(i16 addrspace(1)* %in, i16 %reg, <2 x i16> addrspace(1)* %out) {
316; GCN-LABEL: load_global_d16_hi:
317; GCN:       ; %bb.0: ; %entry
318; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
319; GCN-NEXT:    v_mov_b32_e32 v5, v2
320; GCN-NEXT:    global_load_short_d16_hi v5, v[0:1], off
321; GCN-NEXT:    s_nop 0
322; GCN-NEXT:    global_load_short_d16_hi v2, v[0:1], off offset:64
323; GCN-NEXT:    s_waitcnt vmcnt(1)
324; GCN-NEXT:    global_store_dword v[3:4], v5, off
325; GCN-NEXT:    s_waitcnt vmcnt(1)
326; GCN-NEXT:    global_store_dword v[3:4], v2, off offset:128
327; GCN-NEXT:    s_waitcnt vmcnt(0)
328; GCN-NEXT:    s_setpc_b64 s[30:31]
329;
330; GCN-SCRATCH-LABEL: load_global_d16_hi:
331; GCN-SCRATCH:       ; %bb.0: ; %entry
332; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
333; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
334; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v5, v2
335; GCN-SCRATCH-NEXT:    s_clause 0x1
336; GCN-SCRATCH-NEXT:    global_load_short_d16_hi v5, v[0:1], off
337; GCN-SCRATCH-NEXT:    global_load_short_d16_hi v2, v[0:1], off offset:64
338; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(1)
339; GCN-SCRATCH-NEXT:    global_store_dword v[3:4], v5, off
340; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
341; GCN-SCRATCH-NEXT:    global_store_dword v[3:4], v2, off offset:128
342; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
343; GCN-SCRATCH-NEXT:    s_setpc_b64 s[30:31]
344entry:
345  %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 32
346  %load1 = load i16, i16 addrspace(1)* %in
347  %load2 = load i16, i16 addrspace(1)* %gep
348  %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
349  %build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
350  store <2 x i16> %build1, <2 x i16> addrspace(1)* %out
351  %build2 = insertelement <2 x i16> undef, i16 %reg, i32 0
352  %build3 = insertelement <2 x i16> %build2, i16 %load2, i32 1
353  %gep2 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 32
354  store <2 x i16> %build3, <2 x i16> addrspace(1)* %gep2
355  ret void
356}
357
358define void @load_global_d16_lo(i16 addrspace(1)* %in, i32 %reg, <2 x i16> addrspace(1)* %out) {
359; GCN-LABEL: load_global_d16_lo:
360; GCN:       ; %bb.0: ; %entry
361; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
362; GCN-NEXT:    v_mov_b32_e32 v5, v2
363; GCN-NEXT:    global_load_short_d16 v5, v[0:1], off
364; GCN-NEXT:    s_nop 0
365; GCN-NEXT:    global_load_short_d16 v2, v[0:1], off offset:64
366; GCN-NEXT:    s_waitcnt vmcnt(1)
367; GCN-NEXT:    global_store_dword v[3:4], v5, off
368; GCN-NEXT:    s_waitcnt vmcnt(1)
369; GCN-NEXT:    global_store_dword v[3:4], v2, off offset:128
370; GCN-NEXT:    s_waitcnt vmcnt(0)
371; GCN-NEXT:    s_setpc_b64 s[30:31]
372;
373; GCN-SCRATCH-LABEL: load_global_d16_lo:
374; GCN-SCRATCH:       ; %bb.0: ; %entry
375; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
376; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
377; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v5, v2
378; GCN-SCRATCH-NEXT:    s_clause 0x1
379; GCN-SCRATCH-NEXT:    global_load_short_d16 v5, v[0:1], off
380; GCN-SCRATCH-NEXT:    global_load_short_d16 v2, v[0:1], off offset:64
381; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(1)
382; GCN-SCRATCH-NEXT:    global_store_dword v[3:4], v5, off
383; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
384; GCN-SCRATCH-NEXT:    global_store_dword v[3:4], v2, off offset:128
385; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
386; GCN-SCRATCH-NEXT:    s_setpc_b64 s[30:31]
387entry:
388  %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 32
389  %reg.bc1 = bitcast i32 %reg to <2 x i16>
390  %reg.bc2 = bitcast i32 %reg to <2 x i16>
391  %load1 = load i16, i16 addrspace(1)* %in
392  %load2 = load i16, i16 addrspace(1)* %gep
393  %build1 = insertelement <2 x i16> %reg.bc1, i16 %load1, i32 0
394  %build2 = insertelement <2 x i16> %reg.bc2, i16 %load2, i32 0
395  %gep2 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 32
396  store <2 x i16> %build1, <2 x i16> addrspace(1)* %out
397  store <2 x i16> %build2, <2 x i16> addrspace(1)* %gep2
398  ret void
399}
400
401define amdgpu_kernel void @flat_scratch_load(float %a, float %b, <8 x i32> %desc) {
402; GCN-LABEL: flat_scratch_load:
403; GCN:       ; %bb.0: ; %.entry
404; GCN-NEXT:    s_mov_b32 s16, SCRATCH_RSRC_DWORD0
405; GCN-NEXT:    s_mov_b32 s17, SCRATCH_RSRC_DWORD1
406; GCN-NEXT:    s_mov_b32 s18, -1
407; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
408; GCN-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x44
409; GCN-NEXT:    s_mov_b32 s19, 0xe00000
410; GCN-NEXT:    s_add_u32 s16, s16, s3
411; GCN-NEXT:    s_addc_u32 s17, s17, 0
412; GCN-NEXT:    v_mov_b32_e32 v0, 0x40b00000
413; GCN-NEXT:    buffer_store_dword v0, off, s[16:19], 0 offset:4
414; GCN-NEXT:    s_waitcnt vmcnt(0)
415; GCN-NEXT:    s_brev_b32 s0, 1
416; GCN-NEXT:    s_waitcnt lgkmcnt(0)
417; GCN-NEXT:    v_mov_b32_e32 v0, s12
418; GCN-NEXT:    s_mov_b32 s3, 0
419; GCN-NEXT:    s_mov_b32 s1, s0
420; GCN-NEXT:    s_mov_b32 s2, s0
421; GCN-NEXT:    v_mov_b32_e32 v1, s13
422; GCN-NEXT:    ;;#ASMSTART
423; GCN-NEXT:    ;;#ASMEND
424; GCN-NEXT:    buffer_load_dword v2, off, s[16:19], 0 offset:4
425; GCN-NEXT:    s_nop 0
426; GCN-NEXT:    image_sample v0, v[0:1], s[4:11], s[0:3] dmask:0x1
427; GCN-NEXT:    s_waitcnt vmcnt(0)
428; GCN-NEXT:    v_add_f32_e32 v0, v2, v0
429; GCN-NEXT:    exp mrt0 v0, off, off, off done vm
430; GCN-NEXT:    s_endpgm
431;
432; GCN-SCRATCH-LABEL: flat_scratch_load:
433; GCN-SCRATCH:       ; %bb.0: ; %.entry
434; GCN-SCRATCH-NEXT:    s_add_u32 s2, s2, s5
435; GCN-SCRATCH-NEXT:    s_addc_u32 s3, s3, 0
436; GCN-SCRATCH-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
437; GCN-SCRATCH-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
438; GCN-SCRATCH-NEXT:    s_clause 0x1
439; GCN-SCRATCH-NEXT:    s_load_dwordx2 s[10:11], s[0:1], 0x24
440; GCN-SCRATCH-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x44
441; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v0, 0x40b00000
442; GCN-SCRATCH-NEXT:    s_brev_b32 s8, 1
443; GCN-SCRATCH-NEXT:    s_mov_b32 s9, s8
444; GCN-SCRATCH-NEXT:    scratch_store_dword off, v0, off offset:4
445; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
446; GCN-SCRATCH-NEXT:    ;;#ASMSTART
447; GCN-SCRATCH-NEXT:    ;;#ASMEND
448; GCN-SCRATCH-NEXT:    scratch_load_dword v2, off, off offset:4
449; GCN-SCRATCH-NEXT:    s_waitcnt lgkmcnt(0)
450; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v0, s10
451; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v1, s11
452; GCN-SCRATCH-NEXT:    s_mov_b32 s11, 0
453; GCN-SCRATCH-NEXT:    s_mov_b32 s10, s8
454; GCN-SCRATCH-NEXT:    image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
455; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
456; GCN-SCRATCH-NEXT:    v_add_f32_e32 v0, v2, v0
457; GCN-SCRATCH-NEXT:    exp mrt0 v0, off, off, off done vm
458; GCN-SCRATCH-NEXT:    s_endpgm
459.entry:
460  %alloca = alloca float, align 4, addrspace(5)
461  store volatile float 5.5, float addrspace(5)* %alloca
462  call void asm sideeffect "", ""()
463  ; There was a bug with flat scratch instructions that do not not use any address registers (ST mode).
464  ; To trigger, the scratch_load has to be immediately before the image_sample in MIR.
465  %load = load float, float addrspace(5)* %alloca
466  %val = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 9, float %a, float %b, <8 x i32> %desc, <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 0>, i1 false, i32 0, i32 0)
467  %val0 = extractelement <2 x float> %val, i32 0
468  %valadd = fadd float %load, %val0
469  call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 1, float %valadd, float undef, float undef, float undef, i1 immarg true, i1 immarg true)
470  ret void
471}
472
473define amdgpu_kernel void @flat_scratch_load_clause(float %a, float %b, <8 x i32> %desc) {
474; GCN-LABEL: flat_scratch_load_clause:
475; GCN:       ; %bb.0: ; %.entry
476; GCN-NEXT:    s_mov_b32 s4, SCRATCH_RSRC_DWORD0
477; GCN-NEXT:    s_mov_b32 s5, SCRATCH_RSRC_DWORD1
478; GCN-NEXT:    s_mov_b32 s6, -1
479; GCN-NEXT:    s_mov_b32 s7, 0xe00000
480; GCN-NEXT:    s_add_u32 s4, s4, s3
481; GCN-NEXT:    s_addc_u32 s5, s5, 0
482; GCN-NEXT:    v_mov_b32_e32 v0, 0x40b00000
483; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0 offset:4
484; GCN-NEXT:    s_waitcnt vmcnt(0)
485; GCN-NEXT:    v_mov_b32_e32 v0, 0x40d00000
486; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0 offset:8
487; GCN-NEXT:    s_waitcnt vmcnt(0)
488; GCN-NEXT:    ;;#ASMSTART
489; GCN-NEXT:    ;;#ASMEND
490; GCN-NEXT:    buffer_load_dword v0, off, s[4:7], 0 offset:4
491; GCN-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:8
492; GCN-NEXT:    s_waitcnt vmcnt(0)
493; GCN-NEXT:    v_add_f32_e32 v0, v0, v1
494; GCN-NEXT:    exp mrt0 v0, off, off, off done vm
495; GCN-NEXT:    s_endpgm
496;
497; GCN-SCRATCH-LABEL: flat_scratch_load_clause:
498; GCN-SCRATCH:       ; %bb.0: ; %.entry
499; GCN-SCRATCH-NEXT:    s_add_u32 s2, s2, s5
500; GCN-SCRATCH-NEXT:    s_addc_u32 s3, s3, 0
501; GCN-SCRATCH-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
502; GCN-SCRATCH-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
503; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v0, 0x40b00000
504; GCN-SCRATCH-NEXT:    v_mov_b32_e32 v1, 0x40d00000
505; GCN-SCRATCH-NEXT:    scratch_store_dword off, v0, off offset:4
506; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
507; GCN-SCRATCH-NEXT:    scratch_store_dword off, v1, off offset:8
508; GCN-SCRATCH-NEXT:    s_waitcnt_vscnt null, 0x0
509; GCN-SCRATCH-NEXT:    ;;#ASMSTART
510; GCN-SCRATCH-NEXT:    ;;#ASMEND
511; GCN-SCRATCH-NEXT:    s_clause 0x1
512; GCN-SCRATCH-NEXT:    scratch_load_dword v0, off, off offset:4
513; GCN-SCRATCH-NEXT:    scratch_load_dword v1, off, off offset:8
514; GCN-SCRATCH-NEXT:    s_waitcnt vmcnt(0)
515; GCN-SCRATCH-NEXT:    v_add_f32_e32 v0, v0, v1
516; GCN-SCRATCH-NEXT:    exp mrt0 v0, off, off, off done vm
517; GCN-SCRATCH-NEXT:    s_endpgm
518.entry:
519  %alloca = alloca float, align 4, addrspace(5)
520  %alloca2 = alloca float, align 4, addrspace(5)
521  store volatile float 5.5, float addrspace(5)* %alloca
522  store volatile float 6.5, float addrspace(5)* %alloca2
523  call void asm sideeffect "", ""()
524  %load0 = load float, float addrspace(5)* %alloca
525  %load1 = load float, float addrspace(5)* %alloca2
526  %valadd = fadd float %load0, %load1
527  call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 1, float %valadd, float undef, float undef, float undef, i1 immarg true, i1 immarg true)
528  ret void
529}
530
531declare i32 @llvm.amdgcn.workitem.id.x()
532declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)
533declare <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg)
534