1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,VI
3; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,GFX9
4
5; FIXME: Need to handle non-uniform case for function below (load without gep).
6define amdgpu_kernel void @v_test_imax_sge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
7; VI-LABEL: v_test_imax_sge_i16:
8; VI:       ; %bb.0:
9; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
10; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
11; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
12; VI-NEXT:    s_waitcnt lgkmcnt(0)
13; VI-NEXT:    v_mov_b32_e32 v1, s7
14; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
15; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
16; VI-NEXT:    v_mov_b32_e32 v3, s1
17; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
18; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
19; VI-NEXT:    flat_load_ushort v0, v[0:1]
20; VI-NEXT:    flat_load_ushort v1, v[2:3]
21; VI-NEXT:    v_mov_b32_e32 v5, s5
22; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
23; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
24; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
25; VI-NEXT:    v_max_i16_e32 v0, v0, v1
26; VI-NEXT:    flat_store_short v[4:5], v0
27; VI-NEXT:    s_endpgm
28;
29; GFX9-LABEL: v_test_imax_sge_i16:
30; GFX9:       ; %bb.0:
31; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
32; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
33; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
34; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
35; GFX9-NEXT:    v_mov_b32_e32 v1, s7
36; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
37; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
38; GFX9-NEXT:    v_mov_b32_e32 v3, s1
39; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
40; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
41; GFX9-NEXT:    global_load_ushort v0, v[0:1], off
42; GFX9-NEXT:    global_load_ushort v1, v[2:3], off
43; GFX9-NEXT:    v_mov_b32_e32 v5, s5
44; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
45; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
46; GFX9-NEXT:    s_waitcnt vmcnt(0)
47; GFX9-NEXT:    v_max_i16_e32 v0, v0, v1
48; GFX9-NEXT:    global_store_short v[4:5], v0, off
49; GFX9-NEXT:    s_endpgm
50  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
51  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
52  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
53  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
54  %a = load i16, i16 addrspace(1)* %gep0, align 4
55  %b = load i16, i16 addrspace(1)* %gep1, align 4
56  %cmp = icmp sge i16 %a, %b
57  %val = select i1 %cmp, i16 %a, i16 %b
58  store i16 %val, i16 addrspace(1)* %outgep, align 4
59  ret void
60}
61
62; FIXME: Need to handle non-uniform case for function below (load without gep).
63define amdgpu_kernel void @v_test_imax_sge_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
64; VI-LABEL: v_test_imax_sge_v2i16:
65; VI:       ; %bb.0:
66; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
67; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
68; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
69; VI-NEXT:    s_waitcnt lgkmcnt(0)
70; VI-NEXT:    v_mov_b32_e32 v1, s7
71; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
72; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
73; VI-NEXT:    v_mov_b32_e32 v3, s1
74; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
75; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
76; VI-NEXT:    flat_load_dword v0, v[0:1]
77; VI-NEXT:    flat_load_dword v1, v[2:3]
78; VI-NEXT:    v_mov_b32_e32 v5, s5
79; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
80; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
81; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
82; VI-NEXT:    v_max_i16_e32 v2, v0, v1
83; VI-NEXT:    v_max_i16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
84; VI-NEXT:    v_or_b32_e32 v0, v2, v0
85; VI-NEXT:    flat_store_dword v[4:5], v0
86; VI-NEXT:    s_endpgm
87;
88; GFX9-LABEL: v_test_imax_sge_v2i16:
89; GFX9:       ; %bb.0:
90; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
91; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
92; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
93; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
94; GFX9-NEXT:    v_mov_b32_e32 v1, s7
95; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
96; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
97; GFX9-NEXT:    v_mov_b32_e32 v3, s1
98; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
99; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
100; GFX9-NEXT:    global_load_dword v0, v[0:1], off
101; GFX9-NEXT:    global_load_dword v1, v[2:3], off
102; GFX9-NEXT:    v_mov_b32_e32 v5, s5
103; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
104; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
105; GFX9-NEXT:    s_waitcnt vmcnt(0)
106; GFX9-NEXT:    v_pk_max_i16 v0, v0, v1
107; GFX9-NEXT:    global_store_dword v[4:5], v0, off
108; GFX9-NEXT:    s_endpgm
109  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
110  %gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
111  %gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
112  %outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
113  %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
114  %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
115  %cmp = icmp sge <2 x i16> %a, %b
116  %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
117  store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
118  ret void
119}
120
121; FIXME: Need to handle non-uniform case for function below (load without gep).
122define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %aptr, <3 x i16> addrspace(1)* %bptr) nounwind {
123; VI-LABEL: v_test_imax_sge_v3i16:
124; VI:       ; %bb.0:
125; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
126; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
127; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
128; VI-NEXT:    s_waitcnt lgkmcnt(0)
129; VI-NEXT:    v_mov_b32_e32 v1, s7
130; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
131; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
132; VI-NEXT:    v_mov_b32_e32 v3, s1
133; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
134; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
135; VI-NEXT:    v_mov_b32_e32 v5, s5
136; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
137; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
138; VI-NEXT:    v_add_u32_e32 v6, vcc, 4, v0
139; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
140; VI-NEXT:    flat_load_ushort v6, v[6:7]
141; VI-NEXT:    flat_load_dword v7, v[0:1]
142; VI-NEXT:    v_add_u32_e32 v0, vcc, 4, v2
143; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
144; VI-NEXT:    flat_load_ushort v0, v[0:1]
145; VI-NEXT:    flat_load_dword v8, v[2:3]
146; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v4
147; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
148; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
149; VI-NEXT:    v_max_i16_e32 v0, v6, v0
150; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
151; VI-NEXT:    v_max_i16_e32 v1, v7, v8
152; VI-NEXT:    v_max_i16_sdwa v7, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
153; VI-NEXT:    v_or_b32_e32 v1, v1, v7
154; VI-NEXT:    flat_store_short v[2:3], v0
155; VI-NEXT:    flat_store_dword v[4:5], v1
156; VI-NEXT:    s_endpgm
157;
158; GFX9-LABEL: v_test_imax_sge_v3i16:
159; GFX9:       ; %bb.0:
160; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
161; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
162; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
163; GFX9-NEXT:    v_mov_b32_e32 v6, 0
164; GFX9-NEXT:    v_mov_b32_e32 v7, 0
165; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
166; GFX9-NEXT:    v_mov_b32_e32 v1, s7
167; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
168; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
169; GFX9-NEXT:    v_mov_b32_e32 v3, s1
170; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
171; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
172; GFX9-NEXT:    global_load_short_d16 v7, v[0:1], off offset:4
173; GFX9-NEXT:    global_load_dword v0, v[0:1], off
174; GFX9-NEXT:    global_load_short_d16 v6, v[2:3], off offset:4
175; GFX9-NEXT:    global_load_dword v1, v[2:3], off
176; GFX9-NEXT:    v_mov_b32_e32 v5, s5
177; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
178; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
179; GFX9-NEXT:    s_waitcnt vmcnt(0)
180; GFX9-NEXT:    v_pk_max_i16 v0, v0, v1
181; GFX9-NEXT:    v_pk_max_i16 v1, v7, v6
182; GFX9-NEXT:    global_store_short v[4:5], v1, off offset:4
183; GFX9-NEXT:    global_store_dword v[4:5], v0, off
184; GFX9-NEXT:    s_endpgm
185  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
186  %gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid
187  %gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid
188  %outgep = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %out, i32 %tid
189  %a = load <3 x i16>, <3 x i16> addrspace(1)* %gep0, align 4
190  %b = load <3 x i16>, <3 x i16> addrspace(1)* %gep1, align 4
191  %cmp = icmp sge <3 x i16> %a, %b
192  %val = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
193  store <3 x i16> %val, <3 x i16> addrspace(1)* %outgep, align 4
194  ret void
195}
196
197; FIXME: Need to handle non-uniform case for function below (load without gep).
198define amdgpu_kernel void @v_test_imax_sge_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %aptr, <4 x i16> addrspace(1)* %bptr) nounwind {
199; VI-LABEL: v_test_imax_sge_v4i16:
200; VI:       ; %bb.0:
201; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
202; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
203; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
204; VI-NEXT:    s_waitcnt lgkmcnt(0)
205; VI-NEXT:    v_mov_b32_e32 v1, s7
206; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
207; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
208; VI-NEXT:    v_mov_b32_e32 v3, s1
209; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
210; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
211; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
212; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
213; VI-NEXT:    v_mov_b32_e32 v5, s5
214; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
215; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
216; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
217; VI-NEXT:    v_max_i16_e32 v6, v1, v3
218; VI-NEXT:    v_max_i16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
219; VI-NEXT:    v_max_i16_e32 v3, v0, v2
220; VI-NEXT:    v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
221; VI-NEXT:    v_or_b32_e32 v1, v6, v1
222; VI-NEXT:    v_or_b32_e32 v0, v3, v0
223; VI-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]
224; VI-NEXT:    s_endpgm
225;
226; GFX9-LABEL: v_test_imax_sge_v4i16:
227; GFX9:       ; %bb.0:
228; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
229; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
230; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
231; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
232; GFX9-NEXT:    v_mov_b32_e32 v1, s7
233; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
234; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
235; GFX9-NEXT:    v_mov_b32_e32 v3, s1
236; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
237; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
238; GFX9-NEXT:    global_load_dwordx2 v[0:1], v[0:1], off
239; GFX9-NEXT:    global_load_dwordx2 v[2:3], v[2:3], off
240; GFX9-NEXT:    v_mov_b32_e32 v5, s5
241; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
242; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
243; GFX9-NEXT:    s_waitcnt vmcnt(0)
244; GFX9-NEXT:    v_pk_max_i16 v1, v1, v3
245; GFX9-NEXT:    v_pk_max_i16 v0, v0, v2
246; GFX9-NEXT:    global_store_dwordx2 v[4:5], v[0:1], off
247; GFX9-NEXT:    s_endpgm
248  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
249  %gep0 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %aptr, i32 %tid
250  %gep1 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %bptr, i32 %tid
251  %outgep = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %out, i32 %tid
252  %a = load <4 x i16>, <4 x i16> addrspace(1)* %gep0, align 4
253  %b = load <4 x i16>, <4 x i16> addrspace(1)* %gep1, align 4
254  %cmp = icmp sge <4 x i16> %a, %b
255  %val = select <4 x i1> %cmp, <4 x i16> %a, <4 x i16> %b
256  store <4 x i16> %val, <4 x i16> addrspace(1)* %outgep, align 4
257  ret void
258}
259
260; FIXME: Need to handle non-uniform case for function below (load without gep).
261define amdgpu_kernel void @v_test_imax_sgt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
262; VI-LABEL: v_test_imax_sgt_i16:
263; VI:       ; %bb.0:
264; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
265; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
266; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
267; VI-NEXT:    s_waitcnt lgkmcnt(0)
268; VI-NEXT:    v_mov_b32_e32 v1, s7
269; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
270; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
271; VI-NEXT:    v_mov_b32_e32 v3, s1
272; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
273; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
274; VI-NEXT:    flat_load_ushort v0, v[0:1]
275; VI-NEXT:    flat_load_ushort v1, v[2:3]
276; VI-NEXT:    v_mov_b32_e32 v5, s5
277; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
278; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
279; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
280; VI-NEXT:    v_max_i16_e32 v0, v0, v1
281; VI-NEXT:    flat_store_short v[4:5], v0
282; VI-NEXT:    s_endpgm
283;
284; GFX9-LABEL: v_test_imax_sgt_i16:
285; GFX9:       ; %bb.0:
286; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
287; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
288; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
289; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
290; GFX9-NEXT:    v_mov_b32_e32 v1, s7
291; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
292; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
293; GFX9-NEXT:    v_mov_b32_e32 v3, s1
294; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
295; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
296; GFX9-NEXT:    global_load_ushort v0, v[0:1], off
297; GFX9-NEXT:    global_load_ushort v1, v[2:3], off
298; GFX9-NEXT:    v_mov_b32_e32 v5, s5
299; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
300; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
301; GFX9-NEXT:    s_waitcnt vmcnt(0)
302; GFX9-NEXT:    v_max_i16_e32 v0, v0, v1
303; GFX9-NEXT:    global_store_short v[4:5], v0, off
304; GFX9-NEXT:    s_endpgm
305  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
306  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
307  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
308  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
309  %a = load i16, i16 addrspace(1)* %gep0, align 4
310  %b = load i16, i16 addrspace(1)* %gep1, align 4
311  %cmp = icmp sgt i16 %a, %b
312  %val = select i1 %cmp, i16 %a, i16 %b
313  store i16 %val, i16 addrspace(1)* %outgep, align 4
314  ret void
315}
316
317; FIXME: Need to handle non-uniform case for function below (load without gep).
318define amdgpu_kernel void @v_test_umax_uge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
319; VI-LABEL: v_test_umax_uge_i16:
320; VI:       ; %bb.0:
321; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
322; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
323; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
324; VI-NEXT:    s_waitcnt lgkmcnt(0)
325; VI-NEXT:    v_mov_b32_e32 v1, s7
326; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
327; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
328; VI-NEXT:    v_mov_b32_e32 v3, s1
329; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
330; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
331; VI-NEXT:    flat_load_ushort v0, v[0:1]
332; VI-NEXT:    flat_load_ushort v1, v[2:3]
333; VI-NEXT:    v_mov_b32_e32 v5, s5
334; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
335; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
336; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
337; VI-NEXT:    v_max_u16_e32 v0, v0, v1
338; VI-NEXT:    flat_store_short v[4:5], v0
339; VI-NEXT:    s_endpgm
340;
341; GFX9-LABEL: v_test_umax_uge_i16:
342; GFX9:       ; %bb.0:
343; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
344; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
345; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
346; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
347; GFX9-NEXT:    v_mov_b32_e32 v1, s7
348; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
349; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
350; GFX9-NEXT:    v_mov_b32_e32 v3, s1
351; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
352; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
353; GFX9-NEXT:    global_load_ushort v0, v[0:1], off
354; GFX9-NEXT:    global_load_ushort v1, v[2:3], off
355; GFX9-NEXT:    v_mov_b32_e32 v5, s5
356; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
357; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
358; GFX9-NEXT:    s_waitcnt vmcnt(0)
359; GFX9-NEXT:    v_max_u16_e32 v0, v0, v1
360; GFX9-NEXT:    global_store_short v[4:5], v0, off
361; GFX9-NEXT:    s_endpgm
362  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
363  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
364  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
365  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
366  %a = load i16, i16 addrspace(1)* %gep0, align 4
367  %b = load i16, i16 addrspace(1)* %gep1, align 4
368  %cmp = icmp uge i16 %a, %b
369  %val = select i1 %cmp, i16 %a, i16 %b
370  store i16 %val, i16 addrspace(1)* %outgep, align 4
371  ret void
372}
373
374; FIXME: Need to handle non-uniform case for function below (load without gep).
375define amdgpu_kernel void @v_test_umax_ugt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
376; VI-LABEL: v_test_umax_ugt_i16:
377; VI:       ; %bb.0:
378; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
379; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
380; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
381; VI-NEXT:    s_waitcnt lgkmcnt(0)
382; VI-NEXT:    v_mov_b32_e32 v1, s7
383; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
384; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
385; VI-NEXT:    v_mov_b32_e32 v3, s1
386; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
387; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
388; VI-NEXT:    flat_load_ushort v0, v[0:1]
389; VI-NEXT:    flat_load_ushort v1, v[2:3]
390; VI-NEXT:    v_mov_b32_e32 v5, s5
391; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
392; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
393; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
394; VI-NEXT:    v_max_u16_e32 v0, v0, v1
395; VI-NEXT:    flat_store_short v[4:5], v0
396; VI-NEXT:    s_endpgm
397;
398; GFX9-LABEL: v_test_umax_ugt_i16:
399; GFX9:       ; %bb.0:
400; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
401; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
402; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
403; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
404; GFX9-NEXT:    v_mov_b32_e32 v1, s7
405; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
406; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
407; GFX9-NEXT:    v_mov_b32_e32 v3, s1
408; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
409; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
410; GFX9-NEXT:    global_load_ushort v0, v[0:1], off
411; GFX9-NEXT:    global_load_ushort v1, v[2:3], off
412; GFX9-NEXT:    v_mov_b32_e32 v5, s5
413; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
414; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
415; GFX9-NEXT:    s_waitcnt vmcnt(0)
416; GFX9-NEXT:    v_max_u16_e32 v0, v0, v1
417; GFX9-NEXT:    global_store_short v[4:5], v0, off
418; GFX9-NEXT:    s_endpgm
419  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
420  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
421  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
422  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
423  %a = load i16, i16 addrspace(1)* %gep0, align 4
424  %b = load i16, i16 addrspace(1)* %gep1, align 4
425  %cmp = icmp ugt i16 %a, %b
426  %val = select i1 %cmp, i16 %a, i16 %b
427  store i16 %val, i16 addrspace(1)* %outgep, align 4
428  ret void
429}
430
431define amdgpu_kernel void @v_test_umax_ugt_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
432; VI-LABEL: v_test_umax_ugt_v2i16:
433; VI:       ; %bb.0:
434; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
435; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
436; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
437; VI-NEXT:    s_waitcnt lgkmcnt(0)
438; VI-NEXT:    v_mov_b32_e32 v1, s7
439; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
440; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
441; VI-NEXT:    v_mov_b32_e32 v3, s1
442; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
443; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
444; VI-NEXT:    flat_load_dword v0, v[0:1]
445; VI-NEXT:    flat_load_dword v1, v[2:3]
446; VI-NEXT:    v_mov_b32_e32 v5, s5
447; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
448; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
449; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
450; VI-NEXT:    v_max_u16_e32 v2, v0, v1
451; VI-NEXT:    v_max_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
452; VI-NEXT:    v_or_b32_e32 v0, v2, v0
453; VI-NEXT:    flat_store_dword v[4:5], v0
454; VI-NEXT:    s_endpgm
455;
456; GFX9-LABEL: v_test_umax_ugt_v2i16:
457; GFX9:       ; %bb.0:
458; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
459; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
460; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
461; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
462; GFX9-NEXT:    v_mov_b32_e32 v1, s7
463; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
464; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
465; GFX9-NEXT:    v_mov_b32_e32 v3, s1
466; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
467; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
468; GFX9-NEXT:    global_load_dword v0, v[0:1], off
469; GFX9-NEXT:    global_load_dword v1, v[2:3], off
470; GFX9-NEXT:    v_mov_b32_e32 v5, s5
471; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
472; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
473; GFX9-NEXT:    s_waitcnt vmcnt(0)
474; GFX9-NEXT:    v_pk_max_u16 v0, v0, v1
475; GFX9-NEXT:    global_store_dword v[4:5], v0, off
476; GFX9-NEXT:    s_endpgm
477  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
478  %gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
479  %gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
480  %outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
481  %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
482  %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
483  %cmp = icmp ugt <2 x i16> %a, %b
484  %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
485  store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
486  ret void
487}
488
489declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
490