1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,VI
3; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,GFX9
4
5; FIXME: Need to handle non-uniform case for function below (load without gep).
6define amdgpu_kernel void @v_test_imax_sge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
7; VI-LABEL: v_test_imax_sge_i16:
8; VI:       ; %bb.0:
9; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
10; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
11; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
12; VI-NEXT:    s_waitcnt lgkmcnt(0)
13; VI-NEXT:    v_mov_b32_e32 v1, s7
14; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
15; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
16; VI-NEXT:    v_mov_b32_e32 v3, s1
17; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
18; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
19; VI-NEXT:    flat_load_ushort v5, v[0:1]
20; VI-NEXT:    flat_load_ushort v2, v[2:3]
21; VI-NEXT:    v_mov_b32_e32 v1, s5
22; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
23; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
24; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
25; VI-NEXT:    v_max_i16_e32 v2, v5, v2
26; VI-NEXT:    flat_store_short v[0:1], v2
27; VI-NEXT:    s_endpgm
28;
29; GFX9-LABEL: v_test_imax_sge_i16:
30; GFX9:       ; %bb.0:
31; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
32; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
33; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
34; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
35; GFX9-NEXT:    v_mov_b32_e32 v1, s7
36; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
37; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
38; GFX9-NEXT:    v_mov_b32_e32 v3, s1
39; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
40; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
41; GFX9-NEXT:    global_load_ushort v5, v[0:1], off
42; GFX9-NEXT:    global_load_ushort v2, v[2:3], off
43; GFX9-NEXT:    v_mov_b32_e32 v1, s5
44; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s4, v4
45; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
46; GFX9-NEXT:    s_waitcnt vmcnt(0)
47; GFX9-NEXT:    v_max_i16_e32 v2, v5, v2
48; GFX9-NEXT:    global_store_short v[0:1], v2, off
49; GFX9-NEXT:    s_endpgm
50  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
51  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
52  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
53  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
54  %a = load i16, i16 addrspace(1)* %gep0, align 4
55  %b = load i16, i16 addrspace(1)* %gep1, align 4
56  %cmp = icmp sge i16 %a, %b
57  %val = select i1 %cmp, i16 %a, i16 %b
58  store i16 %val, i16 addrspace(1)* %outgep, align 4
59  ret void
60}
61
62; FIXME: Need to handle non-uniform case for function below (load without gep).
63define amdgpu_kernel void @v_test_imax_sge_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
64; VI-LABEL: v_test_imax_sge_v2i16:
65; VI:       ; %bb.0:
66; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
67; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
68; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
69; VI-NEXT:    s_waitcnt lgkmcnt(0)
70; VI-NEXT:    v_mov_b32_e32 v1, s7
71; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
72; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
73; VI-NEXT:    v_mov_b32_e32 v3, s1
74; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
75; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
76; VI-NEXT:    flat_load_dword v5, v[0:1]
77; VI-NEXT:    flat_load_dword v2, v[2:3]
78; VI-NEXT:    v_mov_b32_e32 v1, s5
79; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
80; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
81; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
82; VI-NEXT:    v_max_i16_e32 v3, v5, v2
83; VI-NEXT:    v_max_i16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
84; VI-NEXT:    v_or_b32_e32 v2, v3, v2
85; VI-NEXT:    flat_store_dword v[0:1], v2
86; VI-NEXT:    s_endpgm
87;
88; GFX9-LABEL: v_test_imax_sge_v2i16:
89; GFX9:       ; %bb.0:
90; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
91; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
92; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
93; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
94; GFX9-NEXT:    v_mov_b32_e32 v1, s7
95; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
96; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
97; GFX9-NEXT:    v_mov_b32_e32 v3, s1
98; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
99; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
100; GFX9-NEXT:    global_load_dword v5, v[0:1], off
101; GFX9-NEXT:    global_load_dword v2, v[2:3], off
102; GFX9-NEXT:    v_mov_b32_e32 v1, s5
103; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s4, v4
104; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
105; GFX9-NEXT:    s_waitcnt vmcnt(0)
106; GFX9-NEXT:    v_pk_max_i16 v2, v5, v2
107; GFX9-NEXT:    global_store_dword v[0:1], v2, off
108; GFX9-NEXT:    s_endpgm
109  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
110  %gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
111  %gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
112  %outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
113  %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
114  %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
115  %cmp = icmp sge <2 x i16> %a, %b
116  %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
117  store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
118  ret void
119}
120
121; FIXME: Need to handle non-uniform case for function below (load without gep).
122define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %aptr, <3 x i16> addrspace(1)* %bptr) nounwind {
123; VI-LABEL: v_test_imax_sge_v3i16:
124; VI:       ; %bb.0:
125; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
126; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
127; VI-NEXT:    v_lshlrev_b32_e32 v6, 3, v0
128; VI-NEXT:    s_waitcnt lgkmcnt(0)
129; VI-NEXT:    v_mov_b32_e32 v1, s7
130; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v6
131; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
132; VI-NEXT:    v_mov_b32_e32 v3, s1
133; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v6
134; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
135; VI-NEXT:    v_add_u32_e32 v4, vcc, 4, v0
136; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
137; VI-NEXT:    v_mov_b32_e32 v7, s5
138; VI-NEXT:    v_add_u32_e32 v6, vcc, s4, v6
139; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
140; VI-NEXT:    flat_load_ushort v8, v[4:5]
141; VI-NEXT:    flat_load_dword v9, v[0:1]
142; VI-NEXT:    v_add_u32_e32 v0, vcc, 4, v2
143; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
144; VI-NEXT:    flat_load_ushort v0, v[0:1]
145; VI-NEXT:    flat_load_dword v1, v[2:3]
146; VI-NEXT:    v_add_u32_e32 v4, vcc, 4, v6
147; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
148; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
149; VI-NEXT:    v_max_i16_e32 v0, v8, v0
150; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
151; VI-NEXT:    v_max_i16_e32 v2, v9, v1
152; VI-NEXT:    v_max_i16_sdwa v1, v9, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
153; VI-NEXT:    v_or_b32_e32 v1, v2, v1
154; VI-NEXT:    flat_store_short v[4:5], v0
155; VI-NEXT:    flat_store_dword v[6:7], v1
156; VI-NEXT:    s_endpgm
157;
158; GFX9-LABEL: v_test_imax_sge_v3i16:
159; GFX9:       ; %bb.0:
160; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
161; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
162; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
163; GFX9-NEXT:    v_mov_b32_e32 v5, 0
164; GFX9-NEXT:    v_mov_b32_e32 v6, 0
165; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
166; GFX9-NEXT:    v_mov_b32_e32 v1, s7
167; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
168; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
169; GFX9-NEXT:    v_mov_b32_e32 v3, s1
170; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
171; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
172; GFX9-NEXT:    global_load_short_d16 v6, v[0:1], off offset:4
173; GFX9-NEXT:    global_load_dword v7, v[0:1], off
174; GFX9-NEXT:    global_load_short_d16 v5, v[2:3], off offset:4
175; GFX9-NEXT:    global_load_dword v2, v[2:3], off
176; GFX9-NEXT:    v_mov_b32_e32 v1, s5
177; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s4, v4
178; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
179; GFX9-NEXT:    s_waitcnt vmcnt(1)
180; GFX9-NEXT:    v_pk_max_i16 v3, v6, v5
181; GFX9-NEXT:    s_waitcnt vmcnt(0)
182; GFX9-NEXT:    v_pk_max_i16 v2, v7, v2
183; GFX9-NEXT:    global_store_short v[0:1], v3, off offset:4
184; GFX9-NEXT:    global_store_dword v[0:1], v2, off
185; GFX9-NEXT:    s_endpgm
186  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
187  %gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid
188  %gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid
189  %outgep = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %out, i32 %tid
190  %a = load <3 x i16>, <3 x i16> addrspace(1)* %gep0, align 4
191  %b = load <3 x i16>, <3 x i16> addrspace(1)* %gep1, align 4
192  %cmp = icmp sge <3 x i16> %a, %b
193  %val = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
194  store <3 x i16> %val, <3 x i16> addrspace(1)* %outgep, align 4
195  ret void
196}
197
198; FIXME: Need to handle non-uniform case for function below (load without gep).
199define amdgpu_kernel void @v_test_imax_sge_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %aptr, <4 x i16> addrspace(1)* %bptr) nounwind {
200; VI-LABEL: v_test_imax_sge_v4i16:
201; VI:       ; %bb.0:
202; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
203; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
204; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
205; VI-NEXT:    s_waitcnt lgkmcnt(0)
206; VI-NEXT:    v_mov_b32_e32 v1, s7
207; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
208; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
209; VI-NEXT:    v_mov_b32_e32 v3, s1
210; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
211; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
212; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
213; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
214; VI-NEXT:    v_mov_b32_e32 v5, s5
215; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
216; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
217; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
218; VI-NEXT:    v_max_i16_e32 v6, v1, v3
219; VI-NEXT:    v_max_i16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
220; VI-NEXT:    v_max_i16_e32 v3, v0, v2
221; VI-NEXT:    v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
222; VI-NEXT:    v_or_b32_e32 v1, v6, v1
223; VI-NEXT:    v_or_b32_e32 v0, v3, v0
224; VI-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]
225; VI-NEXT:    s_endpgm
226;
227; GFX9-LABEL: v_test_imax_sge_v4i16:
228; GFX9:       ; %bb.0:
229; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
230; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
231; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
232; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
233; GFX9-NEXT:    v_mov_b32_e32 v1, s7
234; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
235; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
236; GFX9-NEXT:    v_mov_b32_e32 v3, s1
237; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
238; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
239; GFX9-NEXT:    global_load_dwordx2 v[0:1], v[0:1], off
240; GFX9-NEXT:    global_load_dwordx2 v[2:3], v[2:3], off
241; GFX9-NEXT:    v_mov_b32_e32 v5, s5
242; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
243; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
244; GFX9-NEXT:    s_waitcnt vmcnt(0)
245; GFX9-NEXT:    v_pk_max_i16 v1, v1, v3
246; GFX9-NEXT:    v_pk_max_i16 v0, v0, v2
247; GFX9-NEXT:    global_store_dwordx2 v[4:5], v[0:1], off
248; GFX9-NEXT:    s_endpgm
249  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
250  %gep0 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %aptr, i32 %tid
251  %gep1 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %bptr, i32 %tid
252  %outgep = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %out, i32 %tid
253  %a = load <4 x i16>, <4 x i16> addrspace(1)* %gep0, align 4
254  %b = load <4 x i16>, <4 x i16> addrspace(1)* %gep1, align 4
255  %cmp = icmp sge <4 x i16> %a, %b
256  %val = select <4 x i1> %cmp, <4 x i16> %a, <4 x i16> %b
257  store <4 x i16> %val, <4 x i16> addrspace(1)* %outgep, align 4
258  ret void
259}
260
261; FIXME: Need to handle non-uniform case for function below (load without gep).
262define amdgpu_kernel void @v_test_imax_sgt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
263; VI-LABEL: v_test_imax_sgt_i16:
264; VI:       ; %bb.0:
265; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
266; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
267; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
268; VI-NEXT:    s_waitcnt lgkmcnt(0)
269; VI-NEXT:    v_mov_b32_e32 v1, s7
270; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
271; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
272; VI-NEXT:    v_mov_b32_e32 v3, s1
273; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
274; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
275; VI-NEXT:    flat_load_ushort v5, v[0:1]
276; VI-NEXT:    flat_load_ushort v2, v[2:3]
277; VI-NEXT:    v_mov_b32_e32 v1, s5
278; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
279; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
280; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
281; VI-NEXT:    v_max_i16_e32 v2, v5, v2
282; VI-NEXT:    flat_store_short v[0:1], v2
283; VI-NEXT:    s_endpgm
284;
285; GFX9-LABEL: v_test_imax_sgt_i16:
286; GFX9:       ; %bb.0:
287; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
288; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
289; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
290; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
291; GFX9-NEXT:    v_mov_b32_e32 v1, s7
292; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
293; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
294; GFX9-NEXT:    v_mov_b32_e32 v3, s1
295; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
296; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
297; GFX9-NEXT:    global_load_ushort v5, v[0:1], off
298; GFX9-NEXT:    global_load_ushort v2, v[2:3], off
299; GFX9-NEXT:    v_mov_b32_e32 v1, s5
300; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s4, v4
301; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
302; GFX9-NEXT:    s_waitcnt vmcnt(0)
303; GFX9-NEXT:    v_max_i16_e32 v2, v5, v2
304; GFX9-NEXT:    global_store_short v[0:1], v2, off
305; GFX9-NEXT:    s_endpgm
306  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
307  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
308  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
309  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
310  %a = load i16, i16 addrspace(1)* %gep0, align 4
311  %b = load i16, i16 addrspace(1)* %gep1, align 4
312  %cmp = icmp sgt i16 %a, %b
313  %val = select i1 %cmp, i16 %a, i16 %b
314  store i16 %val, i16 addrspace(1)* %outgep, align 4
315  ret void
316}
317
318; FIXME: Need to handle non-uniform case for function below (load without gep).
319define amdgpu_kernel void @v_test_umax_uge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
320; VI-LABEL: v_test_umax_uge_i16:
321; VI:       ; %bb.0:
322; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
323; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
324; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
325; VI-NEXT:    s_waitcnt lgkmcnt(0)
326; VI-NEXT:    v_mov_b32_e32 v1, s7
327; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
328; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
329; VI-NEXT:    v_mov_b32_e32 v3, s1
330; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
331; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
332; VI-NEXT:    flat_load_ushort v5, v[0:1]
333; VI-NEXT:    flat_load_ushort v2, v[2:3]
334; VI-NEXT:    v_mov_b32_e32 v1, s5
335; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
336; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
337; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
338; VI-NEXT:    v_max_u16_e32 v2, v5, v2
339; VI-NEXT:    flat_store_short v[0:1], v2
340; VI-NEXT:    s_endpgm
341;
342; GFX9-LABEL: v_test_umax_uge_i16:
343; GFX9:       ; %bb.0:
344; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
345; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
346; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
347; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
348; GFX9-NEXT:    v_mov_b32_e32 v1, s7
349; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
350; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
351; GFX9-NEXT:    v_mov_b32_e32 v3, s1
352; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
353; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
354; GFX9-NEXT:    global_load_ushort v5, v[0:1], off
355; GFX9-NEXT:    global_load_ushort v2, v[2:3], off
356; GFX9-NEXT:    v_mov_b32_e32 v1, s5
357; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s4, v4
358; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
359; GFX9-NEXT:    s_waitcnt vmcnt(0)
360; GFX9-NEXT:    v_max_u16_e32 v2, v5, v2
361; GFX9-NEXT:    global_store_short v[0:1], v2, off
362; GFX9-NEXT:    s_endpgm
363  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
364  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
365  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
366  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
367  %a = load i16, i16 addrspace(1)* %gep0, align 4
368  %b = load i16, i16 addrspace(1)* %gep1, align 4
369  %cmp = icmp uge i16 %a, %b
370  %val = select i1 %cmp, i16 %a, i16 %b
371  store i16 %val, i16 addrspace(1)* %outgep, align 4
372  ret void
373}
374
375; FIXME: Need to handle non-uniform case for function below (load without gep).
376define amdgpu_kernel void @v_test_umax_ugt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
377; VI-LABEL: v_test_umax_ugt_i16:
378; VI:       ; %bb.0:
379; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
380; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
381; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
382; VI-NEXT:    s_waitcnt lgkmcnt(0)
383; VI-NEXT:    v_mov_b32_e32 v1, s7
384; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
385; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
386; VI-NEXT:    v_mov_b32_e32 v3, s1
387; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
388; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
389; VI-NEXT:    flat_load_ushort v5, v[0:1]
390; VI-NEXT:    flat_load_ushort v2, v[2:3]
391; VI-NEXT:    v_mov_b32_e32 v1, s5
392; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
393; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
394; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
395; VI-NEXT:    v_max_u16_e32 v2, v5, v2
396; VI-NEXT:    flat_store_short v[0:1], v2
397; VI-NEXT:    s_endpgm
398;
399; GFX9-LABEL: v_test_umax_ugt_i16:
400; GFX9:       ; %bb.0:
401; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
402; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
403; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
404; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
405; GFX9-NEXT:    v_mov_b32_e32 v1, s7
406; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
407; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
408; GFX9-NEXT:    v_mov_b32_e32 v3, s1
409; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
410; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
411; GFX9-NEXT:    global_load_ushort v5, v[0:1], off
412; GFX9-NEXT:    global_load_ushort v2, v[2:3], off
413; GFX9-NEXT:    v_mov_b32_e32 v1, s5
414; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s4, v4
415; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
416; GFX9-NEXT:    s_waitcnt vmcnt(0)
417; GFX9-NEXT:    v_max_u16_e32 v2, v5, v2
418; GFX9-NEXT:    global_store_short v[0:1], v2, off
419; GFX9-NEXT:    s_endpgm
420  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
421  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
422  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
423  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
424  %a = load i16, i16 addrspace(1)* %gep0, align 4
425  %b = load i16, i16 addrspace(1)* %gep1, align 4
426  %cmp = icmp ugt i16 %a, %b
427  %val = select i1 %cmp, i16 %a, i16 %b
428  store i16 %val, i16 addrspace(1)* %outgep, align 4
429  ret void
430}
431
432define amdgpu_kernel void @v_test_umax_ugt_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
433; VI-LABEL: v_test_umax_ugt_v2i16:
434; VI:       ; %bb.0:
435; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
436; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
437; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
438; VI-NEXT:    s_waitcnt lgkmcnt(0)
439; VI-NEXT:    v_mov_b32_e32 v1, s7
440; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
441; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
442; VI-NEXT:    v_mov_b32_e32 v3, s1
443; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
444; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
445; VI-NEXT:    flat_load_dword v5, v[0:1]
446; VI-NEXT:    flat_load_dword v2, v[2:3]
447; VI-NEXT:    v_mov_b32_e32 v1, s5
448; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
449; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
450; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
451; VI-NEXT:    v_max_u16_e32 v3, v5, v2
452; VI-NEXT:    v_max_u16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
453; VI-NEXT:    v_or_b32_e32 v2, v3, v2
454; VI-NEXT:    flat_store_dword v[0:1], v2
455; VI-NEXT:    s_endpgm
456;
457; GFX9-LABEL: v_test_umax_ugt_v2i16:
458; GFX9:       ; %bb.0:
459; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
460; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
461; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
462; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
463; GFX9-NEXT:    v_mov_b32_e32 v1, s7
464; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s6, v4
465; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
466; GFX9-NEXT:    v_mov_b32_e32 v3, s1
467; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, s0, v4
468; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
469; GFX9-NEXT:    global_load_dword v5, v[0:1], off
470; GFX9-NEXT:    global_load_dword v2, v[2:3], off
471; GFX9-NEXT:    v_mov_b32_e32 v1, s5
472; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s4, v4
473; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
474; GFX9-NEXT:    s_waitcnt vmcnt(0)
475; GFX9-NEXT:    v_pk_max_u16 v2, v5, v2
476; GFX9-NEXT:    global_store_dword v[0:1], v2, off
477; GFX9-NEXT:    s_endpgm
478  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
479  %gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
480  %gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
481  %outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
482  %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
483  %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
484  %cmp = icmp ugt <2 x i16> %a, %b
485  %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
486  store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
487  ret void
488}
489
490declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
491