1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,VI
3; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VIPLUS,GFX9
4
5; FIXME: Need to handle non-uniform case for function below (load without gep).
6define amdgpu_kernel void @v_test_imax_sge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
7; VI-LABEL: v_test_imax_sge_i16:
8; VI:       ; %bb.0:
9; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
10; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
11; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
12; VI-NEXT:    s_waitcnt lgkmcnt(0)
13; VI-NEXT:    v_mov_b32_e32 v1, s7
14; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
15; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
16; VI-NEXT:    v_mov_b32_e32 v3, s1
17; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
18; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
19; VI-NEXT:    flat_load_ushort v0, v[0:1]
20; VI-NEXT:    flat_load_ushort v1, v[2:3]
21; VI-NEXT:    v_mov_b32_e32 v5, s5
22; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
23; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
24; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
25; VI-NEXT:    v_max_i16_e32 v0, v0, v1
26; VI-NEXT:    flat_store_short v[4:5], v0
27; VI-NEXT:    s_endpgm
28;
29; GFX9-LABEL: v_test_imax_sge_i16:
30; GFX9:       ; %bb.0:
31; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
32; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
33; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
34; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
35; GFX9-NEXT:    global_load_ushort v1, v0, s[6:7]
36; GFX9-NEXT:    global_load_ushort v2, v0, s[0:1]
37; GFX9-NEXT:    s_waitcnt vmcnt(0)
38; GFX9-NEXT:    v_max_i16_e32 v1, v1, v2
39; GFX9-NEXT:    global_store_short v0, v1, s[4:5]
40; GFX9-NEXT:    s_endpgm
41  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
42  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
43  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
44  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
45  %a = load i16, i16 addrspace(1)* %gep0, align 4
46  %b = load i16, i16 addrspace(1)* %gep1, align 4
47  %cmp = icmp sge i16 %a, %b
48  %val = select i1 %cmp, i16 %a, i16 %b
49  store i16 %val, i16 addrspace(1)* %outgep, align 4
50  ret void
51}
52
53; FIXME: Need to handle non-uniform case for function below (load without gep).
54define amdgpu_kernel void @v_test_imax_sge_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
55; VI-LABEL: v_test_imax_sge_v2i16:
56; VI:       ; %bb.0:
57; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
58; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
59; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
60; VI-NEXT:    s_waitcnt lgkmcnt(0)
61; VI-NEXT:    v_mov_b32_e32 v1, s7
62; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
63; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
64; VI-NEXT:    v_mov_b32_e32 v3, s1
65; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
66; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
67; VI-NEXT:    flat_load_dword v5, v[0:1]
68; VI-NEXT:    flat_load_dword v2, v[2:3]
69; VI-NEXT:    v_mov_b32_e32 v1, s5
70; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
71; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
72; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
73; VI-NEXT:    v_max_i16_e32 v3, v5, v2
74; VI-NEXT:    v_max_i16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
75; VI-NEXT:    v_or_b32_e32 v2, v3, v2
76; VI-NEXT:    flat_store_dword v[0:1], v2
77; VI-NEXT:    s_endpgm
78;
79; GFX9-LABEL: v_test_imax_sge_v2i16:
80; GFX9:       ; %bb.0:
81; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
82; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
83; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
84; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
85; GFX9-NEXT:    global_load_dword v1, v0, s[6:7]
86; GFX9-NEXT:    global_load_dword v2, v0, s[0:1]
87; GFX9-NEXT:    s_waitcnt vmcnt(0)
88; GFX9-NEXT:    v_pk_max_i16 v1, v1, v2
89; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
90; GFX9-NEXT:    s_endpgm
91  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
92  %gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
93  %gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
94  %outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
95  %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
96  %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
97  %cmp = icmp sge <2 x i16> %a, %b
98  %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
99  store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
100  ret void
101}
102
103; FIXME: Need to handle non-uniform case for function below (load without gep).
104define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %aptr, <3 x i16> addrspace(1)* %bptr) nounwind {
105; VI-LABEL: v_test_imax_sge_v3i16:
106; VI:       ; %bb.0:
107; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
108; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
109; VI-NEXT:    v_lshlrev_b32_e32 v6, 3, v0
110; VI-NEXT:    s_waitcnt lgkmcnt(0)
111; VI-NEXT:    v_mov_b32_e32 v1, s7
112; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v6
113; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
114; VI-NEXT:    v_mov_b32_e32 v3, s1
115; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v6
116; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
117; VI-NEXT:    v_add_u32_e32 v4, vcc, 4, v0
118; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
119; VI-NEXT:    flat_load_ushort v4, v[4:5]
120; VI-NEXT:    flat_load_dword v5, v[0:1]
121; VI-NEXT:    v_add_u32_e32 v0, vcc, 4, v2
122; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
123; VI-NEXT:    flat_load_dword v7, v[2:3]
124; VI-NEXT:    flat_load_ushort v8, v[0:1]
125; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v6
126; VI-NEXT:    v_mov_b32_e32 v1, s5
127; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
128; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
129; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
130; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
131; VI-NEXT:    v_max_i16_e32 v6, v5, v7
132; VI-NEXT:    v_max_i16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
133; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
134; VI-NEXT:    v_max_i16_e32 v4, v4, v8
135; VI-NEXT:    v_or_b32_e32 v5, v6, v5
136; VI-NEXT:    flat_store_short v[2:3], v4
137; VI-NEXT:    flat_store_dword v[0:1], v5
138; VI-NEXT:    s_endpgm
139;
140; GFX9-LABEL: v_test_imax_sge_v3i16:
141; GFX9:       ; %bb.0:
142; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
143; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
144; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
145; GFX9-NEXT:    v_mov_b32_e32 v1, 0
146; GFX9-NEXT:    v_mov_b32_e32 v2, 0
147; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
148; GFX9-NEXT:    global_load_short_d16 v1, v0, s[0:1] offset:4
149; GFX9-NEXT:    global_load_dword v3, v0, s[0:1]
150; GFX9-NEXT:    global_load_short_d16 v2, v0, s[6:7] offset:4
151; GFX9-NEXT:    global_load_dword v4, v0, s[6:7]
152; GFX9-NEXT:    s_waitcnt vmcnt(1)
153; GFX9-NEXT:    v_pk_max_i16 v1, v2, v1
154; GFX9-NEXT:    s_waitcnt vmcnt(0)
155; GFX9-NEXT:    v_pk_max_i16 v3, v4, v3
156; GFX9-NEXT:    global_store_short v0, v1, s[4:5] offset:4
157; GFX9-NEXT:    global_store_dword v0, v3, s[4:5]
158; GFX9-NEXT:    s_endpgm
159  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
160  %gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid
161  %gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid
162  %outgep = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %out, i32 %tid
163  %a = load <3 x i16>, <3 x i16> addrspace(1)* %gep0, align 4
164  %b = load <3 x i16>, <3 x i16> addrspace(1)* %gep1, align 4
165  %cmp = icmp sge <3 x i16> %a, %b
166  %val = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b
167  store <3 x i16> %val, <3 x i16> addrspace(1)* %outgep, align 4
168  ret void
169}
170
171; FIXME: Need to handle non-uniform case for function below (load without gep).
172define amdgpu_kernel void @v_test_imax_sge_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %aptr, <4 x i16> addrspace(1)* %bptr) nounwind {
173; VI-LABEL: v_test_imax_sge_v4i16:
174; VI:       ; %bb.0:
175; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
176; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
177; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
178; VI-NEXT:    s_waitcnt lgkmcnt(0)
179; VI-NEXT:    v_mov_b32_e32 v1, s7
180; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
181; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
182; VI-NEXT:    v_mov_b32_e32 v3, s1
183; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
184; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
185; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
186; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
187; VI-NEXT:    v_mov_b32_e32 v5, s5
188; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
189; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
190; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
191; VI-NEXT:    v_max_i16_e32 v6, v1, v3
192; VI-NEXT:    v_max_i16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
193; VI-NEXT:    v_max_i16_e32 v3, v0, v2
194; VI-NEXT:    v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
195; VI-NEXT:    v_or_b32_e32 v1, v6, v1
196; VI-NEXT:    v_or_b32_e32 v0, v3, v0
197; VI-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]
198; VI-NEXT:    s_endpgm
199;
200; GFX9-LABEL: v_test_imax_sge_v4i16:
201; GFX9:       ; %bb.0:
202; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
203; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
204; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
205; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
206; GFX9-NEXT:    global_load_dwordx2 v[0:1], v4, s[6:7]
207; GFX9-NEXT:    global_load_dwordx2 v[2:3], v4, s[0:1]
208; GFX9-NEXT:    s_waitcnt vmcnt(0)
209; GFX9-NEXT:    v_pk_max_i16 v1, v1, v3
210; GFX9-NEXT:    v_pk_max_i16 v0, v0, v2
211; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[4:5]
212; GFX9-NEXT:    s_endpgm
213  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
214  %gep0 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %aptr, i32 %tid
215  %gep1 = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %bptr, i32 %tid
216  %outgep = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %out, i32 %tid
217  %a = load <4 x i16>, <4 x i16> addrspace(1)* %gep0, align 4
218  %b = load <4 x i16>, <4 x i16> addrspace(1)* %gep1, align 4
219  %cmp = icmp sge <4 x i16> %a, %b
220  %val = select <4 x i1> %cmp, <4 x i16> %a, <4 x i16> %b
221  store <4 x i16> %val, <4 x i16> addrspace(1)* %outgep, align 4
222  ret void
223}
224
225; FIXME: Need to handle non-uniform case for function below (load without gep).
226define amdgpu_kernel void @v_test_imax_sgt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
227; VI-LABEL: v_test_imax_sgt_i16:
228; VI:       ; %bb.0:
229; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
230; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
231; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
232; VI-NEXT:    s_waitcnt lgkmcnt(0)
233; VI-NEXT:    v_mov_b32_e32 v1, s7
234; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
235; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
236; VI-NEXT:    v_mov_b32_e32 v3, s1
237; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
238; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
239; VI-NEXT:    flat_load_ushort v0, v[0:1]
240; VI-NEXT:    flat_load_ushort v1, v[2:3]
241; VI-NEXT:    v_mov_b32_e32 v5, s5
242; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
243; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
244; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
245; VI-NEXT:    v_max_i16_e32 v0, v0, v1
246; VI-NEXT:    flat_store_short v[4:5], v0
247; VI-NEXT:    s_endpgm
248;
249; GFX9-LABEL: v_test_imax_sgt_i16:
250; GFX9:       ; %bb.0:
251; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
252; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
253; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
254; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
255; GFX9-NEXT:    global_load_ushort v1, v0, s[6:7]
256; GFX9-NEXT:    global_load_ushort v2, v0, s[0:1]
257; GFX9-NEXT:    s_waitcnt vmcnt(0)
258; GFX9-NEXT:    v_max_i16_e32 v1, v1, v2
259; GFX9-NEXT:    global_store_short v0, v1, s[4:5]
260; GFX9-NEXT:    s_endpgm
261  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
262  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
263  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
264  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
265  %a = load i16, i16 addrspace(1)* %gep0, align 4
266  %b = load i16, i16 addrspace(1)* %gep1, align 4
267  %cmp = icmp sgt i16 %a, %b
268  %val = select i1 %cmp, i16 %a, i16 %b
269  store i16 %val, i16 addrspace(1)* %outgep, align 4
270  ret void
271}
272
273; FIXME: Need to handle non-uniform case for function below (load without gep).
274define amdgpu_kernel void @v_test_umax_uge_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
275; VI-LABEL: v_test_umax_uge_i16:
276; VI:       ; %bb.0:
277; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
278; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
279; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
280; VI-NEXT:    s_waitcnt lgkmcnt(0)
281; VI-NEXT:    v_mov_b32_e32 v1, s7
282; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
283; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
284; VI-NEXT:    v_mov_b32_e32 v3, s1
285; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
286; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
287; VI-NEXT:    flat_load_ushort v0, v[0:1]
288; VI-NEXT:    flat_load_ushort v1, v[2:3]
289; VI-NEXT:    v_mov_b32_e32 v5, s5
290; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
291; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
292; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
293; VI-NEXT:    v_max_u16_e32 v0, v0, v1
294; VI-NEXT:    flat_store_short v[4:5], v0
295; VI-NEXT:    s_endpgm
296;
297; GFX9-LABEL: v_test_umax_uge_i16:
298; GFX9:       ; %bb.0:
299; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
300; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
301; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
302; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
303; GFX9-NEXT:    global_load_ushort v1, v0, s[6:7]
304; GFX9-NEXT:    global_load_ushort v2, v0, s[0:1]
305; GFX9-NEXT:    s_waitcnt vmcnt(0)
306; GFX9-NEXT:    v_max_u16_e32 v1, v1, v2
307; GFX9-NEXT:    global_store_short v0, v1, s[4:5]
308; GFX9-NEXT:    s_endpgm
309  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
310  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
311  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
312  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
313  %a = load i16, i16 addrspace(1)* %gep0, align 4
314  %b = load i16, i16 addrspace(1)* %gep1, align 4
315  %cmp = icmp uge i16 %a, %b
316  %val = select i1 %cmp, i16 %a, i16 %b
317  store i16 %val, i16 addrspace(1)* %outgep, align 4
318  ret void
319}
320
321; FIXME: Need to handle non-uniform case for function below (load without gep).
322define amdgpu_kernel void @v_test_umax_ugt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) nounwind {
323; VI-LABEL: v_test_umax_ugt_i16:
324; VI:       ; %bb.0:
325; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
326; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
327; VI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
328; VI-NEXT:    s_waitcnt lgkmcnt(0)
329; VI-NEXT:    v_mov_b32_e32 v1, s7
330; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
331; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
332; VI-NEXT:    v_mov_b32_e32 v3, s1
333; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
334; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
335; VI-NEXT:    flat_load_ushort v0, v[0:1]
336; VI-NEXT:    flat_load_ushort v1, v[2:3]
337; VI-NEXT:    v_mov_b32_e32 v5, s5
338; VI-NEXT:    v_add_u32_e32 v4, vcc, s4, v4
339; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
340; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
341; VI-NEXT:    v_max_u16_e32 v0, v0, v1
342; VI-NEXT:    flat_store_short v[4:5], v0
343; VI-NEXT:    s_endpgm
344;
345; GFX9-LABEL: v_test_umax_ugt_i16:
346; GFX9:       ; %bb.0:
347; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
348; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
349; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
350; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
351; GFX9-NEXT:    global_load_ushort v1, v0, s[6:7]
352; GFX9-NEXT:    global_load_ushort v2, v0, s[0:1]
353; GFX9-NEXT:    s_waitcnt vmcnt(0)
354; GFX9-NEXT:    v_max_u16_e32 v1, v1, v2
355; GFX9-NEXT:    global_store_short v0, v1, s[4:5]
356; GFX9-NEXT:    s_endpgm
357  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
358  %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
359  %gep1 = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
360  %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
361  %a = load i16, i16 addrspace(1)* %gep0, align 4
362  %b = load i16, i16 addrspace(1)* %gep1, align 4
363  %cmp = icmp ugt i16 %a, %b
364  %val = select i1 %cmp, i16 %a, i16 %b
365  store i16 %val, i16 addrspace(1)* %outgep, align 4
366  ret void
367}
368
369define amdgpu_kernel void @v_test_umax_ugt_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %aptr, <2 x i16> addrspace(1)* %bptr) nounwind {
370; VI-LABEL: v_test_umax_ugt_v2i16:
371; VI:       ; %bb.0:
372; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
373; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
374; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
375; VI-NEXT:    s_waitcnt lgkmcnt(0)
376; VI-NEXT:    v_mov_b32_e32 v1, s7
377; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v4
378; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
379; VI-NEXT:    v_mov_b32_e32 v3, s1
380; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v4
381; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
382; VI-NEXT:    flat_load_dword v5, v[0:1]
383; VI-NEXT:    flat_load_dword v2, v[2:3]
384; VI-NEXT:    v_mov_b32_e32 v1, s5
385; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v4
386; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
387; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
388; VI-NEXT:    v_max_u16_e32 v3, v5, v2
389; VI-NEXT:    v_max_u16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
390; VI-NEXT:    v_or_b32_e32 v2, v3, v2
391; VI-NEXT:    flat_store_dword v[0:1], v2
392; VI-NEXT:    s_endpgm
393;
394; GFX9-LABEL: v_test_umax_ugt_v2i16:
395; GFX9:       ; %bb.0:
396; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
397; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
398; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
399; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
400; GFX9-NEXT:    global_load_dword v1, v0, s[6:7]
401; GFX9-NEXT:    global_load_dword v2, v0, s[0:1]
402; GFX9-NEXT:    s_waitcnt vmcnt(0)
403; GFX9-NEXT:    v_pk_max_u16 v1, v1, v2
404; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
405; GFX9-NEXT:    s_endpgm
406  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
407  %gep0 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %aptr, i32 %tid
408  %gep1 = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %bptr, i32 %tid
409  %outgep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
410  %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep0, align 4
411  %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep1, align 4
412  %cmp = icmp ugt <2 x i16> %a, %b
413  %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
414  store <2 x i16> %val, <2 x i16> addrspace(1)* %outgep, align 4
415  ret void
416}
417
418declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
419