1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
2; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
3; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN1
4; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2
5; RUN: llc < %s -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2
6
7declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
8
9; FUNC-LABEL: {{^}}u32_mad24:
10; EG: MULADD_UINT24
11; SI: v_mad_u32_u24
12; VI: v_mad_u32_u24
13
14define amdgpu_kernel void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
15entry:
16  %0 = shl i32 %a, 8
17  %a_24 = lshr i32 %0, 8
18  %1 = shl i32 %b, 8
19  %b_24 = lshr i32 %1, 8
20  %2 = mul i32 %a_24, %b_24
21  %3 = add i32 %2, %c
22  store i32 %3, i32 addrspace(1)* %out
23  ret void
24}
25
26; FUNC-LABEL: {{^}}i16_mad24:
27; The order of A and B does not matter.
28; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
29; The result must be sign-extended
30; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
31; EG: 16
32; FIXME: Should be using scalar instructions here.
33; GCN1: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
34; GCN1: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16
35; GCN2:	s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}}
36; GCN2:	s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}}
37; GCN2:	s_sext_i32_i16 s0, [[MAD]]
38; GCN2:	v_mov_b32_e32 v0, s0
39define amdgpu_kernel void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
40entry:
41  %0 = mul i16 %a, %b
42  %1 = add i16 %0, %c
43  %2 = sext i16 %1 to i32
44  store i32 %2, i32 addrspace(1)* %out
45  ret void
46}
47
48; FIXME: Need to handle non-uniform case for function below (load without gep).
49; FUNC-LABEL: {{^}}i8_mad24:
50; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
51; The result must be sign-extended
52; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
53; EG: 8
54; GCN1: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
55; GCN1: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
56; GCN2:	s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}}
57; GCN2:	s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}}
58; GCN2:	s_sext_i32_i8 s0, [[MAD]]
59; GCN2:	v_mov_b32_e32 v0, s0
60define amdgpu_kernel void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
61entry:
62  %0 = mul i8 %a, %b
63  %1 = add i8 %0, %c
64  %2 = sext i8 %1 to i32
65  store i32 %2, i32 addrspace(1)* %out
66  ret void
67}
68
69; This tests for a bug where the mad_u24 pattern matcher would call
70; SimplifyDemandedBits on the first operand of the mul instruction
71; assuming that the pattern would be matched to a 24-bit mad.  This
72; led to some instructions being incorrectly erased when the entire
73; 24-bit mad pattern wasn't being matched.
74
75; Check that the select instruction is not deleted.
76; FUNC-LABEL: {{^}}i24_i32_i32_mad:
77; EG: CNDE_INT
78; SI: s_cselect
79define amdgpu_kernel void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
80entry:
81  %0 = ashr i32 %a, 8
82  %1 = icmp ne i32 %c, 0
83  %2 = select i1 %1, i32 %0, i32 34
84  %3 = mul i32 %2, %c
85  %4 = add i32 %3, %d
86  store i32 %4, i32 addrspace(1)* %out
87  ret void
88}
89
90; FUNC-LABEL: {{^}}extra_and:
91; SI-NOT: v_and
92; SI: v_mad_u32_u24
93; SI: v_mad_u32_u24
94define amdgpu_kernel void @extra_and(i32 addrspace(1)* %arg, i32 %arg2, i32 %arg3) {
95bb:
96  br label %bb4
97
98bb4:                                              ; preds = %bb4, %bb
99  %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
100  %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
101  %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
102  %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
103  %tmp8 = and i32 %tmp7, 16777215
104  %tmp9 = and i32 %tmp6, 16777215
105  %tmp10 = and i32 %tmp5, 16777215
106  %tmp11 = and i32 %tmp, 16777215
107  %tmp12 = mul i32 %tmp8, %tmp11
108  %tmp13 = add i32 %arg2, %tmp12
109  %tmp14 = mul i32 %tmp9, %tmp11
110  %tmp15 = add i32 %arg3, %tmp14
111  %tmp16 = add nuw nsw i32 %tmp13, %tmp15
112  %tmp17 = icmp eq i32 %tmp16, 8
113  br i1 %tmp17, label %bb18, label %bb4
114
115bb18:                                             ; preds = %bb4
116  store i32 %tmp16, i32 addrspace(1)* %arg
117  ret void
118}
119
120; FUNC-LABEL: {{^}}dont_remove_shift
121; SI: v_lshr
122; SI: v_mad_u32_u24
123; SI: v_mad_u32_u24
124define amdgpu_kernel void @dont_remove_shift(i32 addrspace(1)* %arg, i32 %arg2, i32 %arg3) {
125bb:
126  br label %bb4
127
128bb4:                                              ; preds = %bb4, %bb
129  %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
130  %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
131  %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
132  %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
133  %tmp8 = lshr i32 %tmp7, 8
134  %tmp9 = lshr i32 %tmp6, 8
135  %tmp10 = lshr i32 %tmp5, 8
136  %tmp11 = lshr i32 %tmp, 8
137  %tmp12 = mul i32 %tmp8, %tmp11
138  %tmp13 = add i32 %arg2, %tmp12
139  %tmp14 = mul i32 %tmp9, %tmp11
140  %tmp15 = add i32 %arg3, %tmp14
141  %tmp16 = add nuw nsw i32 %tmp13, %tmp15
142  %tmp17 = icmp eq i32 %tmp16, 8
143  br i1 %tmp17, label %bb18, label %bb4
144
145bb18:                                             ; preds = %bb4
146  store i32 %tmp16, i32 addrspace(1)* %arg
147  ret void
148}
149
150; FUNC-LABEL: {{^}}i8_mad_sat_16:
151; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
152; The result must be sign-extended
153; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
154; EG: 8
155; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
156; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
157; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
158; GCN: v_med3_i32 v{{[0-9]}}, [[EXT]],
159define amdgpu_kernel void @i8_mad_sat_16(i8 addrspace(1)* %out, i8 addrspace(1)* %in0, i8 addrspace(1)* %in1, i8 addrspace(1)* %in2, i64 addrspace(5)* %idx) {
160entry:
161  %retval.0.i = load i64, i64 addrspace(5)* %idx
162  %arrayidx = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 %retval.0.i
163  %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 %retval.0.i
164  %arrayidx4 = getelementptr inbounds i8, i8 addrspace(1)* %in2, i64 %retval.0.i
165  %l1 = load i8, i8 addrspace(1)* %arrayidx, align 1
166  %l2 = load i8, i8 addrspace(1)* %arrayidx2, align 1
167  %l3 = load i8, i8 addrspace(1)* %arrayidx4, align 1
168  %conv1.i = sext i8 %l1 to i16
169  %conv3.i = sext i8 %l2 to i16
170  %conv5.i = sext i8 %l3 to i16
171  %mul.i.i.i = mul nsw i16 %conv3.i, %conv1.i
172  %add.i.i = add i16 %mul.i.i.i, %conv5.i
173  %c4 = icmp sgt i16 %add.i.i, -128
174  %cond.i.i = select i1 %c4, i16 %add.i.i, i16 -128
175  %c5 = icmp slt i16 %cond.i.i, 127
176  %cond13.i.i = select i1 %c5, i16 %cond.i.i, i16 127
177  %conv8.i = trunc i16 %cond13.i.i to i8
178  %arrayidx7 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 %retval.0.i
179  store i8 %conv8.i, i8 addrspace(1)* %arrayidx7, align 1
180  ret void
181}
182
183; FUNC-LABEL: {{^}}i8_mad_32:
184; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
185; The result must be sign-extended
186; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
187; EG: 8
188; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
189; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
190; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
191define amdgpu_kernel void @i8_mad_32(i32 addrspace(1)* %out, i8 addrspace(1)* %a, i8 addrspace(1)* %b, i8 addrspace(1)* %c, i64 addrspace(5)* %idx) {
192entry:
193  %retval.0.i = load i64, i64 addrspace(5)* %idx
194  %arrayidx = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 %retval.0.i
195  %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %b, i64 %retval.0.i
196  %arrayidx4 = getelementptr inbounds i8, i8 addrspace(1)* %c, i64 %retval.0.i
197  %la = load i8, i8 addrspace(1)* %arrayidx, align 1
198  %lb = load i8, i8 addrspace(1)* %arrayidx2, align 1
199  %lc = load i8, i8 addrspace(1)* %arrayidx4, align 1
200  %exta = sext i8 %la to i16
201  %extb = sext i8 %lb to i16
202  %extc = sext i8 %lc to i16
203  %mul = mul i16 %exta, %extb
204  %mad = add i16 %mul, %extc
205  %mad_ext = sext i16 %mad to i32
206  store i32 %mad_ext, i32 addrspace(1)* %out
207  ret void
208}
209
210; FUNC-LABEL: {{^}}i8_mad_64:
211; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
212; The result must be sign-extended
213; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
214; EG: 8
215; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
216; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
217; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
218define amdgpu_kernel void @i8_mad_64(i64 addrspace(1)* %out, i8 addrspace(1)* %a, i8 addrspace(1)* %b, i8 addrspace(1)* %c, i64 addrspace(5)* %idx) {
219entry:
220  %retval.0.i = load i64, i64 addrspace(5)* %idx
221  %arrayidx = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 %retval.0.i
222  %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %b, i64 %retval.0.i
223  %arrayidx4 = getelementptr inbounds i8, i8 addrspace(1)* %c, i64 %retval.0.i
224  %la = load i8, i8 addrspace(1)* %arrayidx, align 1
225  %lb = load i8, i8 addrspace(1)* %arrayidx2, align 1
226  %lc = load i8, i8 addrspace(1)* %arrayidx4, align 1
227  %exta = sext i8 %la to i16
228  %extb = sext i8 %lb to i16
229  %extc = sext i8 %lc to i16
230  %mul = mul i16 %exta, %extb
231  %mad = add i16 %mul, %extc
232  %mad_ext = sext i16 %mad to i64
233  store i64 %mad_ext, i64 addrspace(1)* %out
234  ret void
235}
236
237; The ands are asserting the high bits are 0. SimplifyDemandedBits on
238; the adds would remove the ands before the target combine on the mul
239; had a chance to form mul24. The mul combine would then see
240; extractelement with no known bits and fail. All of the mul/add
241; combos in this loop should form v_mad_u32_u24.
242
243; FUNC-LABEL: {{^}}mad24_known_bits_destroyed:
244; GCN: v_mad_u32_u24
245; GCN: v_mad_u32_u24
246; GCN: v_mad_u32_u24
247; GCN: v_mad_u32_u24
248; GCN: v_mad_u32_u24
249; GCN: v_mad_u32_u24
250; GCN: v_mad_u32_u24
251; GCN: v_mad_u32_u24
252define void @mad24_known_bits_destroyed(i32 %arg, <4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 addrspace(1)* %arg7, <4 x i32> addrspace(1)* %arg8) #0 {
253bb:
254  %tmp = and i32 %arg4, 16777215
255  %tmp9 = extractelement <4 x i32> %arg1, i64 1
256  %tmp10 = extractelement <4 x i32> %arg3, i64 1
257  %tmp11 = and i32 %tmp9, 16777215
258  %tmp12 = extractelement <4 x i32> %arg1, i64 2
259  %tmp13 = extractelement <4 x i32> %arg3, i64 2
260  %tmp14 = and i32 %tmp12, 16777215
261  %tmp15 = extractelement <4 x i32> %arg1, i64 3
262  %tmp16 = extractelement <4 x i32> %arg3, i64 3
263  %tmp17 = and i32 %tmp15, 16777215
264  br label %bb19
265
266bb18:                                             ; preds = %bb19
267  ret void
268
269bb19:                                             ; preds = %bb19, %bb
270  %tmp20 = phi i32 [ %arg, %bb ], [ %tmp40, %bb19 ]
271  %tmp21 = phi i32 [ 0, %bb ], [ %tmp54, %bb19 ]
272  %tmp22 = phi <4 x i32> [ %arg2, %bb ], [ %tmp53, %bb19 ]
273  %tmp23 = and i32 %tmp20, 16777215
274  %tmp24 = mul i32 %tmp23, %tmp
275  %tmp25 = add i32 %tmp24, %arg5
276  %tmp26 = extractelement <4 x i32> %tmp22, i64 1
277  %tmp27 = and i32 %tmp26, 16777215
278  %tmp28 = mul i32 %tmp27, %tmp11
279  %tmp29 = add i32 %tmp28, %tmp10
280  %tmp30 = extractelement <4 x i32> %tmp22, i64 2
281  %tmp31 = and i32 %tmp30, 16777215
282  %tmp32 = mul i32 %tmp31, %tmp14
283  %tmp33 = add i32 %tmp32, %tmp13
284  %tmp34 = extractelement <4 x i32> %tmp22, i64 3
285  %tmp35 = and i32 %tmp34, 16777215
286  %tmp36 = mul i32 %tmp35, %tmp17
287  %tmp37 = add i32 %tmp36, %tmp16
288  %tmp38 = and i32 %tmp25, 16777215
289  %tmp39 = mul i32 %tmp38, %tmp
290  %tmp40 = add i32 %tmp39, %arg5
291  store i32 %tmp40, i32 addrspace(1)* %arg7
292  %tmp41 = insertelement <4 x i32> undef, i32 %tmp40, i32 0
293  %tmp42 = and i32 %tmp29, 16777215
294  %tmp43 = mul i32 %tmp42, %tmp11
295  %tmp44 = add i32 %tmp43, %tmp10
296  %tmp45 = insertelement <4 x i32> %tmp41, i32 %tmp44, i32 1
297  %tmp46 = and i32 %tmp33, 16777215
298  %tmp47 = mul i32 %tmp46, %tmp14
299  %tmp48 = add i32 %tmp47, %tmp13
300  %tmp49 = insertelement <4 x i32> %tmp45, i32 %tmp48, i32 2
301  %tmp50 = and i32 %tmp37, 16777215
302  %tmp51 = mul i32 %tmp50, %tmp17
303  %tmp52 = add i32 %tmp51, %tmp16
304  %tmp53 = insertelement <4 x i32> %tmp49, i32 %tmp52, i32 3
305  store <4 x i32> %tmp53, <4 x i32> addrspace(1)* %arg8
306  %tmp54 = add nuw nsw i32 %tmp21, 1
307  %tmp55 = icmp eq i32 %tmp54, %arg6
308  br i1 %tmp55, label %bb18, label %bb19
309}
310
311attributes #0 = { norecurse nounwind }
312