1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 --verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9 %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 --verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10 %s
4; RUN: llc -march=amdgcn -mcpu=gfx1100 --verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX11 %s
5
6define amdgpu_ps float @mad_i32_vvv(i32 %a, i32 %b, i32 %c) {
7; GFX9-LABEL: mad_i32_vvv:
8; GFX9:       ; %bb.0:
9; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]
10; GFX9-NEXT:    ; return to shader part epilog
11;
12; GFX10-LABEL: mad_i32_vvv:
13; GFX10:       ; %bb.0:
14; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, v1, v[2:3]
15; GFX10-NEXT:    ; return to shader part epilog
16;
17; GFX11-LABEL: mad_i32_vvv:
18; GFX11:       ; %bb.0:
19; GFX11-NEXT:    v_mov_b32_e32 v3, v1
20; GFX11-NEXT:    v_mov_b32_e32 v4, v0
21; GFX11-NEXT:    v_mad_u64_u32 v[0:1], s0, v4, v3, v[2:3]
22; GFX11-NEXT:    ; return to shader part epilog
23  %mul = mul i32 %a, %b
24  %add = add i32 %mul, %c
25  %cast = bitcast i32 %add to float
26  ret float %cast
27}
28
29define amdgpu_ps float @mad_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
30; GCN-LABEL: mad_i32_sss:
31; GCN:       ; %bb.0:
32; GCN-NEXT:    s_mul_i32 s0, s0, s1
33; GCN-NEXT:    s_add_i32 s0, s0, s2
34; GCN-NEXT:    v_mov_b32_e32 v0, s0
35; GCN-NEXT:    ; return to shader part epilog
36  %mul = mul i32 %a, %b
37  %add = add i32 %mul, %c
38  %cast = bitcast i32 %add to float
39  ret float %cast
40}
41
42define amdgpu_ps float @mad_i32_vvc(i32 %a, i32 %b) {
43; GFX9-LABEL: mad_i32_vvc:
44; GFX9:       ; %bb.0:
45; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, v1, 42
46; GFX9-NEXT:    ; return to shader part epilog
47;
48; GFX10-LABEL: mad_i32_vvc:
49; GFX10:       ; %bb.0:
50; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, v1, 42
51; GFX10-NEXT:    ; return to shader part epilog
52;
53; GFX11-LABEL: mad_i32_vvc:
54; GFX11:       ; %bb.0:
55; GFX11-NEXT:    v_mov_b32_e32 v2, v1
56; GFX11-NEXT:    v_mov_b32_e32 v3, v0
57; GFX11-NEXT:    v_mad_u64_u32 v[0:1], s0, v3, v2, 42
58; GFX11-NEXT:    ; return to shader part epilog
59  %mul = mul i32 %a, %b
60  %add = add i32 %mul, 42
61  %cast = bitcast i32 %add to float
62  ret float %cast
63}
64
65define amdgpu_ps float @mad_i32_vvi(i32 %a, i32 %b) {
66; GFX9-LABEL: mad_i32_vvi:
67; GFX9:       ; %bb.0:
68; GFX9-NEXT:    v_mov_b32_e32 v2, 0x12d687
69; GFX9-NEXT:    v_mov_b32_e32 v3, 0
70; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]
71; GFX9-NEXT:    ; return to shader part epilog
72;
73; GFX10-LABEL: mad_i32_vvi:
74; GFX10:       ; %bb.0:
75; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, v1, 0x12d687
76; GFX10-NEXT:    ; return to shader part epilog
77;
78; GFX11-LABEL: mad_i32_vvi:
79; GFX11:       ; %bb.0:
80; GFX11-NEXT:    v_mov_b32_e32 v2, v1
81; GFX11-NEXT:    v_mov_b32_e32 v3, v0
82; GFX11-NEXT:    v_mad_u64_u32 v[0:1], s0, v3, v2, 0x12d687
83; GFX11-NEXT:    ; return to shader part epilog
84  %mul = mul i32 %a, %b
85  %add = add i32 %mul, 1234567
86  %cast = bitcast i32 %add to float
87  ret float %cast
88}
89
90define amdgpu_ps float @mad_i32_vcv(i32 %a, i32 %c) {
91; GFX9-LABEL: mad_i32_vcv:
92; GFX9:       ; %bb.0:
93; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 42, v[1:2]
94; GFX9-NEXT:    ; return to shader part epilog
95;
96; GFX10-LABEL: mad_i32_vcv:
97; GFX10:       ; %bb.0:
98; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, 42, v[1:2]
99; GFX10-NEXT:    ; return to shader part epilog
100;
101; GFX11-LABEL: mad_i32_vcv:
102; GFX11:       ; %bb.0:
103; GFX11-NEXT:    v_mad_u64_u32 v[2:3], s0, v0, 42, v[1:2]
104; GFX11-NEXT:    v_mov_b32_e32 v0, v2
105; GFX11-NEXT:    ; return to shader part epilog
106  %mul = mul i32 %a, 42
107  %add = add i32 %mul, %c
108  %cast = bitcast i32 %add to float
109  ret float %cast
110}
111
112define amdgpu_ps float @mad_i32_vcc(i32 %a) {
113; GFX9-LABEL: mad_i32_vcc:
114; GFX9:       ; %bb.0:
115; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 42, 43
116; GFX9-NEXT:    ; return to shader part epilog
117;
118; GFX10-LABEL: mad_i32_vcc:
119; GFX10:       ; %bb.0:
120; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, 42, 43
121; GFX10-NEXT:    ; return to shader part epilog
122;
123; GFX11-LABEL: mad_i32_vcc:
124; GFX11:       ; %bb.0:
125; GFX11-NEXT:    v_mov_b32_e32 v2, v0
126; GFX11-NEXT:    v_mad_u64_u32 v[0:1], s0, v2, 42, 43
127; GFX11-NEXT:    ; return to shader part epilog
128  %mul = mul i32 %a, 42
129  %add = add i32 %mul, 43
130  %cast = bitcast i32 %add to float
131  ret float %cast
132}
133
134define amdgpu_ps float @mad_i32_vvs(i32 %a, i32 %b, i32 inreg %c) {
135; GFX9-LABEL: mad_i32_vvs:
136; GFX9:       ; %bb.0:
137; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, v1, s[0:1]
138; GFX9-NEXT:    ; return to shader part epilog
139;
140; GFX10-LABEL: mad_i32_vvs:
141; GFX10:       ; %bb.0:
142; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, v1, s[0:1]
143; GFX10-NEXT:    ; return to shader part epilog
144;
145; GFX11-LABEL: mad_i32_vvs:
146; GFX11:       ; %bb.0:
147; GFX11-NEXT:    v_mov_b32_e32 v2, v1
148; GFX11-NEXT:    v_mov_b32_e32 v3, v0
149; GFX11-NEXT:    v_mad_u64_u32 v[0:1], s0, v3, v2, s[0:1]
150; GFX11-NEXT:    ; return to shader part epilog
151  %mul = mul i32 %a, %b
152  %add = add i32 %mul, %c
153  %cast = bitcast i32 %add to float
154  ret float %cast
155}
156
157define amdgpu_ps float @mad_i32_vsv(i32 %a, i32 inreg %b, i32 %c) {
158; GFX9-LABEL: mad_i32_vsv:
159; GFX9:       ; %bb.0:
160; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, s0, v[1:2]
161; GFX9-NEXT:    ; return to shader part epilog
162;
163; GFX10-LABEL: mad_i32_vsv:
164; GFX10:       ; %bb.0:
165; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, s0, v[1:2]
166; GFX10-NEXT:    ; return to shader part epilog
167;
168; GFX11-LABEL: mad_i32_vsv:
169; GFX11:       ; %bb.0:
170; GFX11-NEXT:    v_mad_u64_u32 v[2:3], s0, v0, s0, v[1:2]
171; GFX11-NEXT:    v_mov_b32_e32 v0, v2
172; GFX11-NEXT:    ; return to shader part epilog
173  %mul = mul i32 %a, %b
174  %add = add i32 %mul, %c
175  %cast = bitcast i32 %add to float
176  ret float %cast
177}
178
179define amdgpu_ps float @mad_i32_svv(i32 inreg %a, i32 %b, i32 %c) {
180; GFX9-LABEL: mad_i32_svv:
181; GFX9:       ; %bb.0:
182; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s0, v0, v[1:2]
183; GFX9-NEXT:    ; return to shader part epilog
184;
185; GFX10-LABEL: mad_i32_svv:
186; GFX10:       ; %bb.0:
187; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s0, v0, v[1:2]
188; GFX10-NEXT:    ; return to shader part epilog
189;
190; GFX11-LABEL: mad_i32_svv:
191; GFX11:       ; %bb.0:
192; GFX11-NEXT:    v_mad_u64_u32 v[2:3], s0, s0, v0, v[1:2]
193; GFX11-NEXT:    v_mov_b32_e32 v0, v2
194; GFX11-NEXT:    ; return to shader part epilog
195  %mul = mul i32 %a, %b
196  %add = add i32 %mul, %c
197  %cast = bitcast i32 %add to float
198  ret float %cast
199}
200
201define amdgpu_ps float @mad_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c) {
202; GFX9-LABEL: mad_i32_vss:
203; GFX9:       ; %bb.0:
204; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s0
205; GFX9-NEXT:    v_add_u32_e32 v0, s1, v0
206; GFX9-NEXT:    ; return to shader part epilog
207;
208; GFX10-LABEL: mad_i32_vss:
209; GFX10:       ; %bb.0:
210; GFX10-NEXT:    s_mov_b32 s2, s1
211; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, v0, s0, s[2:3]
212; GFX10-NEXT:    ; return to shader part epilog
213;
214; GFX11-LABEL: mad_i32_vss:
215; GFX11:       ; %bb.0:
216; GFX11-NEXT:    v_mov_b32_e32 v2, v0
217; GFX11-NEXT:    s_mov_b32 s2, s1
218; GFX11-NEXT:    v_mad_u64_u32 v[0:1], s0, v2, s0, s[2:3]
219; GFX11-NEXT:    ; return to shader part epilog
220  %mul = mul i32 %a, %b
221  %add = add i32 %mul, %c
222  %cast = bitcast i32 %add to float
223  ret float %cast
224}
225
226define amdgpu_ps float @mad_i32_svs(i32 inreg %a, i32 %b, i32 inreg %c) {
227; GFX9-LABEL: mad_i32_svs:
228; GFX9:       ; %bb.0:
229; GFX9-NEXT:    v_mul_lo_u32 v0, s0, v0
230; GFX9-NEXT:    v_add_u32_e32 v0, s1, v0
231; GFX9-NEXT:    ; return to shader part epilog
232;
233; GFX10-LABEL: mad_i32_svs:
234; GFX10:       ; %bb.0:
235; GFX10-NEXT:    s_mov_b32 s2, s1
236; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s0, v0, s[2:3]
237; GFX10-NEXT:    ; return to shader part epilog
238;
239; GFX11-LABEL: mad_i32_svs:
240; GFX11:       ; %bb.0:
241; GFX11-NEXT:    v_mov_b32_e32 v2, v0
242; GFX11-NEXT:    s_mov_b32 s2, s1
243; GFX11-NEXT:    v_mad_u64_u32 v[0:1], s0, s0, v2, s[2:3]
244; GFX11-NEXT:    ; return to shader part epilog
245  %mul = mul i32 %a, %b
246  %add = add i32 %mul, %c
247  %cast = bitcast i32 %add to float
248  ret float %cast
249}
250
251define amdgpu_ps float @mad_i32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
252; GFX9-LABEL: mad_i32_ssv:
253; GFX9:       ; %bb.0:
254; GFX9-NEXT:    s_mul_i32 s0, s0, s1
255; GFX9-NEXT:    v_add_u32_e32 v0, s0, v0
256; GFX9-NEXT:    ; return to shader part epilog
257;
258; GFX10-LABEL: mad_i32_ssv:
259; GFX10:       ; %bb.0:
260; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s0, s1, v[0:1]
261; GFX10-NEXT:    ; return to shader part epilog
262;
263; GFX11-LABEL: mad_i32_ssv:
264; GFX11:       ; %bb.0:
265; GFX11-NEXT:    v_mad_u64_u32 v[1:2], s0, s0, s1, v[0:1]
266; GFX11-NEXT:    v_mov_b32_e32 v0, v1
267; GFX11-NEXT:    ; return to shader part epilog
268  %mul = mul i32 %a, %b
269  %add = add i32 %mul, %c
270  %cast = bitcast i32 %add to float
271  ret float %cast
272}
273
274define amdgpu_ps float @mad_i32_vvv_multiuse(i32 %a, i32 %b, i32 %c) {
275; GFX9-LABEL: mad_i32_vvv_multiuse:
276; GFX9:       ; %bb.0:
277; GFX9-NEXT:    v_mul_lo_u32 v1, v0, v1
278; GFX9-NEXT:    v_add_u32_e32 v0, v1, v2
279; GFX9-NEXT:    flat_store_dword v[0:1], v1
280; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
281; GFX9-NEXT:    ; return to shader part epilog
282;
283; GFX10-LABEL: mad_i32_vvv_multiuse:
284; GFX10:       ; %bb.0:
285; GFX10-NEXT:    v_mul_lo_u32 v1, v0, v1
286; GFX10-NEXT:    v_add_nc_u32_e32 v0, v1, v2
287; GFX10-NEXT:    flat_store_dword v[0:1], v1
288; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
289; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
290; GFX10-NEXT:    ; return to shader part epilog
291;
292; GFX11-LABEL: mad_i32_vvv_multiuse:
293; GFX11:       ; %bb.0:
294; GFX11-NEXT:    v_mul_lo_u32 v1, v0, v1
295; GFX11-NEXT:    v_add_nc_u32_e32 v0, v1, v2
296; GFX11-NEXT:    flat_store_b32 v[0:1], v1
297; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
298; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
299; GFX11-NEXT:    ; return to shader part epilog
300  %mul = mul i32 %a, %b
301  %add = add i32 %mul, %c
302  store i32 %mul, i32* undef
303  %cast = bitcast i32 %add to float
304  ret float %cast
305}
306