1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=CI %s
3; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
4
5define i64 @mad_i64_i32_sextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
6; CI-LABEL: mad_i64_i32_sextops:
7; CI:       ; %bb.0:
8; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9; CI-NEXT:    v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
10; CI-NEXT:    s_setpc_b64 s[30:31]
11;
12; SI-LABEL: mad_i64_i32_sextops:
13; SI:       ; %bb.0:
14; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15; SI-NEXT:    v_mul_lo_u32 v4, v0, v1
16; SI-NEXT:    v_mul_hi_i32 v1, v0, v1
17; SI-NEXT:    v_add_i32_e32 v0, vcc, v4, v2
18; SI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
19; SI-NEXT:    s_setpc_b64 s[30:31]
20  %sext0 = sext i32 %arg0 to i64
21  %sext1 = sext i32 %arg1 to i64
22  %mul = mul i64 %sext0, %sext1
23  %mad = add i64 %mul, %arg2
24  ret i64 %mad
25}
26
27define i64 @mad_i64_i32_sextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
28; CI-LABEL: mad_i64_i32_sextops_commute:
29; CI:       ; %bb.0:
30; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
31; CI-NEXT:    v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
32; CI-NEXT:    s_setpc_b64 s[30:31]
33;
34; SI-LABEL: mad_i64_i32_sextops_commute:
35; SI:       ; %bb.0:
36; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
37; SI-NEXT:    v_mul_lo_u32 v4, v0, v1
38; SI-NEXT:    v_mul_hi_i32 v1, v0, v1
39; SI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
40; SI-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
41; SI-NEXT:    s_setpc_b64 s[30:31]
42  %sext0 = sext i32 %arg0 to i64
43  %sext1 = sext i32 %arg1 to i64
44  %mul = mul i64 %sext0, %sext1
45  %mad = add i64 %arg2, %mul
46  ret i64 %mad
47}
48
49define i64 @mad_u64_u32_zextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
50; CI-LABEL: mad_u64_u32_zextops:
51; CI:       ; %bb.0:
52; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
53; CI-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]
54; CI-NEXT:    s_setpc_b64 s[30:31]
55;
56; SI-LABEL: mad_u64_u32_zextops:
57; SI:       ; %bb.0:
58; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
59; SI-NEXT:    v_mul_lo_u32 v4, v0, v1
60; SI-NEXT:    v_mul_hi_u32 v1, v0, v1
61; SI-NEXT:    v_add_i32_e32 v0, vcc, v4, v2
62; SI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
63; SI-NEXT:    s_setpc_b64 s[30:31]
64  %sext0 = zext i32 %arg0 to i64
65  %sext1 = zext i32 %arg1 to i64
66  %mul = mul i64 %sext0, %sext1
67  %mad = add i64 %mul, %arg2
68  ret i64 %mad
69}
70
71define i64 @mad_u64_u32_zextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
72; CI-LABEL: mad_u64_u32_zextops_commute:
73; CI:       ; %bb.0:
74; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
75; CI-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]
76; CI-NEXT:    s_setpc_b64 s[30:31]
77;
78; SI-LABEL: mad_u64_u32_zextops_commute:
79; SI:       ; %bb.0:
80; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
81; SI-NEXT:    v_mul_lo_u32 v4, v0, v1
82; SI-NEXT:    v_mul_hi_u32 v1, v0, v1
83; SI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
84; SI-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
85; SI-NEXT:    s_setpc_b64 s[30:31]
86  %sext0 = zext i32 %arg0 to i64
87  %sext1 = zext i32 %arg1 to i64
88  %mul = mul i64 %sext0, %sext1
89  %mad = add i64 %arg2, %mul
90  ret i64 %mad
91}
92
93define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {
94; CI-LABEL: mad_i64_i32_sextops_i32_i128:
95; CI:       ; %bb.0:
96; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
97; CI-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v0, v1, 0
98; CI-NEXT:    v_ashrrev_i32_e32 v13, 31, v0
99; CI-NEXT:    v_mov_b32_e32 v8, 0
100; CI-NEXT:    v_mad_u64_u32 v[9:10], s[4:5], v13, v1, v[7:8]
101; CI-NEXT:    v_ashrrev_i32_e32 v14, 31, v1
102; CI-NEXT:    v_mad_i64_i32 v[11:12], s[4:5], v1, v13, 0
103; CI-NEXT:    v_mov_b32_e32 v7, v10
104; CI-NEXT:    v_mov_b32_e32 v10, v8
105; CI-NEXT:    v_mad_u64_u32 v[8:9], s[4:5], v0, v14, v[9:10]
106; CI-NEXT:    v_mad_i64_i32 v[0:1], s[4:5], v14, v0, v[11:12]
107; CI-NEXT:    v_add_i32_e32 v9, vcc, v7, v9
108; CI-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, vcc
109; CI-NEXT:    v_mad_u64_u32 v[9:10], s[4:5], v13, v14, v[9:10]
110; CI-NEXT:    v_add_i32_e32 v7, vcc, v9, v0
111; CI-NEXT:    v_addc_u32_e32 v9, vcc, v10, v1, vcc
112; CI-NEXT:    v_mov_b32_e32 v1, v8
113; CI-NEXT:    v_add_i32_e32 v0, vcc, v6, v2
114; CI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
115; CI-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
116; CI-NEXT:    v_addc_u32_e32 v3, vcc, v9, v5, vcc
117; CI-NEXT:    s_setpc_b64 s[30:31]
118;
119; SI-LABEL: mad_i64_i32_sextops_i32_i128:
120; SI:       ; %bb.0:
121; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
122; SI-NEXT:    v_ashrrev_i32_e32 v6, 31, v0
123; SI-NEXT:    v_mul_lo_u32 v11, v6, v1
124; SI-NEXT:    v_mul_hi_u32 v12, v0, v1
125; SI-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
126; SI-NEXT:    v_mul_hi_u32 v14, v6, v1
127; SI-NEXT:    v_mul_lo_u32 v13, v0, v7
128; SI-NEXT:    v_mul_hi_u32 v10, v0, v7
129; SI-NEXT:    v_add_i32_e32 v12, vcc, v11, v12
130; SI-NEXT:    v_addc_u32_e32 v14, vcc, 0, v14, vcc
131; SI-NEXT:    v_mul_hi_u32 v8, v6, v7
132; SI-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
133; SI-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
134; SI-NEXT:    v_mul_i32_i24_e32 v9, v6, v7
135; SI-NEXT:    v_add_i32_e32 v10, vcc, v14, v10
136; SI-NEXT:    v_mul_hi_i32 v6, v1, v6
137; SI-NEXT:    v_mul_hi_i32 v7, v7, v0
138; SI-NEXT:    v_addc_u32_e64 v14, s[4:5], 0, 0, vcc
139; SI-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
140; SI-NEXT:    v_addc_u32_e32 v8, vcc, v8, v14, vcc
141; SI-NEXT:    v_add_i32_e32 v10, vcc, v13, v11
142; SI-NEXT:    v_mul_lo_u32 v0, v0, v1
143; SI-NEXT:    v_addc_u32_e32 v6, vcc, v7, v6, vcc
144; SI-NEXT:    v_add_i32_e32 v7, vcc, v9, v10
145; SI-NEXT:    v_addc_u32_e32 v6, vcc, v8, v6, vcc
146; SI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
147; SI-NEXT:    v_addc_u32_e32 v1, vcc, v12, v3, vcc
148; SI-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
149; SI-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
150; SI-NEXT:    s_setpc_b64 s[30:31]
151  %sext0 = sext i32 %arg0 to i128
152  %sext1 = sext i32 %arg1 to i128
153  %mul = mul i128 %sext0, %sext1
154  %mad = add i128 %mul, %arg2
155  ret i128 %mad
156}
157
158define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
159; CI-LABEL: mad_i64_i32_sextops_i32_i63:
160; CI:       ; %bb.0:
161; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
162; CI-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
163; CI-NEXT:    v_ashr_i64 v[2:3], v[2:3], 1
164; CI-NEXT:    v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
165; CI-NEXT:    s_setpc_b64 s[30:31]
166;
167; SI-LABEL: mad_i64_i32_sextops_i32_i63:
168; SI:       ; %bb.0:
169; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
170; SI-NEXT:    v_mul_lo_u32 v4, v0, v1
171; SI-NEXT:    v_mul_hi_i32 v1, v0, v1
172; SI-NEXT:    v_add_i32_e32 v0, vcc, v4, v2
173; SI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
174; SI-NEXT:    s_setpc_b64 s[30:31]
175  %sext0 = sext i32 %arg0 to i63
176  %sext1 = sext i32 %arg1 to i63
177  %mul = mul i63 %sext0, %sext1
178  %mad = add i63 %mul, %arg2
179  ret i63 %mad
180}
181
182define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
183; CI-LABEL: mad_i64_i32_sextops_i31_i63:
184; CI:       ; %bb.0:
185; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
186; CI-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
187; CI-NEXT:    v_bfe_i32 v1, v1, 0, 31
188; CI-NEXT:    v_ashr_i64 v[2:3], v[2:3], 1
189; CI-NEXT:    v_bfe_i32 v0, v0, 0, 31
190; CI-NEXT:    v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
191; CI-NEXT:    s_setpc_b64 s[30:31]
192;
193; SI-LABEL: mad_i64_i32_sextops_i31_i63:
194; SI:       ; %bb.0:
195; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
196; SI-NEXT:    v_lshlrev_b32_e32 v4, 1, v0
197; SI-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
198; SI-NEXT:    v_ashr_i64 v[4:5], v[3:4], 33
199; SI-NEXT:    v_ashr_i64 v[0:1], v[0:1], 33
200; SI-NEXT:    v_mul_lo_u32 v1, v4, v0
201; SI-NEXT:    v_mul_hi_i32 v4, v4, v0
202; SI-NEXT:    v_add_i32_e32 v0, vcc, v1, v2
203; SI-NEXT:    v_addc_u32_e32 v1, vcc, v4, v3, vcc
204; SI-NEXT:    s_setpc_b64 s[30:31]
205  %sext0 = sext i31 %arg0 to i63
206  %sext1 = sext i31 %arg1 to i63
207  %mul = mul i63 %sext0, %sext1
208  %mad = add i63 %mul, %arg2
209  ret i63 %mad
210}
211
212define i64 @mad_u64_u32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
213; CI-LABEL: mad_u64_u32_bitops:
214; CI:       ; %bb.0:
215; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
216; CI-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[4:5]
217; CI-NEXT:    s_setpc_b64 s[30:31]
218;
219; SI-LABEL: mad_u64_u32_bitops:
220; SI:       ; %bb.0:
221; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
222; SI-NEXT:    v_mul_lo_u32 v1, v0, v2
223; SI-NEXT:    v_mul_hi_u32 v2, v0, v2
224; SI-NEXT:    v_add_i32_e32 v0, vcc, v1, v4
225; SI-NEXT:    v_addc_u32_e32 v1, vcc, v2, v5, vcc
226; SI-NEXT:    s_setpc_b64 s[30:31]
227  %trunc.lhs = and i64 %arg0, 4294967295
228  %trunc.rhs = and i64 %arg1, 4294967295
229  %mul = mul i64 %trunc.lhs, %trunc.rhs
230  %add = add i64 %mul, %arg2
231  ret i64 %add
232}
233
234define i64 @mad_u64_u32_bitops_lhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
235; CI-LABEL: mad_u64_u32_bitops_lhs_mask_small:
236; CI:       ; %bb.0:
237; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
238; CI-NEXT:    v_and_b32_e32 v1, 1, v1
239; CI-NEXT:    v_mul_lo_u32 v3, v1, v2
240; CI-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 0
241; CI-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
242; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
243; CI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
244; CI-NEXT:    s_setpc_b64 s[30:31]
245;
246; SI-LABEL: mad_u64_u32_bitops_lhs_mask_small:
247; SI:       ; %bb.0:
248; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
249; SI-NEXT:    v_and_b32_e32 v1, 1, v1
250; SI-NEXT:    v_mul_hi_u32 v3, v0, v2
251; SI-NEXT:    v_mul_lo_u32 v1, v1, v2
252; SI-NEXT:    v_mul_lo_u32 v0, v0, v2
253; SI-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
254; SI-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
255; SI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
256; SI-NEXT:    s_setpc_b64 s[30:31]
257  %trunc.lhs = and i64 %arg0, 8589934591
258  %trunc.rhs = and i64 %arg1, 4294967295
259  %mul = mul i64 %trunc.lhs, %trunc.rhs
260  %add = add i64 %mul, %arg2
261  ret i64 %add
262}
263
264define i64 @mad_u64_u32_bitops_rhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
265; CI-LABEL: mad_u64_u32_bitops_rhs_mask_small:
266; CI:       ; %bb.0:
267; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
268; CI-NEXT:    v_and_b32_e32 v1, 1, v3
269; CI-NEXT:    v_mul_lo_u32 v3, v0, v1
270; CI-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 0
271; CI-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
272; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
273; CI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
274; CI-NEXT:    s_setpc_b64 s[30:31]
275;
276; SI-LABEL: mad_u64_u32_bitops_rhs_mask_small:
277; SI:       ; %bb.0:
278; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
279; SI-NEXT:    v_and_b32_e32 v1, 1, v3
280; SI-NEXT:    v_mul_hi_u32 v3, v0, v2
281; SI-NEXT:    v_mul_lo_u32 v1, v0, v1
282; SI-NEXT:    v_mul_lo_u32 v0, v0, v2
283; SI-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
284; SI-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
285; SI-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
286; SI-NEXT:    s_setpc_b64 s[30:31]
287  %trunc.lhs = and i64 %arg0, 4294967295
288  %trunc.rhs = and i64 %arg1, 8589934591
289  %mul = mul i64 %trunc.lhs, %trunc.rhs
290  %add = add i64 %mul, %arg2
291  ret i64 %add
292}
293
294define i64 @mad_i64_i32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
295; CI-LABEL: mad_i64_i32_bitops:
296; CI:       ; %bb.0:
297; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
298; CI-NEXT:    v_mad_i64_i32 v[0:1], s[4:5], v0, v2, v[4:5]
299; CI-NEXT:    s_setpc_b64 s[30:31]
300;
301; SI-LABEL: mad_i64_i32_bitops:
302; SI:       ; %bb.0:
303; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
304; SI-NEXT:    v_mul_lo_u32 v1, v0, v2
305; SI-NEXT:    v_mul_hi_i32 v2, v0, v2
306; SI-NEXT:    v_add_i32_e32 v0, vcc, v1, v4
307; SI-NEXT:    v_addc_u32_e32 v1, vcc, v2, v5, vcc
308; SI-NEXT:    s_setpc_b64 s[30:31]
309  %shl.lhs = shl i64 %arg0, 32
310  %trunc.lhs = ashr i64 %shl.lhs, 32
311  %shl.rhs = shl i64 %arg1, 32
312  %trunc.rhs = ashr i64 %shl.rhs, 32
313  %mul = mul i64 %trunc.lhs, %trunc.rhs
314  %add = add i64 %mul, %arg2
315  ret i64 %add
316}
317
318; Example from bug report
319define i64 @mad_i64_i32_unpack_i64ops(i64 %arg0) #0 {
320; CI-LABEL: mad_i64_i32_unpack_i64ops:
321; CI:       ; %bb.0:
322; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
323; CI-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v1, v0, v[0:1]
324; CI-NEXT:    s_setpc_b64 s[30:31]
325;
326; SI-LABEL: mad_i64_i32_unpack_i64ops:
327; SI:       ; %bb.0:
328; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
329; SI-NEXT:    v_mul_lo_u32 v2, v1, v0
330; SI-NEXT:    v_mul_hi_u32 v3, v1, v0
331; SI-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
332; SI-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
333; SI-NEXT:    s_setpc_b64 s[30:31]
334  %tmp4 = lshr i64 %arg0, 32
335  %tmp5 = and i64 %arg0, 4294967295
336  %mul = mul nuw i64 %tmp4, %tmp5
337  %mad = add i64 %mul, %arg0
338  ret i64 %mad
339}
340
341attributes #0 = { nounwind }
342attributes #1 = { nounwind readnone speculatable }
343