1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s 3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s 4; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s 5; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s 6; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s 7 8define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 { 9; GFX9-LABEL: s_lshr_v2i16: 10; GFX9: ; %bb.0: 11; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c 12; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 13; GFX9-NEXT: v_mov_b32_e32 v0, 0 14; GFX9-NEXT: s_waitcnt lgkmcnt(0) 15; GFX9-NEXT: v_mov_b32_e32 v1, s2 16; GFX9-NEXT: v_pk_lshrrev_b16 v1, s3, v1 17; GFX9-NEXT: global_store_dword v0, v1, s[4:5] 18; GFX9-NEXT: s_endpgm 19; 20; VI-LABEL: s_lshr_v2i16: 21; VI: ; %bb.0: 22; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c 23; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 24; VI-NEXT: s_waitcnt lgkmcnt(0) 25; VI-NEXT: s_and_b32 s4, s2, 0xffff 26; VI-NEXT: s_lshr_b32 s2, s2, 16 27; VI-NEXT: s_lshr_b32 s5, s3, 16 28; VI-NEXT: s_lshr_b32 s2, s2, s5 29; VI-NEXT: s_lshr_b32 s3, s4, s3 30; VI-NEXT: s_lshl_b32 s2, s2, 16 31; VI-NEXT: s_or_b32 s2, s3, s2 32; VI-NEXT: v_mov_b32_e32 v0, s0 33; VI-NEXT: v_mov_b32_e32 v1, s1 34; VI-NEXT: v_mov_b32_e32 v2, s2 35; VI-NEXT: flat_store_dword v[0:1], v2 36; VI-NEXT: s_endpgm 37; 38; CI-LABEL: s_lshr_v2i16: 39; CI: ; %bb.0: 40; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 41; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 42; CI-NEXT: s_mov_b32 s3, 0xf000 43; CI-NEXT: s_mov_b32 s2, -1 44; CI-NEXT: s_waitcnt lgkmcnt(0) 45; CI-NEXT: s_and_b32 s6, s4, 0xffff 46; CI-NEXT: s_lshr_b32 s4, s4, 16 47; CI-NEXT: s_lshr_b32 s7, s5, 16 48; CI-NEXT: s_lshr_b32 s4, s4, s7 49; CI-NEXT: s_lshl_b32 s4, s4, 16 50; CI-NEXT: s_lshr_b32 s5, s6, s5 51; CI-NEXT: s_or_b32 s4, s5, s4 52; CI-NEXT: v_mov_b32_e32 v0, s4 53; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 54; CI-NEXT: s_endpgm 55; 56; GFX10-LABEL: s_lshr_v2i16: 57; GFX10: ; %bb.0: 58; GFX10-NEXT: s_clause 0x1 59; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c 60; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 61; GFX10-NEXT: v_mov_b32_e32 v0, 0 62; GFX10-NEXT: s_waitcnt lgkmcnt(0) 63; GFX10-NEXT: v_pk_lshrrev_b16 v1, s3, s2 64; GFX10-NEXT: global_store_dword v0, v1, s[4:5] 65; GFX10-NEXT: s_endpgm 66; 67; GFX11-LABEL: s_lshr_v2i16: 68; GFX11: ; %bb.0: 69; GFX11-NEXT: s_clause 0x1 70; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x2c 71; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 72; GFX11-NEXT: v_mov_b32_e32 v0, 0 73; GFX11-NEXT: s_waitcnt lgkmcnt(0) 74; GFX11-NEXT: v_pk_lshrrev_b16 v1, s3, s2 75; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 76; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 77; GFX11-NEXT: s_endpgm 78 %result = lshr <2 x i16> %lhs, %rhs 79 store <2 x i16> %result, <2 x i16> addrspace(1)* %out 80 ret void 81} 82 83define amdgpu_kernel void @v_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 84; GFX9-LABEL: v_lshr_v2i16: 85; GFX9: ; %bb.0: 86; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 87; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 88; GFX9-NEXT: s_waitcnt lgkmcnt(0) 89; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] 90; GFX9-NEXT: s_waitcnt vmcnt(0) 91; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0 92; GFX9-NEXT: global_store_dword v2, v0, s[0:1] 93; GFX9-NEXT: s_endpgm 94; 95; VI-LABEL: v_lshr_v2i16: 96; VI: ; %bb.0: 97; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 98; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 99; VI-NEXT: s_waitcnt lgkmcnt(0) 100; VI-NEXT: v_mov_b32_e32 v1, s3 101; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 102; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 103; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] 104; VI-NEXT: v_mov_b32_e32 v3, s1 105; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 106; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 107; VI-NEXT: s_waitcnt vmcnt(0) 108; VI-NEXT: v_lshrrev_b16_e32 v4, v1, v0 109; VI-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 110; VI-NEXT: v_or_b32_e32 v0, v4, v0 111; VI-NEXT: flat_store_dword v[2:3], v0 112; VI-NEXT: s_endpgm 113; 114; CI-LABEL: v_lshr_v2i16: 115; CI: ; %bb.0: 116; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 117; CI-NEXT: s_mov_b32 s7, 0xf000 118; CI-NEXT: s_mov_b32 s6, 0 119; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 120; CI-NEXT: v_mov_b32_e32 v1, 0 121; CI-NEXT: s_waitcnt lgkmcnt(0) 122; CI-NEXT: s_mov_b64 s[4:5], s[2:3] 123; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 124; CI-NEXT: s_mov_b64 s[2:3], s[6:7] 125; CI-NEXT: s_waitcnt vmcnt(0) 126; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 127; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2 128; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 129; CI-NEXT: v_lshrrev_b32_e32 v2, v3, v2 130; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v4 131; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 132; CI-NEXT: v_or_b32_e32 v2, v2, v3 133; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 134; CI-NEXT: s_endpgm 135; 136; GFX10-LABEL: v_lshr_v2i16: 137; GFX10: ; %bb.0: 138; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 139; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 140; GFX10-NEXT: s_waitcnt lgkmcnt(0) 141; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] 142; GFX10-NEXT: s_waitcnt vmcnt(0) 143; GFX10-NEXT: v_pk_lshrrev_b16 v0, v1, v0 144; GFX10-NEXT: global_store_dword v2, v0, s[0:1] 145; GFX10-NEXT: s_endpgm 146; 147; GFX11-LABEL: v_lshr_v2i16: 148; GFX11: ; %bb.0: 149; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 150; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0 151; GFX11-NEXT: s_waitcnt lgkmcnt(0) 152; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3] 153; GFX11-NEXT: s_waitcnt vmcnt(0) 154; GFX11-NEXT: v_pk_lshrrev_b16 v0, v1, v0 155; GFX11-NEXT: global_store_b32 v2, v0, s[0:1] 156; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 157; GFX11-NEXT: s_endpgm 158 %tid = call i32 @llvm.amdgcn.workitem.id.x() 159 %tid.ext = sext i32 %tid to i64 160 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 161 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 162 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1 163 %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 164 %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr 165 %result = lshr <2 x i16> %a, %b 166 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep 167 ret void 168} 169 170define amdgpu_kernel void @lshr_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 { 171; GFX9-LABEL: lshr_v_s_v2i16: 172; GFX9: ; %bb.0: 173; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 174; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34 175; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 176; GFX9-NEXT: s_waitcnt lgkmcnt(0) 177; GFX9-NEXT: global_load_dword v1, v0, s[6:7] 178; GFX9-NEXT: s_waitcnt vmcnt(0) 179; GFX9-NEXT: v_pk_lshrrev_b16 v1, s2, v1 180; GFX9-NEXT: global_store_dword v0, v1, s[4:5] 181; GFX9-NEXT: s_endpgm 182; 183; VI-LABEL: lshr_v_s_v2i16: 184; VI: ; %bb.0: 185; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 186; VI-NEXT: s_load_dword s0, s[0:1], 0x34 187; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 188; VI-NEXT: s_waitcnt lgkmcnt(0) 189; VI-NEXT: v_mov_b32_e32 v1, s7 190; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 191; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 192; VI-NEXT: flat_load_dword v3, v[0:1] 193; VI-NEXT: s_lshr_b32 s1, s0, 16 194; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2 195; VI-NEXT: v_mov_b32_e32 v2, s1 196; VI-NEXT: v_mov_b32_e32 v1, s5 197; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 198; VI-NEXT: s_waitcnt vmcnt(0) 199; VI-NEXT: v_lshrrev_b16_e32 v4, s0, v3 200; VI-NEXT: v_lshrrev_b16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 201; VI-NEXT: v_or_b32_e32 v2, v4, v2 202; VI-NEXT: flat_store_dword v[0:1], v2 203; VI-NEXT: s_endpgm 204; 205; CI-LABEL: lshr_v_s_v2i16: 206; CI: ; %bb.0: 207; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 208; CI-NEXT: s_load_dword s8, s[0:1], 0xd 209; CI-NEXT: s_mov_b32 s3, 0xf000 210; CI-NEXT: s_mov_b32 s2, 0 211; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 212; CI-NEXT: s_waitcnt lgkmcnt(0) 213; CI-NEXT: s_mov_b64 s[0:1], s[6:7] 214; CI-NEXT: v_mov_b32_e32 v1, 0 215; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 216; CI-NEXT: s_lshr_b32 s0, s8, 16 217; CI-NEXT: s_mov_b64 s[6:7], s[2:3] 218; CI-NEXT: s_waitcnt vmcnt(0) 219; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 220; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2 221; CI-NEXT: v_lshrrev_b32_e32 v3, s0, v3 222; CI-NEXT: v_lshrrev_b32_e32 v2, s8, v2 223; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 224; CI-NEXT: v_or_b32_e32 v2, v2, v3 225; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 226; CI-NEXT: s_endpgm 227; 228; GFX10-LABEL: lshr_v_s_v2i16: 229; GFX10: ; %bb.0: 230; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 231; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 232; GFX10-NEXT: s_load_dword s0, s[0:1], 0x34 233; GFX10-NEXT: s_waitcnt lgkmcnt(0) 234; GFX10-NEXT: global_load_dword v1, v0, s[6:7] 235; GFX10-NEXT: s_waitcnt vmcnt(0) 236; GFX10-NEXT: v_pk_lshrrev_b16 v1, s0, v1 237; GFX10-NEXT: global_store_dword v0, v1, s[4:5] 238; GFX10-NEXT: s_endpgm 239; 240; GFX11-LABEL: lshr_v_s_v2i16: 241; GFX11: ; %bb.0: 242; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 243; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 244; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x34 245; GFX11-NEXT: s_waitcnt lgkmcnt(0) 246; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] 247; GFX11-NEXT: s_waitcnt vmcnt(0) 248; GFX11-NEXT: v_pk_lshrrev_b16 v1, s0, v1 249; GFX11-NEXT: global_store_b32 v0, v1, s[4:5] 250; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 251; GFX11-NEXT: s_endpgm 252 %tid = call i32 @llvm.amdgcn.workitem.id.x() 253 %tid.ext = sext i32 %tid to i64 254 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 255 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 256 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 257 %result = lshr <2 x i16> %vgpr, %sgpr 258 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep 259 ret void 260} 261 262define amdgpu_kernel void @lshr_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 { 263; GFX9-LABEL: lshr_s_v_v2i16: 264; GFX9: ; %bb.0: 265; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 266; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34 267; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 268; GFX9-NEXT: s_waitcnt lgkmcnt(0) 269; GFX9-NEXT: global_load_dword v1, v0, s[6:7] 270; GFX9-NEXT: s_waitcnt vmcnt(0) 271; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, s2 272; GFX9-NEXT: global_store_dword v0, v1, s[4:5] 273; GFX9-NEXT: s_endpgm 274; 275; VI-LABEL: lshr_s_v_v2i16: 276; VI: ; %bb.0: 277; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 278; VI-NEXT: s_load_dword s0, s[0:1], 0x34 279; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 280; VI-NEXT: s_waitcnt lgkmcnt(0) 281; VI-NEXT: v_mov_b32_e32 v1, s7 282; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 283; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 284; VI-NEXT: flat_load_dword v3, v[0:1] 285; VI-NEXT: s_lshr_b32 s1, s0, 16 286; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2 287; VI-NEXT: v_mov_b32_e32 v2, s1 288; VI-NEXT: v_mov_b32_e32 v1, s5 289; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 290; VI-NEXT: s_waitcnt vmcnt(0) 291; VI-NEXT: v_lshrrev_b16_e64 v4, v3, s0 292; VI-NEXT: v_lshrrev_b16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 293; VI-NEXT: v_or_b32_e32 v2, v4, v2 294; VI-NEXT: flat_store_dword v[0:1], v2 295; VI-NEXT: s_endpgm 296; 297; CI-LABEL: lshr_s_v_v2i16: 298; CI: ; %bb.0: 299; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 300; CI-NEXT: s_load_dword s8, s[0:1], 0xd 301; CI-NEXT: s_mov_b32 s3, 0xf000 302; CI-NEXT: s_mov_b32 s2, 0 303; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 304; CI-NEXT: s_waitcnt lgkmcnt(0) 305; CI-NEXT: s_mov_b64 s[0:1], s[6:7] 306; CI-NEXT: v_mov_b32_e32 v1, 0 307; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 308; CI-NEXT: s_lshr_b32 s0, s8, 16 309; CI-NEXT: s_and_b32 s1, s8, 0xffff 310; CI-NEXT: s_mov_b64 s[6:7], s[2:3] 311; CI-NEXT: s_waitcnt vmcnt(0) 312; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 313; CI-NEXT: v_lshr_b32_e32 v3, s0, v3 314; CI-NEXT: v_lshr_b32_e32 v2, s1, v2 315; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 316; CI-NEXT: v_or_b32_e32 v2, v2, v3 317; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 318; CI-NEXT: s_endpgm 319; 320; GFX10-LABEL: lshr_s_v_v2i16: 321; GFX10: ; %bb.0: 322; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 323; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 324; GFX10-NEXT: s_load_dword s0, s[0:1], 0x34 325; GFX10-NEXT: s_waitcnt lgkmcnt(0) 326; GFX10-NEXT: global_load_dword v1, v0, s[6:7] 327; GFX10-NEXT: s_waitcnt vmcnt(0) 328; GFX10-NEXT: v_pk_lshrrev_b16 v1, v1, s0 329; GFX10-NEXT: global_store_dword v0, v1, s[4:5] 330; GFX10-NEXT: s_endpgm 331; 332; GFX11-LABEL: lshr_s_v_v2i16: 333; GFX11: ; %bb.0: 334; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 335; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 336; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x34 337; GFX11-NEXT: s_waitcnt lgkmcnt(0) 338; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] 339; GFX11-NEXT: s_waitcnt vmcnt(0) 340; GFX11-NEXT: v_pk_lshrrev_b16 v1, v1, s0 341; GFX11-NEXT: global_store_b32 v0, v1, s[4:5] 342; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 343; GFX11-NEXT: s_endpgm 344 %tid = call i32 @llvm.amdgcn.workitem.id.x() 345 %tid.ext = sext i32 %tid to i64 346 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 347 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 348 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 349 %result = lshr <2 x i16> %sgpr, %vgpr 350 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep 351 ret void 352} 353 354define amdgpu_kernel void @lshr_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 355; GFX9-LABEL: lshr_imm_v_v2i16: 356; GFX9: ; %bb.0: 357; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 358; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 359; GFX9-NEXT: s_waitcnt lgkmcnt(0) 360; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 361; GFX9-NEXT: s_waitcnt vmcnt(0) 362; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, 8 op_sel_hi:[1,0] 363; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 364; GFX9-NEXT: s_endpgm 365; 366; VI-LABEL: lshr_imm_v_v2i16: 367; VI: ; %bb.0: 368; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 369; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 370; VI-NEXT: v_mov_b32_e32 v4, 8 371; VI-NEXT: s_waitcnt lgkmcnt(0) 372; VI-NEXT: v_mov_b32_e32 v1, s3 373; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 374; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 375; VI-NEXT: flat_load_dword v3, v[0:1] 376; VI-NEXT: v_mov_b32_e32 v1, s1 377; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 378; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 379; VI-NEXT: s_waitcnt vmcnt(0) 380; VI-NEXT: v_lshrrev_b16_e64 v2, v3, 8 381; VI-NEXT: v_lshrrev_b16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 382; VI-NEXT: v_or_b32_e32 v2, v2, v3 383; VI-NEXT: flat_store_dword v[0:1], v2 384; VI-NEXT: s_endpgm 385; 386; CI-LABEL: lshr_imm_v_v2i16: 387; CI: ; %bb.0: 388; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 389; CI-NEXT: s_mov_b32 s7, 0xf000 390; CI-NEXT: s_mov_b32 s6, 0 391; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 392; CI-NEXT: v_mov_b32_e32 v1, 0 393; CI-NEXT: s_waitcnt lgkmcnt(0) 394; CI-NEXT: s_mov_b64 s[4:5], s[2:3] 395; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 396; CI-NEXT: s_mov_b64 s[2:3], s[6:7] 397; CI-NEXT: s_waitcnt vmcnt(0) 398; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 399; CI-NEXT: v_lshr_b32_e32 v3, 8, v3 400; CI-NEXT: v_lshr_b32_e32 v2, 8, v2 401; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 402; CI-NEXT: v_or_b32_e32 v2, v2, v3 403; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 404; CI-NEXT: s_endpgm 405; 406; GFX10-LABEL: lshr_imm_v_v2i16: 407; GFX10: ; %bb.0: 408; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 409; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 410; GFX10-NEXT: s_waitcnt lgkmcnt(0) 411; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 412; GFX10-NEXT: s_waitcnt vmcnt(0) 413; GFX10-NEXT: v_pk_lshrrev_b16 v1, v1, 8 op_sel_hi:[1,0] 414; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 415; GFX10-NEXT: s_endpgm 416; 417; GFX11-LABEL: lshr_imm_v_v2i16: 418; GFX11: ; %bb.0: 419; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 420; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 421; GFX11-NEXT: s_waitcnt lgkmcnt(0) 422; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 423; GFX11-NEXT: s_waitcnt vmcnt(0) 424; GFX11-NEXT: v_pk_lshrrev_b16 v1, v1, 8 op_sel_hi:[1,0] 425; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 426; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 427; GFX11-NEXT: s_endpgm 428 %tid = call i32 @llvm.amdgcn.workitem.id.x() 429 %tid.ext = sext i32 %tid to i64 430 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 431 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 432 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 433 %result = lshr <2 x i16> <i16 8, i16 8>, %vgpr 434 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep 435 ret void 436} 437 438define amdgpu_kernel void @lshr_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 439; GFX9-LABEL: lshr_v_imm_v2i16: 440; GFX9: ; %bb.0: 441; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 442; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 443; GFX9-NEXT: s_waitcnt lgkmcnt(0) 444; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 445; GFX9-NEXT: s_waitcnt vmcnt(0) 446; GFX9-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1] 447; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 448; GFX9-NEXT: s_endpgm 449; 450; VI-LABEL: lshr_v_imm_v2i16: 451; VI: ; %bb.0: 452; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 453; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 454; VI-NEXT: s_waitcnt lgkmcnt(0) 455; VI-NEXT: v_mov_b32_e32 v1, s3 456; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 457; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 458; VI-NEXT: flat_load_dword v3, v[0:1] 459; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 460; VI-NEXT: v_mov_b32_e32 v1, s1 461; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 462; VI-NEXT: s_waitcnt vmcnt(0) 463; VI-NEXT: v_lshrrev_b32_e32 v2, 24, v3 464; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 465; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD 466; VI-NEXT: flat_store_dword v[0:1], v2 467; VI-NEXT: s_endpgm 468; 469; CI-LABEL: lshr_v_imm_v2i16: 470; CI: ; %bb.0: 471; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 472; CI-NEXT: s_mov_b32 s7, 0xf000 473; CI-NEXT: s_mov_b32 s6, 0 474; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 475; CI-NEXT: v_mov_b32_e32 v1, 0 476; CI-NEXT: s_waitcnt lgkmcnt(0) 477; CI-NEXT: s_mov_b64 s[4:5], s[2:3] 478; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 479; CI-NEXT: s_mov_b64 s[2:3], s[6:7] 480; CI-NEXT: s_waitcnt vmcnt(0) 481; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2 482; CI-NEXT: v_and_b32_e32 v2, 0xff00ff, v2 483; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 484; CI-NEXT: s_endpgm 485; 486; GFX10-LABEL: lshr_v_imm_v2i16: 487; GFX10: ; %bb.0: 488; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 489; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 490; GFX10-NEXT: s_waitcnt lgkmcnt(0) 491; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 492; GFX10-NEXT: s_waitcnt vmcnt(0) 493; GFX10-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1] 494; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 495; GFX10-NEXT: s_endpgm 496; 497; GFX11-LABEL: lshr_v_imm_v2i16: 498; GFX11: ; %bb.0: 499; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 500; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 501; GFX11-NEXT: s_waitcnt lgkmcnt(0) 502; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 503; GFX11-NEXT: s_waitcnt vmcnt(0) 504; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1] 505; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 506; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 507; GFX11-NEXT: s_endpgm 508 %tid = call i32 @llvm.amdgcn.workitem.id.x() 509 %tid.ext = sext i32 %tid to i64 510 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 511 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 512 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 513 %result = lshr <2 x i16> %vgpr, <i16 8, i16 8> 514 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep 515 ret void 516} 517 518define amdgpu_kernel void @v_lshr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { 519; GFX9-LABEL: v_lshr_v4i16: 520; GFX9: ; %bb.0: 521; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 522; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0 523; GFX9-NEXT: s_waitcnt lgkmcnt(0) 524; GFX9-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3] 525; GFX9-NEXT: s_waitcnt vmcnt(0) 526; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1 527; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0 528; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] 529; GFX9-NEXT: s_endpgm 530; 531; VI-LABEL: v_lshr_v4i16: 532; VI: ; %bb.0: 533; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 534; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 535; VI-NEXT: s_waitcnt lgkmcnt(0) 536; VI-NEXT: v_mov_b32_e32 v1, s3 537; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 538; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 539; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] 540; VI-NEXT: v_mov_b32_e32 v5, s1 541; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 542; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc 543; VI-NEXT: s_waitcnt vmcnt(0) 544; VI-NEXT: v_lshrrev_b16_e32 v6, v3, v1 545; VI-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 546; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v0 547; VI-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 548; VI-NEXT: v_or_b32_e32 v1, v6, v1 549; VI-NEXT: v_or_b32_e32 v0, v3, v0 550; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] 551; VI-NEXT: s_endpgm 552; 553; CI-LABEL: v_lshr_v4i16: 554; CI: ; %bb.0: 555; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 556; CI-NEXT: s_mov_b32 s7, 0xf000 557; CI-NEXT: s_mov_b32 s6, 0 558; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 559; CI-NEXT: v_mov_b32_e32 v5, 0 560; CI-NEXT: s_waitcnt lgkmcnt(0) 561; CI-NEXT: s_mov_b64 s[4:5], s[2:3] 562; CI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64 563; CI-NEXT: s_mov_b64 s[2:3], s[6:7] 564; CI-NEXT: s_waitcnt vmcnt(0) 565; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v0 566; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0 567; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v1 568; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1 569; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v2 570; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v3 571; CI-NEXT: v_lshrrev_b32_e32 v1, v3, v1 572; CI-NEXT: v_lshrrev_b32_e32 v3, v9, v7 573; CI-NEXT: v_lshrrev_b32_e32 v0, v2, v0 574; CI-NEXT: v_lshrrev_b32_e32 v2, v8, v6 575; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 576; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 577; CI-NEXT: v_or_b32_e32 v1, v1, v3 578; CI-NEXT: v_or_b32_e32 v0, v0, v2 579; CI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64 580; CI-NEXT: s_endpgm 581; 582; GFX10-LABEL: v_lshr_v4i16: 583; GFX10: ; %bb.0: 584; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 585; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0 586; GFX10-NEXT: s_waitcnt lgkmcnt(0) 587; GFX10-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3] 588; GFX10-NEXT: s_waitcnt vmcnt(0) 589; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1 590; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0 591; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] 592; GFX10-NEXT: s_endpgm 593; 594; GFX11-LABEL: v_lshr_v4i16: 595; GFX11: ; %bb.0: 596; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 597; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0 598; GFX11-NEXT: s_waitcnt lgkmcnt(0) 599; GFX11-NEXT: global_load_b128 v[0:3], v4, s[2:3] 600; GFX11-NEXT: s_waitcnt vmcnt(0) 601; GFX11-NEXT: v_pk_lshrrev_b16 v1, v3, v1 602; GFX11-NEXT: v_pk_lshrrev_b16 v0, v2, v0 603; GFX11-NEXT: global_store_b64 v4, v[0:1], s[0:1] 604; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 605; GFX11-NEXT: s_endpgm 606 %tid = call i32 @llvm.amdgcn.workitem.id.x() 607 %tid.ext = sext i32 %tid to i64 608 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext 609 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext 610 %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in.gep, i32 1 611 %a = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep 612 %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr 613 %result = lshr <4 x i16> %a, %b 614 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep 615 ret void 616} 617 618define amdgpu_kernel void @lshr_v_imm_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { 619; GFX9-LABEL: lshr_v_imm_v4i16: 620; GFX9: ; %bb.0: 621; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 622; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0 623; GFX9-NEXT: s_waitcnt lgkmcnt(0) 624; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] 625; GFX9-NEXT: s_waitcnt vmcnt(0) 626; GFX9-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1] 627; GFX9-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1] 628; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] 629; GFX9-NEXT: s_endpgm 630; 631; VI-LABEL: lshr_v_imm_v4i16: 632; VI: ; %bb.0: 633; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 634; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 635; VI-NEXT: s_waitcnt lgkmcnt(0) 636; VI-NEXT: v_mov_b32_e32 v1, s3 637; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 638; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 639; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] 640; VI-NEXT: v_mov_b32_e32 v3, s1 641; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 642; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 643; VI-NEXT: s_waitcnt vmcnt(0) 644; VI-NEXT: v_lshrrev_b32_e32 v4, 24, v1 645; VI-NEXT: v_lshrrev_b32_e32 v5, 24, v0 646; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 647; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 648; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD 649; VI-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD 650; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] 651; VI-NEXT: s_endpgm 652; 653; CI-LABEL: lshr_v_imm_v4i16: 654; CI: ; %bb.0: 655; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 656; CI-NEXT: s_mov_b32 s7, 0xf000 657; CI-NEXT: s_mov_b32 s6, 0 658; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 659; CI-NEXT: v_mov_b32_e32 v1, 0 660; CI-NEXT: s_waitcnt lgkmcnt(0) 661; CI-NEXT: s_mov_b64 s[4:5], s[2:3] 662; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 663; CI-NEXT: s_mov_b64 s[2:3], s[6:7] 664; CI-NEXT: s_waitcnt vmcnt(0) 665; CI-NEXT: v_lshrrev_b32_e32 v3, 8, v3 666; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2 667; CI-NEXT: v_and_b32_e32 v3, 0xff00ff, v3 668; CI-NEXT: v_and_b32_e32 v2, 0xff00ff, v2 669; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 670; CI-NEXT: s_endpgm 671; 672; GFX10-LABEL: lshr_v_imm_v4i16: 673; GFX10: ; %bb.0: 674; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 675; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 676; GFX10-NEXT: s_waitcnt lgkmcnt(0) 677; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] 678; GFX10-NEXT: s_waitcnt vmcnt(0) 679; GFX10-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1] 680; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1] 681; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] 682; GFX10-NEXT: s_endpgm 683; 684; GFX11-LABEL: lshr_v_imm_v4i16: 685; GFX11: ; %bb.0: 686; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 687; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0 688; GFX11-NEXT: s_waitcnt lgkmcnt(0) 689; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3] 690; GFX11-NEXT: s_waitcnt vmcnt(0) 691; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1] 692; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1] 693; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] 694; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 695; GFX11-NEXT: s_endpgm 696 %tid = call i32 @llvm.amdgcn.workitem.id.x() 697 %tid.ext = sext i32 %tid to i64 698 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext 699 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext 700 %vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep 701 %result = lshr <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8> 702 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep 703 ret void 704} 705 706declare i32 @llvm.amdgcn.workitem.id.x() #1 707 708attributes #0 = { nounwind } 709attributes #1 = { nounwind readnone } 710