1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck %s
3
4# %bb.1 and %bb.3 loop back to each other, and thus neither dominates
5# the other.
6# When the phi in %bb.3 is handled, it attempted to insert instructions
7# in %bb.1 to handle this def, but ended up inserting mask management
8# instructions before the def of %34. This is avoided by treating
9# IMPLICIT_DEF specially like constants
10
11---
12name:            recursive_vreg_1_phi
13tracksRegLiveness: true
14machineFunctionInfo:
15  isEntryFunction: true
16body:             |
17  ; CHECK-LABEL: name: recursive_vreg_1_phi
18  ; CHECK: bb.0:
19  ; CHECK:   successors: %bb.1(0x80000000)
20  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16
21  ; CHECK:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
22  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 20
23  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
24  ; CHECK:   [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
25  ; CHECK:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 10
26  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
27  ; CHECK:   [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
28  ; CHECK:   [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
29  ; CHECK:   [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 killed [[DEF3]], killed [[DEF1]], implicit $exec
30  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31  ; CHECK:   [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
32  ; CHECK:   [[V_ASHRREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 31, [[COPY2]], implicit $exec
33  ; CHECK:   [[DEF5:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
34  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_ASHRREV_I32_e32_]], %subreg.sub1
35  ; CHECK:   [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 2
36  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY killed [[S_MOV_B32_2]]
37  ; CHECK:   [[V_LSHL_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_B64_e64 killed [[REG_SEQUENCE]], [[COPY3]], implicit $exec
38  ; CHECK:   [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD killed [[V_LSHL_B64_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)
39  ; CHECK:   [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
40  ; CHECK:   [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 68
41  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_4]]
42  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_3]]
43  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
44  ; CHECK:   [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 432
45  ; CHECK:   [[V_MAD_I64_I32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_I64_I32_e64_1:%[0-9]+]]:sreg_64 = V_MAD_I64_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[S_MOV_B32_5]], [[REG_SEQUENCE1]], 0, implicit $exec
46  ; CHECK:   [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
47  ; CHECK:   [[DEF6:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
48  ; CHECK: bb.1:
49  ; CHECK:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
50  ; CHECK:   [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF6]], %bb.0, %31, %bb.3
51  ; CHECK:   [[PHI1:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_]], %bb.0, %54, %bb.3
52  ; CHECK:   [[PHI2:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_3]], %bb.0, %29, %bb.3
53  ; CHECK:   [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 0
54  ; CHECK:   [[S_ANDN2_B64_:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[PHI]], $exec, implicit-def $scc
55  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_64 = COPY [[S_ANDN2_B64_]]
56  ; CHECK:   S_CMP_EQ_U32 [[PHI2]], killed [[S_MOV_B32_6]], implicit-def $scc
57  ; CHECK:   [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -1
58  ; CHECK:   [[DEF7:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
59  ; CHECK:   S_CBRANCH_SCC1 %bb.3, implicit $scc
60  ; CHECK:   S_BRANCH %bb.2
61  ; CHECK: bb.2:
62  ; CHECK:   successors: %bb.3(0x80000000)
63  ; CHECK:   [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[V_MAD_I64_I32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)
64  ; CHECK:   [[S_MOV_B32_7:%[0-9]+]]:sreg_32 = S_MOV_B32 6
65  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_7]]
66  ; CHECK:   [[V_LSHR_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHR_B32_e32 killed [[FLAT_LOAD_DWORD1]], killed [[COPY7]], implicit $exec
67  ; CHECK:   [[DEF8:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
68  ; CHECK:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 1, [[V_LSHR_B32_e32_]], implicit $exec
69  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_AND_B32_e64_]], 1, implicit $exec
70  ; CHECK:   [[COPY8:%[0-9]+]]:sreg_64 = COPY [[PHI1]]
71  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY8]], killed [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
72  ; CHECK:   [[COPY9:%[0-9]+]]:sreg_64 = COPY [[PHI1]]
73  ; CHECK:   [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 killed [[S_AND_B64_]], [[COPY9]], implicit-def dead $scc
74  ; CHECK:   [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 0
75  ; CHECK:   [[DEF9:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
76  ; CHECK:   [[S_ANDN2_B64_1:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[COPY6]], $exec, implicit-def $scc
77  ; CHECK:   [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_OR_B64_]], $exec, implicit-def $scc
78  ; CHECK:   [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_ANDN2_B64_1]], [[S_AND_B64_1]], implicit-def $scc
79  ; CHECK: bb.3:
80  ; CHECK:   successors: %bb.4(0x00000000), %bb.1(0x80000000)
81  ; CHECK:   [[PHI3:%[0-9]+]]:sreg_64 = PHI [[COPY6]], %bb.1, [[S_OR_B64_1]], %bb.2
82  ; CHECK:   [[PHI4:%[0-9]+]]:sreg_64 = PHI [[PHI1]], %bb.1, [[DEF9]], %bb.2
83  ; CHECK:   [[PHI5:%[0-9]+]]:sreg_64_xexec = PHI [[S_MOV_B64_1]], %bb.1, [[S_MOV_B64_2]], %bb.2
84  ; CHECK:   [[S_MOV_B32_8:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
85  ; CHECK:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[PHI5]], implicit $exec
86  ; CHECK:   [[S_MOV_B32_9:%[0-9]+]]:sreg_32 = S_MOV_B32 1
87  ; CHECK:   [[DEF10:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
88  ; CHECK:   V_CMP_NE_U32_e32 killed [[S_MOV_B32_9]], [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
89  ; CHECK:   $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
90  ; CHECK:   [[S_ANDN2_B64_2:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[PHI4]], $exec, implicit-def $scc
91  ; CHECK:   [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[PHI3]], $exec, implicit-def $scc
92  ; CHECK:   [[S_OR_B64_2:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_ANDN2_B64_2]], [[S_AND_B64_2]], implicit-def $scc
93  ; CHECK:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
94  ; CHECK:   S_BRANCH %bb.4
95  ; CHECK: bb.4:
96  bb.0:
97    liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16
98
99    %0:sreg_64 = IMPLICIT_DEF
100    %1:sreg_32 = S_MOV_B32 20
101    %2:vgpr_32 = COPY %1
102    %3:vgpr_32 = IMPLICIT_DEF
103    %4:sreg_32 = S_MOV_B32 10
104    %5:vgpr_32 = COPY %4
105    %6:vgpr_32 = IMPLICIT_DEF
106    %7:vgpr_32 = IMPLICIT_DEF
107    %8:vgpr_32 = V_OR_B32_e32 killed %7, killed %3, implicit $exec
108    %9:vgpr_32 = COPY $vgpr0
109    %10:sreg_32 = IMPLICIT_DEF
110    %11:vgpr_32 = V_ASHRREV_I32_e32 31, %9, implicit $exec
111    %12:sreg_32_xm0 = IMPLICIT_DEF
112    %13:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %11, %subreg.sub1
113    %14:sreg_32 = S_MOV_B32 2
114    %15:sgpr_32 = COPY killed %14
115    %16:vreg_64 = V_LSHL_B64_e64 killed %13, %15, implicit $exec
116    %17:vgpr_32 = FLAT_LOAD_DWORD killed %16, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)
117    %18:sreg_32 = S_MOV_B32 0
118    %19:sreg_32 = S_MOV_B32 68
119    %20:vgpr_32 = COPY killed %19
120    %21:vgpr_32 = COPY %18
121    %22:vreg_64 = REG_SEQUENCE killed %20, %subreg.sub0, %21, %subreg.sub1
122    %23:sreg_32 = S_MOV_B32 432
123    %24:vreg_64, %25:sreg_64 = V_MAD_I64_I32_e64 killed %17, killed %23, %22, 0, implicit $exec
124    %26:sreg_64 = S_MOV_B64 0
125    %27:vreg_1 = COPY %26, implicit $exec
126
127  bb.1:
128    successors: %bb.2, %bb.3
129
130    %28:sreg_32 = PHI %18, %bb.0, %29, %bb.3
131    %30:vreg_1 = PHI %27, %bb.0, %31, %bb.3
132    %32:sreg_32 = S_MOV_B32 0
133    S_CMP_EQ_U32 %28, killed %32, implicit-def $scc
134    %33:sreg_64 = S_MOV_B64 -1
135    %34:sreg_64 = IMPLICIT_DEF
136    %35:vreg_1 = COPY %34
137    S_CBRANCH_SCC1 %bb.3, implicit $scc
138    S_BRANCH %bb.2
139
140  bb.2:
141    %36:vgpr_32 = FLAT_LOAD_DWORD %24, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)
142    %37:sreg_32 = S_MOV_B32 6
143    %38:vgpr_32 = COPY %37
144    %39:vgpr_32 = V_LSHR_B32_e32 killed %36, killed %38, implicit $exec
145    %40:sreg_32 = IMPLICIT_DEF
146    %41:vgpr_32 = V_AND_B32_e64 1, %39, implicit $exec
147    %42:sreg_64 = V_CMP_EQ_U32_e64 killed %41, 1, implicit $exec
148    %43:sreg_64 = COPY %30
149    %44:sreg_64 = S_AND_B64 %43, killed %42, implicit-def dead $scc
150    %45:sreg_64 = COPY %30
151    %46:sreg_64 = S_OR_B64 killed %44, %45, implicit-def dead $scc
152    %47:sreg_64 = S_MOV_B64 0
153    %48:vreg_1 = COPY %46
154
155  bb.3:
156    successors: %bb.4(0x00000000), %bb.1(0x80000000)
157
158    %31:vreg_1 = PHI %35, %bb.1, %48, %bb.2
159    %49:sreg_64_xexec = PHI %33, %bb.1, %47, %bb.2
160    %29:sreg_32 = S_MOV_B32 -1
161    %50:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %49, implicit $exec
162    %51:sreg_32 = S_MOV_B32 1
163    %52:sreg_32 = IMPLICIT_DEF
164    V_CMP_NE_U32_e32 killed %51, %50, implicit-def $vcc, implicit $exec
165    $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
166    S_CBRANCH_VCCNZ %bb.1, implicit $vcc
167    S_BRANCH %bb.4
168
169  bb.4:
170
171...
172