1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; Combine on select c, (load x), (load y) -> load (select c, x, y)
4; drops MachinePointerInfo, so it can't be relied on for correctness.
5
6; GCN-LABEL: {{^}}select_ptr_crash_i64_flat:
7; GCN: s_load_dwordx2
8; GCN: s_load_dwordx2
9; GCN: s_load_dwordx2
10
11; GCN: s_cmp_eq_u32
12; GCN: s_cselect_b64
13
14; GCN-NOT: load_dword
15; GCN: flat_load_dwordx2
16; GCN-NOT: load_dword
17
18; GCN: flat_store_dwordx2
19define amdgpu_kernel void @select_ptr_crash_i64_flat(i32 %tmp, [8 x i32], i64* %ptr0, [8 x i32], i64* %ptr1, [8 x i32], i64 addrspace(1)* %ptr2) {
20  %tmp2 = icmp eq i32 %tmp, 0
21  %tmp3 = load i64, i64* %ptr0, align 8
22  %tmp4 = load i64, i64* %ptr1, align 8
23  %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
24  store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
25  ret void
26}
27
28; The transform currently doesn't happen for non-addrspace 0, but it
29; should.
30
31; GCN-LABEL: {{^}}select_ptr_crash_i64_global:
32; GCN: s_load_dwordx2
33; GCN: s_load_dwordx2
34; GCN: s_load_dwordx2
35; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
36; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
37; GCN: s_cselect_b64
38; GCN: flat_store_dwordx2
39define amdgpu_kernel void @select_ptr_crash_i64_global(i32 %tmp, [8 x i32], i64 addrspace(1)* %ptr0, [8 x i32], i64 addrspace(1)* %ptr1, [8 x i32], i64 addrspace(1)* %ptr2) {
40  %tmp2 = icmp eq i32 %tmp, 0
41  %tmp3 = load i64, i64 addrspace(1)* %ptr0, align 8
42  %tmp4 = load i64, i64 addrspace(1)* %ptr1, align 8
43  %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
44  store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
45  ret void
46}
47
48; GCN-LABEL: {{^}}select_ptr_crash_i64_local:
49; GCN: ds_read_b64
50; GCN: ds_read_b64
51; GCN: v_cndmask_b32
52; GCN: v_cndmask_b32
53; GCN: flat_store_dwordx2
54define amdgpu_kernel void @select_ptr_crash_i64_local(i32 %tmp, i64 addrspace(3)* %ptr0, i64 addrspace(3)* %ptr1, i64 addrspace(1)* %ptr2) {
55  %tmp2 = icmp eq i32 %tmp, 0
56  %tmp3 = load i64, i64 addrspace(3)* %ptr0, align 8
57  %tmp4 = load i64, i64 addrspace(3)* %ptr1, align 8
58  %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
59  store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
60  ret void
61}
62
63; The transform will break addressing mode matching, so unclear it
64; would be good to do
65
66; GCN-LABEL: {{^}}select_ptr_crash_i64_local_offsets:
67; GCN: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:128
68; GCN: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:512
69; GCN: v_cndmask_b32
70; GCN: v_cndmask_b32
71define amdgpu_kernel void @select_ptr_crash_i64_local_offsets(i32 %tmp, i64 addrspace(3)* %ptr0, i64 addrspace(3)* %ptr1, i64 addrspace(1)* %ptr2) {
72  %tmp2 = icmp eq i32 %tmp, 0
73  %gep0 = getelementptr inbounds i64, i64 addrspace(3)* %ptr0, i64 16
74  %gep1 = getelementptr inbounds i64, i64 addrspace(3)* %ptr1, i64 64
75  %tmp3 = load i64, i64 addrspace(3)* %gep0, align 8
76  %tmp4 = load i64, i64 addrspace(3)* %gep1, align 8
77  %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
78  store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
79  ret void
80}
81