1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s 2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s 3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s 4; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 5 6; FUNC-LABEL: {{^}}constant_load_i16: 7; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}} 8; GCN-HSA: flat_load_ushort 9 10; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 11define void @constant_load_i16(i16 addrspace(1)* %out, i16 addrspace(2)* %in) { 12entry: 13 %ld = load i16, i16 addrspace(2)* %in 14 store i16 %ld, i16 addrspace(1)* %out 15 ret void 16} 17 18; FUNC-LABEL: {{^}}constant_load_v2i16: 19; GCN: s_load_dword s 20 21; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 22define void @constant_load_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) { 23entry: 24 %ld = load <2 x i16>, <2 x i16> addrspace(2)* %in 25 store <2 x i16> %ld, <2 x i16> addrspace(1)* %out 26 ret void 27} 28 29; FUNC-LABEL: {{^}}constant_load_v3i16: 30; GCN: s_load_dwordx2 s 31 32; EG-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 33; EG-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4, #1 34define void @constant_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { 35entry: 36 %ld = load <3 x i16>, <3 x i16> addrspace(2)* %in 37 store <3 x i16> %ld, <3 x i16> addrspace(1)* %out 38 ret void 39} 40 41; FUNC-LABEL: {{^}}constant_load_v4i16: 42; GCN: s_load_dwordx2 43 44; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 45define void @constant_load_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) { 46entry: 47 %ld = load <4 x i16>, <4 x i16> addrspace(2)* %in 48 store <4 x i16> %ld, <4 x i16> addrspace(1)* %out 49 ret void 50} 51 52; FUNC-LABEL: {{^}}constant_load_v8i16: 53; GCN: s_load_dwordx4 54 55; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 56define void @constant_load_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) { 57entry: 58 %ld = load <8 x i16>, <8 x i16> addrspace(2)* %in 59 store <8 x i16> %ld, <8 x i16> addrspace(1)* %out 60 ret void 61} 62 63; FUNC-LABEL: {{^}}constant_load_v16i16: 64; GCN: s_load_dwordx8 65 66; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 67; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 68define void @constant_load_v16i16(<16 x i16> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) { 69entry: 70 %ld = load <16 x i16>, <16 x i16> addrspace(2)* %in 71 store <16 x i16> %ld, <16 x i16> addrspace(1)* %out 72 ret void 73} 74 75; FUNC-LABEL: {{^}}constant_zextload_i16_to_i32: 76; GCN-NOHSA: buffer_load_ushort 77; GCN-NOHSA: buffer_store_dword 78 79; GCN-HSA: flat_load_ushort 80; GCN-HSA: flat_store_dword 81 82; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}, 0, #1 83define void @constant_zextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { 84 %a = load i16, i16 addrspace(2)* %in 85 %ext = zext i16 %a to i32 86 store i32 %ext, i32 addrspace(1)* %out 87 ret void 88} 89 90; FUNC-LABEL: {{^}}constant_sextload_i16_to_i32: 91; GCN-NOHSA: buffer_load_sshort 92; GCN-NOHSA: buffer_store_dword 93 94; GCN-HSA: flat_load_sshort 95; GCN-HSA: flat_store_dword 96 97; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 98; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal 99; EG: 16 100define void @constant_sextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { 101 %a = load i16, i16 addrspace(2)* %in 102 %ext = sext i16 %a to i32 103 store i32 %ext, i32 addrspace(1)* %out 104 ret void 105} 106 107; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i32: 108; GCN-NOHSA: buffer_load_ushort 109; GCN-HSA: flat_load_ushort 110 111; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}, 0, #1 112define void @constant_zextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { 113 %load = load <1 x i16>, <1 x i16> addrspace(2)* %in 114 %ext = zext <1 x i16> %load to <1 x i32> 115 store <1 x i32> %ext, <1 x i32> addrspace(1)* %out 116 ret void 117} 118 119; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i32: 120; GCN-NOHSA: buffer_load_sshort 121; GCN-HSA: flat_load_sshort 122 123; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 124; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal 125; EG: 16 126define void @constant_sextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { 127 %load = load <1 x i16>, <1 x i16> addrspace(2)* %in 128 %ext = sext <1 x i16> %load to <1 x i32> 129 store <1 x i32> %ext, <1 x i32> addrspace(1)* %out 130 ret void 131} 132 133; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i32: 134; GCN: s_load_dword s 135; GCN-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0xffff{{$}} 136; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 137 138; v2i16 is naturally 4 byte aligned 139; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 140; TODO: This should use DST, but for some there are redundant MOVs 141; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal 142; EG: 16 143define void @constant_zextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { 144 %load = load <2 x i16>, <2 x i16> addrspace(2)* %in 145 %ext = zext <2 x i16> %load to <2 x i32> 146 store <2 x i32> %ext, <2 x i32> addrspace(1)* %out 147 ret void 148} 149 150; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i32: 151; GCN: s_load_dword s 152; GCN-DAG: s_ashr_i32 153; GCN-DAG: s_sext_i32_i16 154 155; v2i16 is naturally 4 byte aligned 156; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 157; TODO: These should use DST, but for some there are redundant MOVs 158; TODO: We should also use ASHR instead of LSHR + BFE 159; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, 0.0, literal 160; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, 0.0, literal 161; EG-DAG: 16 162; EG-DAG: 16 163define void @constant_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { 164 %load = load <2 x i16>, <2 x i16> addrspace(2)* %in 165 %ext = sext <2 x i16> %load to <2 x i32> 166 store <2 x i32> %ext, <2 x i32> addrspace(1)* %out 167 ret void 168} 169 170; FUNC-LABEL: {{^}}constant_constant_zextload_v3i16_to_v3i32: 171; GCN: s_load_dwordx2 172 173; v3i16 is naturally 8 byte aligned 174; EG-DAG: VTX_READ_32 [[DST_HI:T[0-9]\.[XYZW]]], [[DST_HI]], 0, #1 175; EG-DAG: VTX_READ_16 [[DST_LO:T[0-9]\.[XYZW]]], [[DST_LO]], 4, #1 176; TODO: This should use DST, but for some there are redundant MOVs 177; EG: LSHR {{[* ]*}}{{T[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal 178; EG: 16 179define void @constant_constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { 180entry: 181 %ld = load <3 x i16>, <3 x i16> addrspace(2)* %in 182 %ext = zext <3 x i16> %ld to <3 x i32> 183 store <3 x i32> %ext, <3 x i32> addrspace(1)* %out 184 ret void 185} 186 187; FUNC-LABEL: {{^}}constant_constant_sextload_v3i16_to_v3i32: 188; GCN: s_load_dwordx2 189 190; v3i16 is naturally 8 byte aligned 191; EG-DAG: VTX_READ_32 [[DST_HI:T[0-9]\.[XYZW]]], [[DST_HI]], 0, #1 192; EG-DAG: VTX_READ_16 [[DST_LO:T[0-9]\.[XYZW]]], [[DST_LO]], 4, #1 193; TODO: These should use DST, but for some there are redundant MOVs 194; EG-DAG: ASHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal 195; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, 0.0, literal 196; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, 0.0, literal 197; EG-DAG: 16 198; EG-DAG: 16 199define void @constant_constant_sextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { 200entry: 201 %ld = load <3 x i16>, <3 x i16> addrspace(2)* %in 202 %ext = sext <3 x i16> %ld to <3 x i32> 203 store <3 x i32> %ext, <3 x i32> addrspace(1)* %out 204 ret void 205} 206 207; FUNC-LABEL: {{^}}constant_constant_zextload_v4i16_to_v4i32: 208; GCN: s_load_dwordx2 209; GCN-DAG: s_and_b32 210; GCN-DAG: s_lshr_b32 211 212; v4i16 is naturally 8 byte aligned 213; EG: VTX_READ_64 [[DST:T[0-9]\.XY]], {{T[0-9].[XYZW]}}, 0, #1 214; TODO: These should use DST, but for some there are redundant MOVs 215; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{PV.[XYZW]}}, literal 216; EG-DAG: 16 217; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal 218; EG-DAG: AND_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{T[0-9].[XYZW]}}, literal 219; EG-DAG: 16 220define void @constant_constant_zextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { 221 %load = load <4 x i16>, <4 x i16> addrspace(2)* %in 222 %ext = zext <4 x i16> %load to <4 x i32> 223 store <4 x i32> %ext, <4 x i32> addrspace(1)* %out 224 ret void 225} 226 227; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i32: 228; GCN: s_load_dwordx2 229; GCN-DAG: s_ashr_i32 230; GCN-DAG: s_sext_i32_i16 231 232; v4i16 is naturally 8 byte aligned 233; EG: VTX_READ_64 [[DST:T[0-9]\.XY]], {{T[0-9].[XYZW]}}, 0, #1 234; TODO: These should use DST, but for some there are redundant MOVs 235; TODO: We should use ASHR instead of LSHR + BFE 236; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 237; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 238; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 239; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 240; EG-DAG: 16 241; EG-DAG: 16 242; EG-DAG: 16 243; EG-DAG: 16 244define void @constant_sextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { 245 %load = load <4 x i16>, <4 x i16> addrspace(2)* %in 246 %ext = sext <4 x i16> %load to <4 x i32> 247 store <4 x i32> %ext, <4 x i32> addrspace(1)* %out 248 ret void 249} 250 251; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i32: 252; GCN: s_load_dwordx4 253; GCN-DAG: s_and_b32 254; GCN-DAG: s_lshr_b32 255 256; v8i16 is naturally 16 byte aligned 257; EG: VTX_READ_128 [[DST:T[0-9]\.XYZW]], {{T[0-9].[XYZW]}}, 0, #1 258; TODO: These should use DST, but for some there are redundant MOVs 259; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 260; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 261; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 262; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 263; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 264; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 265; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 266; EG-DAG: LSHR {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, literal 267; EG-DAG: 16 268; EG-DAG: 16 269; EG-DAG: 16 270; EG-DAG: 16 271; EG-DAG: 16 272; EG-DAG: 16 273; EG-DAG: 16 274; EG-DAG: 16 275define void @constant_zextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { 276 %load = load <8 x i16>, <8 x i16> addrspace(2)* %in 277 %ext = zext <8 x i16> %load to <8 x i32> 278 store <8 x i32> %ext, <8 x i32> addrspace(1)* %out 279 ret void 280} 281 282; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i32: 283; GCN: s_load_dwordx4 284; GCN-DAG: s_ashr_i32 285; GCN-DAG: s_sext_i32_i16 286 287; v8i16 is naturally 16 byte aligned 288; EG: VTX_READ_128 [[DST:T[0-9]\.XYZW]], {{T[0-9].[XYZW]}}, 0, #1 289; TODO: These should use DST, but for some there are redundant MOVs 290; TODO: We should use ASHR instead of LSHR + BFE 291; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 292; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 293; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 294; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 295; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 296; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 297; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 298; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal 299; EG-DAG: 16 300; EG-DAG: 16 301; EG-DAG: 16 302; EG-DAG: 16 303; EG-DAG: 16 304; EG-DAG: 16 305; EG-DAG: 16 306; EG-DAG: 16 307define void @constant_sextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { 308 %load = load <8 x i16>, <8 x i16> addrspace(2)* %in 309 %ext = sext <8 x i16> %load to <8 x i32> 310 store <8 x i32> %ext, <8 x i32> addrspace(1)* %out 311 ret void 312} 313 314; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i32: 315; GCN: s_load_dwordx8 316; GCN-DAG: s_and_b32 317; GCN-DAG: s_lshr_b32 318 319; v16i16 is naturally 32 byte aligned 320; EG-DAG: VTX_READ_128 [[DST_HI:T[0-9]+\.XYZW]], {{T[0-9]+.[XYZW]}}, 0, #1 321; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], {{T[0-9]+.[XYZW]}}, 16, #1 322define void @constant_zextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { 323 %load = load <16 x i16>, <16 x i16> addrspace(2)* %in 324 %ext = zext <16 x i16> %load to <16 x i32> 325 store <16 x i32> %ext, <16 x i32> addrspace(1)* %out 326 ret void 327} 328 329; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i32: 330; GCN: s_load_dwordx8 331; GCN-DAG: s_ashr_i32 332; GCN-DAG: s_sext_i32_i16 333 334; v16i16 is naturally 32 byte aligned 335; EG-DAG: VTX_READ_128 [[DST_HI:T[0-9]+\.XYZW]], {{T[0-9]+\.[XYZW]}}, 0, #1 336; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], {{T[0-9]+\.[XYZW]}}, 16, #1 337define void @constant_sextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { 338 %load = load <16 x i16>, <16 x i16> addrspace(2)* %in 339 %ext = sext <16 x i16> %load to <16 x i32> 340 store <16 x i32> %ext, <16 x i32> addrspace(1)* %out 341 ret void 342} 343 344; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i32: 345; GCN-DAG: s_load_dwordx16 346; GCN-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} 347; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 348; GCN-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[K]] 349 350; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 351; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 352; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 353; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 354define void @constant_zextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { 355 %load = load <32 x i16>, <32 x i16> addrspace(2)* %in 356 %ext = zext <32 x i16> %load to <32 x i32> 357 store <32 x i32> %ext, <32 x i32> addrspace(1)* %out 358 ret void 359} 360 361; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i32: 362; GCN: s_load_dwordx16 363; GCN-DAG: s_ashr_i32 364; GCN-DAG: s_sext_i32_i16 365 366; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 367; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 368; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 369; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 370define void @constant_sextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { 371 %load = load <32 x i16>, <32 x i16> addrspace(2)* %in 372 %ext = sext <32 x i16> %load to <32 x i32> 373 store <32 x i32> %ext, <32 x i32> addrspace(1)* %out 374 ret void 375} 376 377; FUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i32: 378; GCN: s_load_dwordx16 379; GCN: s_load_dwordx16 380 381; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 382; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 383; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 384; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 385; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 64, #1 386; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 80, #1 387; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 96, #1 388; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 112, #1 389define void @constant_zextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { 390 %load = load <64 x i16>, <64 x i16> addrspace(2)* %in 391 %ext = zext <64 x i16> %load to <64 x i32> 392 store <64 x i32> %ext, <64 x i32> addrspace(1)* %out 393 ret void 394} 395 396; FUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i32: 397 398; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 399; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 400; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 401; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 402; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 64, #1 403; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 80, #1 404; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 96, #1 405; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 112, #1 406define void @constant_sextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { 407 %load = load <64 x i16>, <64 x i16> addrspace(2)* %in 408 %ext = sext <64 x i16> %load to <64 x i32> 409 store <64 x i32> %ext, <64 x i32> addrspace(1)* %out 410 ret void 411} 412 413; FUNC-LABEL: {{^}}constant_zextload_i16_to_i64: 414; GCN-NOHSA-DAG: buffer_load_ushort v[[LO:[0-9]+]], 415; GCN-HSA-DAG: flat_load_ushort v[[LO:[0-9]+]], 416; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} 417 418; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] 419; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} 420 421; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 422; EG: MOV {{.*}}, 0.0 423define void @constant_zextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { 424 %a = load i16, i16 addrspace(2)* %in 425 %ext = zext i16 %a to i64 426 store i64 %ext, i64 addrspace(1)* %out 427 ret void 428} 429 430; FUNC-LABEL: {{^}}constant_sextload_i16_to_i64: 431; FIXME: Need to optimize this sequence to avoid extra bfe: 432; t28: i32,ch = load<LD2[%in(addrspace=1)], anyext from i16> t12, t27, undef:i64 433; t31: i64 = any_extend t28 434; t33: i64 = sign_extend_inreg t31, ValueType:ch:i16 435 436; GCN-NOHSA-SI-DAG: buffer_load_sshort v[[LO:[0-9]+]], 437; GCN-HSA-DAG: flat_load_sshort v[[LO:[0-9]+]], 438; GCN-NOHSA-VI-DAG: buffer_load_ushort v[[ULO:[0-9]+]], 439; GCN-NOHSA-VI-DAG: v_bfe_i32 v[[LO:[0-9]+]], v[[ULO]], 0, 16 440; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] 441 442; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] 443; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} 444 445; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 446; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal 447; TODO: Why not 15 ? 448; EG: 31 449define void @constant_sextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { 450 %a = load i16, i16 addrspace(2)* %in 451 %ext = sext i16 %a to i64 452 store i64 %ext, i64 addrspace(1)* %out 453 ret void 454} 455 456; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i64: 457 458; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 459; EG: MOV {{.*}}, 0.0 460define void @constant_zextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { 461 %load = load <1 x i16>, <1 x i16> addrspace(2)* %in 462 %ext = zext <1 x i16> %load to <1 x i64> 463 store <1 x i64> %ext, <1 x i64> addrspace(1)* %out 464 ret void 465} 466 467; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i64: 468 469; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 470; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal 471; TODO: Why not 15 ? 472; EG: 31 473define void @constant_sextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { 474 %load = load <1 x i16>, <1 x i16> addrspace(2)* %in 475 %ext = sext <1 x i16> %load to <1 x i64> 476 store <1 x i64> %ext, <1 x i64> addrspace(1)* %out 477 ret void 478} 479 480; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i64: 481 482; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 483define void @constant_zextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { 484 %load = load <2 x i16>, <2 x i16> addrspace(2)* %in 485 %ext = zext <2 x i16> %load to <2 x i64> 486 store <2 x i64> %ext, <2 x i64> addrspace(1)* %out 487 ret void 488} 489 490; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i64: 491 492; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 493define void @constant_sextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { 494 %load = load <2 x i16>, <2 x i16> addrspace(2)* %in 495 %ext = sext <2 x i16> %load to <2 x i64> 496 store <2 x i64> %ext, <2 x i64> addrspace(1)* %out 497 ret void 498} 499 500; FUNC-LABEL: {{^}}constant_zextload_v4i16_to_v4i64: 501 502; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 503define void @constant_zextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { 504 %load = load <4 x i16>, <4 x i16> addrspace(2)* %in 505 %ext = zext <4 x i16> %load to <4 x i64> 506 store <4 x i64> %ext, <4 x i64> addrspace(1)* %out 507 ret void 508} 509 510; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i64: 511 512; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 513define void @constant_sextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { 514 %load = load <4 x i16>, <4 x i16> addrspace(2)* %in 515 %ext = sext <4 x i16> %load to <4 x i64> 516 store <4 x i64> %ext, <4 x i64> addrspace(1)* %out 517 ret void 518} 519 520; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i64: 521 522; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 523define void @constant_zextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { 524 %load = load <8 x i16>, <8 x i16> addrspace(2)* %in 525 %ext = zext <8 x i16> %load to <8 x i64> 526 store <8 x i64> %ext, <8 x i64> addrspace(1)* %out 527 ret void 528} 529 530; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i64: 531 532; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 533define void @constant_sextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { 534 %load = load <8 x i16>, <8 x i16> addrspace(2)* %in 535 %ext = sext <8 x i16> %load to <8 x i64> 536 store <8 x i64> %ext, <8 x i64> addrspace(1)* %out 537 ret void 538} 539 540; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i64: 541 542; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 543; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 544define void @constant_zextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { 545 %load = load <16 x i16>, <16 x i16> addrspace(2)* %in 546 %ext = zext <16 x i16> %load to <16 x i64> 547 store <16 x i64> %ext, <16 x i64> addrspace(1)* %out 548 ret void 549} 550 551; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i64: 552 553; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 554; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 555define void @constant_sextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { 556 %load = load <16 x i16>, <16 x i16> addrspace(2)* %in 557 %ext = sext <16 x i16> %load to <16 x i64> 558 store <16 x i64> %ext, <16 x i64> addrspace(1)* %out 559 ret void 560} 561 562; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i64: 563 564; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 565; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 566; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 32, #1 567; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 48, #1 568define void @constant_zextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { 569 %load = load <32 x i16>, <32 x i16> addrspace(2)* %in 570 %ext = zext <32 x i16> %load to <32 x i64> 571 store <32 x i64> %ext, <32 x i64> addrspace(1)* %out 572 ret void 573} 574 575; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i64: 576 577; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 578; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 579; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 32, #1 580; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 48, #1 581define void @constant_sextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { 582 %load = load <32 x i16>, <32 x i16> addrspace(2)* %in 583 %ext = sext <32 x i16> %load to <32 x i64> 584 store <32 x i64> %ext, <32 x i64> addrspace(1)* %out 585 ret void 586} 587 588; These trigger undefined register machine verifier errors 589 590; ; XFUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i64: 591; define void @constant_zextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { 592; %load = load <64 x i16>, <64 x i16> addrspace(2)* %in 593; %ext = zext <64 x i16> %load to <64 x i64> 594; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out 595; ret void 596; } 597 598; ; XFUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i64: 599; define void @constant_sextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { 600; %load = load <64 x i16>, <64 x i16> addrspace(2)* %in 601; %ext = sext <64 x i16> %load to <64 x i64> 602; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out 603; ret void 604; } 605 606attributes #0 = { nounwind } 607