1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
3; RUN: llc -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=CI %s
4
5define amdgpu_kernel void @round_f64(double addrspace(1)* %out, double %x) #0 {
6; SI-LABEL: round_f64:
7; SI:       ; %bb.0:
8; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
9; SI-NEXT:    s_mov_b32 s6, -1
10; SI-NEXT:    s_mov_b32 s11, 0x80000
11; SI-NEXT:    s_mov_b32 s10, 0
12; SI-NEXT:    s_mov_b32 s7, 0xf000
13; SI-NEXT:    s_waitcnt lgkmcnt(0)
14; SI-NEXT:    s_mov_b32 s4, s0
15; SI-NEXT:    s_bfe_u32 s0, s3, 0xb0014
16; SI-NEXT:    s_add_i32 s12, s0, 0xfffffc01
17; SI-NEXT:    s_mov_b32 s5, s1
18; SI-NEXT:    s_mov_b32 s1, 0xfffff
19; SI-NEXT:    s_mov_b32 s0, s6
20; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s12
21; SI-NEXT:    s_and_b64 s[8:9], s[2:3], s[0:1]
22; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], s12
23; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
24; SI-NEXT:    v_mov_b32_e32 v1, s10
25; SI-NEXT:    v_mov_b32_e32 v0, s11
26; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
27; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
28; SI-NEXT:    v_mov_b32_e32 v2, s3
29; SI-NEXT:    v_add_i32_e32 v1, vcc, s2, v1
30; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
31; SI-NEXT:    v_not_b32_e32 v2, s0
32; SI-NEXT:    v_and_b32_e32 v2, v1, v2
33; SI-NEXT:    v_not_b32_e32 v1, s1
34; SI-NEXT:    v_and_b32_e32 v0, v0, v1
35; SI-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
36; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
37; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
38; SI-NEXT:    s_brev_b32 s0, -2
39; SI-NEXT:    v_mov_b32_e32 v3, s3
40; SI-NEXT:    v_bfi_b32 v1, s0, v1, v3
41; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
42; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
43; SI-NEXT:    v_mov_b32_e32 v1, s3
44; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
45; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
46; SI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
47; SI-NEXT:    v_mov_b32_e32 v2, s2
48; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
49; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
50; SI-NEXT:    s_endpgm
51;
52; CI-LABEL: round_f64:
53; CI:       ; %bb.0:
54; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
55; CI-NEXT:    s_brev_b32 s8, -2
56; CI-NEXT:    v_mov_b32_e32 v4, 0x3ff00000
57; CI-NEXT:    s_mov_b32 s3, 0xf000
58; CI-NEXT:    s_mov_b32 s2, -1
59; CI-NEXT:    s_waitcnt lgkmcnt(0)
60; CI-NEXT:    v_trunc_f64_e32 v[0:1], s[6:7]
61; CI-NEXT:    v_mov_b32_e32 v5, s7
62; CI-NEXT:    v_add_f64 v[2:3], s[6:7], -v[0:1]
63; CI-NEXT:    v_bfi_b32 v4, s8, v4, v5
64; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
65; CI-NEXT:    v_mov_b32_e32 v2, 0
66; CI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
67; CI-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
68; CI-NEXT:    s_mov_b32 s0, s4
69; CI-NEXT:    s_mov_b32 s1, s5
70; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
71; CI-NEXT:    s_endpgm
72  %result = call double @llvm.round.f64(double %x) #1
73  store double %result, double addrspace(1)* %out
74  ret void
75}
76
77define amdgpu_kernel void @v_round_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
78; SI-LABEL: v_round_f64:
79; SI:       ; %bb.0:
80; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
81; SI-NEXT:    s_mov_b32 s7, 0xf000
82; SI-NEXT:    s_mov_b32 s6, 0
83; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
84; SI-NEXT:    v_mov_b32_e32 v1, 0
85; SI-NEXT:    s_waitcnt lgkmcnt(0)
86; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]
87; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
88; SI-NEXT:    s_movk_i32 s9, 0xfc01
89; SI-NEXT:    s_mov_b32 s5, 0xfffff
90; SI-NEXT:    s_mov_b32 s4, -1
91; SI-NEXT:    v_mov_b32_e32 v8, 0x3ff00000
92; SI-NEXT:    s_brev_b32 s8, -2
93; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]
94; SI-NEXT:    s_mov_b32 s7, 0x80000
95; SI-NEXT:    s_waitcnt vmcnt(0)
96; SI-NEXT:    v_bfe_u32 v4, v3, 20, 11
97; SI-NEXT:    v_add_i32_e32 v10, vcc, s9, v4
98; SI-NEXT:    v_lshr_b64 v[4:5], s[4:5], v10
99; SI-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v10
100; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
101; SI-NEXT:    v_bfi_b32 v11, s8, v8, v3
102; SI-NEXT:    v_and_b32_e32 v9, v3, v5
103; SI-NEXT:    v_and_b32_e32 v8, v2, v4
104; SI-NEXT:    v_lshr_b64 v[6:7], s[6:7], v10
105; SI-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
106; SI-NEXT:    v_not_b32_e32 v4, v4
107; SI-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
108; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
109; SI-NEXT:    v_add_i32_e32 v6, vcc, v2, v6
110; SI-NEXT:    v_addc_u32_e32 v7, vcc, v3, v7, vcc
111; SI-NEXT:    v_not_b32_e32 v5, v5
112; SI-NEXT:    v_and_b32_e32 v5, v7, v5
113; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v10
114; SI-NEXT:    v_and_b32_e32 v4, v6, v4
115; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
116; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
117; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 51, v10
118; SI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
119; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
120; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
121; SI-NEXT:    s_endpgm
122;
123; CI-LABEL: v_round_f64:
124; CI:       ; %bb.0:
125; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
126; CI-NEXT:    s_mov_b32 s7, 0xf000
127; CI-NEXT:    s_mov_b32 s6, 0
128; CI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
129; CI-NEXT:    v_mov_b32_e32 v1, 0
130; CI-NEXT:    s_waitcnt lgkmcnt(0)
131; CI-NEXT:    s_mov_b64 s[4:5], s[2:3]
132; CI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
133; CI-NEXT:    s_brev_b32 s2, -2
134; CI-NEXT:    v_mov_b32_e32 v5, 0x3ff00000
135; CI-NEXT:    v_mov_b32_e32 v4, 0
136; CI-NEXT:    s_waitcnt vmcnt(0)
137; CI-NEXT:    v_trunc_f64_e32 v[6:7], v[2:3]
138; CI-NEXT:    v_add_f64 v[8:9], v[2:3], -v[6:7]
139; CI-NEXT:    v_bfi_b32 v2, s2, v5, v3
140; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[8:9]|, 0.5
141; CI-NEXT:    s_mov_b64 s[2:3], s[6:7]
142; CI-NEXT:    v_cndmask_b32_e32 v5, 0, v2, vcc
143; CI-NEXT:    v_add_f64 v[2:3], v[6:7], v[4:5]
144; CI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
145; CI-NEXT:    s_endpgm
146  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
147  %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
148  %out.gep = getelementptr double, double addrspace(1)* %out, i32 %tid
149  %x = load double, double addrspace(1)* %gep
150  %result = call double @llvm.round.f64(double %x) #1
151  store double %result, double addrspace(1)* %out.gep
152  ret void
153}
154
155define amdgpu_kernel void @round_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) #0 {
156; SI-LABEL: round_v2f64:
157; SI:       ; %bb.0:
158; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
159; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
160; SI-NEXT:    s_mov_b32 s6, -1
161; SI-NEXT:    s_movk_i32 s18, 0xfc01
162; SI-NEXT:    s_mov_b32 s3, 0xfffff
163; SI-NEXT:    s_mov_b32 s2, s6
164; SI-NEXT:    s_waitcnt lgkmcnt(0)
165; SI-NEXT:    s_bfe_u32 s0, s11, 0xb0014
166; SI-NEXT:    s_add_i32 s19, s0, s18
167; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s19
168; SI-NEXT:    s_and_b64 s[12:13], s[10:11], s[0:1]
169; SI-NEXT:    s_mov_b32 s15, 0x80000
170; SI-NEXT:    s_mov_b32 s14, 0
171; SI-NEXT:    s_lshr_b64 s[16:17], s[14:15], s19
172; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[12:13], 0
173; SI-NEXT:    v_mov_b32_e32 v1, s16
174; SI-NEXT:    v_mov_b32_e32 v0, s17
175; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
176; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
177; SI-NEXT:    v_mov_b32_e32 v2, s11
178; SI-NEXT:    v_add_i32_e32 v1, vcc, s10, v1
179; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
180; SI-NEXT:    v_not_b32_e32 v2, s0
181; SI-NEXT:    v_and_b32_e32 v1, v1, v2
182; SI-NEXT:    v_not_b32_e32 v2, s1
183; SI-NEXT:    v_mov_b32_e32 v4, 0x3ff00000
184; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s19, -1
185; SI-NEXT:    v_and_b32_e32 v0, v0, v2
186; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
187; SI-NEXT:    s_brev_b32 s12, -2
188; SI-NEXT:    v_mov_b32_e32 v3, s11
189; SI-NEXT:    v_bfi_b32 v2, s12, v2, v3
190; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s19, 0
191; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
192; SI-NEXT:    v_mov_b32_e32 v2, s11
193; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s19, 51
194; SI-NEXT:    v_cndmask_b32_e64 v3, v0, v2, s[0:1]
195; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
196; SI-NEXT:    v_mov_b32_e32 v1, s10
197; SI-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
198; SI-NEXT:    s_bfe_u32 s0, s9, 0xb0014
199; SI-NEXT:    s_add_i32 s13, s0, s18
200; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s13
201; SI-NEXT:    s_and_b64 s[2:3], s[8:9], s[0:1]
202; SI-NEXT:    s_lshr_b64 s[10:11], s[14:15], s13
203; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[2:3], 0
204; SI-NEXT:    v_mov_b32_e32 v1, s10
205; SI-NEXT:    v_mov_b32_e32 v0, s11
206; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
207; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
208; SI-NEXT:    v_mov_b32_e32 v5, s9
209; SI-NEXT:    v_add_i32_e32 v1, vcc, s8, v1
210; SI-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
211; SI-NEXT:    v_not_b32_e32 v5, s0
212; SI-NEXT:    v_and_b32_e32 v5, v1, v5
213; SI-NEXT:    v_not_b32_e32 v1, s1
214; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s13, -1
215; SI-NEXT:    v_and_b32_e32 v0, v0, v1
216; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
217; SI-NEXT:    v_mov_b32_e32 v4, s9
218; SI-NEXT:    v_bfi_b32 v1, s12, v1, v4
219; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s13, 0
220; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
221; SI-NEXT:    v_mov_b32_e32 v1, s9
222; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s13, 51
223; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
224; SI-NEXT:    v_cndmask_b32_e64 v0, v5, 0, vcc
225; SI-NEXT:    v_mov_b32_e32 v4, s8
226; SI-NEXT:    s_mov_b32 s7, 0xf000
227; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
228; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
229; SI-NEXT:    s_endpgm
230;
231; CI-LABEL: round_v2f64:
232; CI:       ; %bb.0:
233; CI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
234; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
235; CI-NEXT:    s_brev_b32 s6, -2
236; CI-NEXT:    v_mov_b32_e32 v6, 0x3ff00000
237; CI-NEXT:    s_mov_b32 s7, 0xf000
238; CI-NEXT:    s_waitcnt lgkmcnt(0)
239; CI-NEXT:    v_trunc_f64_e32 v[0:1], s[2:3]
240; CI-NEXT:    v_mov_b32_e32 v4, s3
241; CI-NEXT:    v_add_f64 v[2:3], s[2:3], -v[0:1]
242; CI-NEXT:    v_bfi_b32 v4, s6, v6, v4
243; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
244; CI-NEXT:    v_mov_b32_e32 v2, 0
245; CI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
246; CI-NEXT:    v_trunc_f64_e32 v[4:5], s[0:1]
247; CI-NEXT:    v_add_f64 v[2:3], v[0:1], v[2:3]
248; CI-NEXT:    v_add_f64 v[0:1], s[0:1], -v[4:5]
249; CI-NEXT:    v_mov_b32_e32 v7, s1
250; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
251; CI-NEXT:    v_bfi_b32 v6, s6, v6, v7
252; CI-NEXT:    v_cndmask_b32_e32 v1, 0, v6, vcc
253; CI-NEXT:    v_mov_b32_e32 v0, 0
254; CI-NEXT:    v_add_f64 v[0:1], v[4:5], v[0:1]
255; CI-NEXT:    s_mov_b32 s6, -1
256; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
257; CI-NEXT:    s_endpgm
258  %result = call <2 x double> @llvm.round.v2f64(<2 x double> %in) #1
259  store <2 x double> %result, <2 x double> addrspace(1)* %out
260  ret void
261}
262
263define amdgpu_kernel void @round_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) #0 {
264; SI-LABEL: round_v4f64:
265; SI:       ; %bb.0:
266; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
267; SI-NEXT:    s_load_dwordx8 s[8:15], s[0:1], 0x11
268; SI-NEXT:    s_mov_b32 s6, -1
269; SI-NEXT:    s_movk_i32 s22, 0xfc01
270; SI-NEXT:    s_mov_b32 s3, 0xfffff
271; SI-NEXT:    s_mov_b32 s2, s6
272; SI-NEXT:    s_waitcnt lgkmcnt(0)
273; SI-NEXT:    s_bfe_u32 s0, s11, 0xb0014
274; SI-NEXT:    s_add_i32 s23, s0, s22
275; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s23
276; SI-NEXT:    s_and_b64 s[16:17], s[10:11], s[0:1]
277; SI-NEXT:    s_mov_b32 s19, 0x80000
278; SI-NEXT:    s_mov_b32 s18, 0
279; SI-NEXT:    s_lshr_b64 s[20:21], s[18:19], s23
280; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[16:17], 0
281; SI-NEXT:    v_mov_b32_e32 v1, s20
282; SI-NEXT:    v_mov_b32_e32 v0, s21
283; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
284; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
285; SI-NEXT:    v_mov_b32_e32 v2, s11
286; SI-NEXT:    v_add_i32_e32 v1, vcc, s10, v1
287; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
288; SI-NEXT:    v_not_b32_e32 v2, s0
289; SI-NEXT:    v_and_b32_e32 v1, v1, v2
290; SI-NEXT:    v_not_b32_e32 v2, s1
291; SI-NEXT:    v_mov_b32_e32 v4, 0x3ff00000
292; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s23, -1
293; SI-NEXT:    v_and_b32_e32 v0, v0, v2
294; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
295; SI-NEXT:    s_brev_b32 s20, -2
296; SI-NEXT:    v_mov_b32_e32 v3, s11
297; SI-NEXT:    v_bfi_b32 v2, s20, v2, v3
298; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s23, 0
299; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
300; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s23, 51
301; SI-NEXT:    v_cndmask_b32_e64 v3, v0, v3, s[0:1]
302; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
303; SI-NEXT:    v_mov_b32_e32 v1, s10
304; SI-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
305; SI-NEXT:    s_bfe_u32 s0, s9, 0xb0014
306; SI-NEXT:    s_add_i32 s21, s0, s22
307; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s21
308; SI-NEXT:    s_and_b64 s[10:11], s[8:9], s[0:1]
309; SI-NEXT:    s_lshr_b64 s[16:17], s[18:19], s21
310; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[10:11], 0
311; SI-NEXT:    v_mov_b32_e32 v1, s16
312; SI-NEXT:    v_mov_b32_e32 v0, s17
313; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
314; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
315; SI-NEXT:    v_mov_b32_e32 v5, s9
316; SI-NEXT:    v_add_i32_e32 v1, vcc, s8, v1
317; SI-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
318; SI-NEXT:    v_not_b32_e32 v5, s0
319; SI-NEXT:    v_and_b32_e32 v5, v1, v5
320; SI-NEXT:    v_not_b32_e32 v1, s1
321; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s21, -1
322; SI-NEXT:    v_and_b32_e32 v0, v0, v1
323; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
324; SI-NEXT:    v_mov_b32_e32 v6, s9
325; SI-NEXT:    v_bfi_b32 v1, s20, v1, v6
326; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s21, 0
327; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
328; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s21, 51
329; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v6, s[0:1]
330; SI-NEXT:    v_cndmask_b32_e64 v0, v5, 0, vcc
331; SI-NEXT:    v_mov_b32_e32 v5, s8
332; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v5, s[0:1]
333; SI-NEXT:    s_bfe_u32 s0, s15, 0xb0014
334; SI-NEXT:    s_add_i32 s16, s0, s22
335; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s16
336; SI-NEXT:    s_and_b64 s[8:9], s[14:15], s[0:1]
337; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], s16
338; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
339; SI-NEXT:    v_mov_b32_e32 v6, s10
340; SI-NEXT:    v_mov_b32_e32 v5, s11
341; SI-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
342; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
343; SI-NEXT:    v_mov_b32_e32 v7, s15
344; SI-NEXT:    v_add_i32_e32 v6, vcc, s14, v6
345; SI-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
346; SI-NEXT:    v_not_b32_e32 v7, s0
347; SI-NEXT:    v_and_b32_e32 v6, v6, v7
348; SI-NEXT:    v_not_b32_e32 v7, s1
349; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s16, -1
350; SI-NEXT:    v_and_b32_e32 v5, v5, v7
351; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v4, vcc
352; SI-NEXT:    v_mov_b32_e32 v8, s15
353; SI-NEXT:    v_bfi_b32 v7, s20, v7, v8
354; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s16, 0
355; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
356; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s16, 51
357; SI-NEXT:    v_cndmask_b32_e64 v7, v5, v8, s[0:1]
358; SI-NEXT:    v_cndmask_b32_e64 v5, v6, 0, vcc
359; SI-NEXT:    v_mov_b32_e32 v6, s14
360; SI-NEXT:    v_cndmask_b32_e64 v6, v5, v6, s[0:1]
361; SI-NEXT:    s_bfe_u32 s0, s13, 0xb0014
362; SI-NEXT:    s_add_i32 s10, s0, s22
363; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s10
364; SI-NEXT:    s_and_b64 s[2:3], s[12:13], s[0:1]
365; SI-NEXT:    s_lshr_b64 s[8:9], s[18:19], s10
366; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[2:3], 0
367; SI-NEXT:    v_mov_b32_e32 v8, s8
368; SI-NEXT:    v_mov_b32_e32 v5, s9
369; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
370; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
371; SI-NEXT:    v_mov_b32_e32 v9, s13
372; SI-NEXT:    v_add_i32_e32 v8, vcc, s12, v8
373; SI-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
374; SI-NEXT:    v_not_b32_e32 v9, s0
375; SI-NEXT:    v_and_b32_e32 v8, v8, v9
376; SI-NEXT:    v_not_b32_e32 v9, s1
377; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s10, -1
378; SI-NEXT:    v_and_b32_e32 v5, v5, v9
379; SI-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
380; SI-NEXT:    v_mov_b32_e32 v9, s13
381; SI-NEXT:    v_bfi_b32 v4, s20, v4, v9
382; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s10, 0
383; SI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
384; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s10, 51
385; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v9, s[0:1]
386; SI-NEXT:    v_cndmask_b32_e64 v4, v8, 0, vcc
387; SI-NEXT:    v_mov_b32_e32 v8, s12
388; SI-NEXT:    s_mov_b32 s7, 0xf000
389; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[0:1]
390; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
391; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
392; SI-NEXT:    s_endpgm
393;
394; CI-LABEL: round_v4f64:
395; CI:       ; %bb.0:
396; CI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
397; CI-NEXT:    s_load_dwordx8 s[8:15], s[0:1], 0x11
398; CI-NEXT:    s_brev_b32 s2, -2
399; CI-NEXT:    v_mov_b32_e32 v12, 0x3ff00000
400; CI-NEXT:    s_mov_b32 s7, 0xf000
401; CI-NEXT:    s_mov_b32 s6, -1
402; CI-NEXT:    s_waitcnt lgkmcnt(0)
403; CI-NEXT:    v_trunc_f64_e32 v[0:1], s[10:11]
404; CI-NEXT:    v_mov_b32_e32 v4, s11
405; CI-NEXT:    v_add_f64 v[2:3], s[10:11], -v[0:1]
406; CI-NEXT:    v_bfi_b32 v4, s2, v12, v4
407; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
408; CI-NEXT:    v_trunc_f64_e32 v[8:9], s[8:9]
409; CI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
410; CI-NEXT:    v_mov_b32_e32 v2, 0
411; CI-NEXT:    v_add_f64 v[2:3], v[0:1], v[2:3]
412; CI-NEXT:    v_add_f64 v[0:1], s[8:9], -v[8:9]
413; CI-NEXT:    v_mov_b32_e32 v4, s9
414; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
415; CI-NEXT:    v_bfi_b32 v4, s2, v12, v4
416; CI-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
417; CI-NEXT:    v_trunc_f64_e32 v[4:5], s[14:15]
418; CI-NEXT:    v_mov_b32_e32 v10, s15
419; CI-NEXT:    v_add_f64 v[6:7], s[14:15], -v[4:5]
420; CI-NEXT:    v_bfi_b32 v10, s2, v12, v10
421; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
422; CI-NEXT:    v_mov_b32_e32 v6, 0
423; CI-NEXT:    v_cndmask_b32_e32 v7, 0, v10, vcc
424; CI-NEXT:    v_trunc_f64_e32 v[10:11], s[12:13]
425; CI-NEXT:    v_add_f64 v[6:7], v[4:5], v[6:7]
426; CI-NEXT:    v_add_f64 v[4:5], s[12:13], -v[10:11]
427; CI-NEXT:    v_mov_b32_e32 v13, s13
428; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
429; CI-NEXT:    v_bfi_b32 v12, s2, v12, v13
430; CI-NEXT:    v_cndmask_b32_e32 v5, 0, v12, vcc
431; CI-NEXT:    v_mov_b32_e32 v4, 0
432; CI-NEXT:    v_mov_b32_e32 v0, 0
433; CI-NEXT:    v_add_f64 v[4:5], v[10:11], v[4:5]
434; CI-NEXT:    v_add_f64 v[0:1], v[8:9], v[0:1]
435; CI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
436; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
437; CI-NEXT:    s_endpgm
438  %result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1
439  store <4 x double> %result, <4 x double> addrspace(1)* %out
440  ret void
441}
442
443define amdgpu_kernel void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %in) #0 {
444; SI-LABEL: round_v8f64:
445; SI:       ; %bb.0:
446; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
447; SI-NEXT:    s_load_dwordx16 s[8:23], s[0:1], 0x19
448; SI-NEXT:    s_mov_b32 s6, -1
449; SI-NEXT:    s_movk_i32 s30, 0xfc01
450; SI-NEXT:    s_mov_b32 s3, 0xfffff
451; SI-NEXT:    s_mov_b32 s2, s6
452; SI-NEXT:    s_waitcnt lgkmcnt(0)
453; SI-NEXT:    s_bfe_u32 s0, s11, 0xb0014
454; SI-NEXT:    s_add_i32 s31, s0, s30
455; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s31
456; SI-NEXT:    s_and_b64 s[26:27], s[10:11], s[0:1]
457; SI-NEXT:    s_mov_b32 s25, 0x80000
458; SI-NEXT:    s_mov_b32 s24, 0
459; SI-NEXT:    s_lshr_b64 s[28:29], s[24:25], s31
460; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[26:27], 0
461; SI-NEXT:    v_mov_b32_e32 v1, s28
462; SI-NEXT:    v_mov_b32_e32 v0, s29
463; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
464; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
465; SI-NEXT:    v_mov_b32_e32 v2, s11
466; SI-NEXT:    v_add_i32_e32 v1, vcc, s10, v1
467; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
468; SI-NEXT:    v_not_b32_e32 v2, s0
469; SI-NEXT:    v_and_b32_e32 v1, v1, v2
470; SI-NEXT:    v_not_b32_e32 v2, s1
471; SI-NEXT:    v_mov_b32_e32 v12, 0x3ff00000
472; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s31, -1
473; SI-NEXT:    v_and_b32_e32 v0, v0, v2
474; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v12, vcc
475; SI-NEXT:    s_brev_b32 s28, -2
476; SI-NEXT:    v_mov_b32_e32 v3, s11
477; SI-NEXT:    v_bfi_b32 v2, s28, v2, v3
478; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s31, 0
479; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
480; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s31, 51
481; SI-NEXT:    v_cndmask_b32_e64 v3, v0, v3, s[0:1]
482; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
483; SI-NEXT:    v_mov_b32_e32 v1, s10
484; SI-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
485; SI-NEXT:    s_bfe_u32 s0, s9, 0xb0014
486; SI-NEXT:    s_add_i32 s29, s0, s30
487; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s29
488; SI-NEXT:    s_and_b64 s[10:11], s[8:9], s[0:1]
489; SI-NEXT:    s_lshr_b64 s[26:27], s[24:25], s29
490; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[10:11], 0
491; SI-NEXT:    v_mov_b32_e32 v1, s26
492; SI-NEXT:    v_mov_b32_e32 v0, s27
493; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
494; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
495; SI-NEXT:    v_mov_b32_e32 v4, s9
496; SI-NEXT:    v_add_i32_e32 v1, vcc, s8, v1
497; SI-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
498; SI-NEXT:    v_not_b32_e32 v4, s0
499; SI-NEXT:    v_and_b32_e32 v4, v1, v4
500; SI-NEXT:    v_not_b32_e32 v1, s1
501; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s29, -1
502; SI-NEXT:    v_and_b32_e32 v0, v0, v1
503; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v12, vcc
504; SI-NEXT:    v_mov_b32_e32 v5, s9
505; SI-NEXT:    v_bfi_b32 v1, s28, v1, v5
506; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s29, 0
507; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
508; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s29, 51
509; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v5, s[0:1]
510; SI-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc
511; SI-NEXT:    v_mov_b32_e32 v4, s8
512; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
513; SI-NEXT:    s_bfe_u32 s0, s15, 0xb0014
514; SI-NEXT:    s_add_i32 s26, s0, s30
515; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s26
516; SI-NEXT:    s_and_b64 s[8:9], s[14:15], s[0:1]
517; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s26
518; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
519; SI-NEXT:    v_mov_b32_e32 v5, s10
520; SI-NEXT:    v_mov_b32_e32 v4, s11
521; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
522; SI-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
523; SI-NEXT:    v_mov_b32_e32 v6, s15
524; SI-NEXT:    v_add_i32_e32 v5, vcc, s14, v5
525; SI-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
526; SI-NEXT:    v_not_b32_e32 v6, s0
527; SI-NEXT:    v_and_b32_e32 v5, v5, v6
528; SI-NEXT:    v_not_b32_e32 v6, s1
529; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s26, -1
530; SI-NEXT:    v_and_b32_e32 v4, v4, v6
531; SI-NEXT:    v_cndmask_b32_e32 v6, 0, v12, vcc
532; SI-NEXT:    v_mov_b32_e32 v7, s15
533; SI-NEXT:    v_bfi_b32 v6, s28, v6, v7
534; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s26, 0
535; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
536; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s26, 51
537; SI-NEXT:    v_cndmask_b32_e64 v7, v4, v7, s[0:1]
538; SI-NEXT:    v_cndmask_b32_e64 v4, v5, 0, vcc
539; SI-NEXT:    v_mov_b32_e32 v5, s14
540; SI-NEXT:    v_cndmask_b32_e64 v6, v4, v5, s[0:1]
541; SI-NEXT:    s_bfe_u32 s0, s13, 0xb0014
542; SI-NEXT:    s_add_i32 s14, s0, s30
543; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s14
544; SI-NEXT:    s_and_b64 s[8:9], s[12:13], s[0:1]
545; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s14
546; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
547; SI-NEXT:    v_mov_b32_e32 v5, s10
548; SI-NEXT:    v_mov_b32_e32 v4, s11
549; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
550; SI-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
551; SI-NEXT:    v_mov_b32_e32 v8, s13
552; SI-NEXT:    v_add_i32_e32 v5, vcc, s12, v5
553; SI-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
554; SI-NEXT:    v_not_b32_e32 v8, s0
555; SI-NEXT:    v_and_b32_e32 v8, v5, v8
556; SI-NEXT:    v_not_b32_e32 v5, s1
557; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s14, -1
558; SI-NEXT:    v_and_b32_e32 v4, v4, v5
559; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v12, vcc
560; SI-NEXT:    v_mov_b32_e32 v9, s13
561; SI-NEXT:    v_bfi_b32 v5, s28, v5, v9
562; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s14, 0
563; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
564; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s14, 51
565; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v9, s[0:1]
566; SI-NEXT:    v_cndmask_b32_e64 v4, v8, 0, vcc
567; SI-NEXT:    v_mov_b32_e32 v8, s12
568; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[0:1]
569; SI-NEXT:    s_bfe_u32 s0, s19, 0xb0014
570; SI-NEXT:    s_add_i32 s12, s0, s30
571; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s12
572; SI-NEXT:    s_and_b64 s[8:9], s[18:19], s[0:1]
573; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s12
574; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
575; SI-NEXT:    v_mov_b32_e32 v9, s10
576; SI-NEXT:    v_mov_b32_e32 v8, s11
577; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v9, vcc
578; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
579; SI-NEXT:    v_mov_b32_e32 v10, s19
580; SI-NEXT:    v_add_i32_e32 v9, vcc, s18, v9
581; SI-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
582; SI-NEXT:    v_not_b32_e32 v10, s0
583; SI-NEXT:    v_and_b32_e32 v9, v9, v10
584; SI-NEXT:    v_not_b32_e32 v10, s1
585; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
586; SI-NEXT:    v_and_b32_e32 v8, v8, v10
587; SI-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
588; SI-NEXT:    v_mov_b32_e32 v11, s19
589; SI-NEXT:    v_bfi_b32 v10, s28, v10, v11
590; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
591; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v10, vcc
592; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
593; SI-NEXT:    v_cndmask_b32_e64 v11, v8, v11, s[0:1]
594; SI-NEXT:    v_cndmask_b32_e64 v8, v9, 0, vcc
595; SI-NEXT:    v_mov_b32_e32 v9, s18
596; SI-NEXT:    v_cndmask_b32_e64 v10, v8, v9, s[0:1]
597; SI-NEXT:    s_bfe_u32 s0, s17, 0xb0014
598; SI-NEXT:    s_add_i32 s12, s0, s30
599; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s12
600; SI-NEXT:    s_and_b64 s[8:9], s[16:17], s[0:1]
601; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s12
602; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
603; SI-NEXT:    v_mov_b32_e32 v9, s10
604; SI-NEXT:    v_mov_b32_e32 v8, s11
605; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v9, vcc
606; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
607; SI-NEXT:    v_mov_b32_e32 v13, s17
608; SI-NEXT:    v_add_i32_e32 v9, vcc, s16, v9
609; SI-NEXT:    v_addc_u32_e32 v8, vcc, v13, v8, vcc
610; SI-NEXT:    v_not_b32_e32 v13, s0
611; SI-NEXT:    v_and_b32_e32 v13, v9, v13
612; SI-NEXT:    v_not_b32_e32 v9, s1
613; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
614; SI-NEXT:    v_and_b32_e32 v8, v8, v9
615; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v12, vcc
616; SI-NEXT:    v_mov_b32_e32 v14, s17
617; SI-NEXT:    v_bfi_b32 v9, s28, v9, v14
618; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
619; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
620; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
621; SI-NEXT:    v_cndmask_b32_e64 v9, v8, v14, s[0:1]
622; SI-NEXT:    v_cndmask_b32_e64 v8, v13, 0, vcc
623; SI-NEXT:    v_mov_b32_e32 v13, s16
624; SI-NEXT:    v_cndmask_b32_e64 v8, v8, v13, s[0:1]
625; SI-NEXT:    s_bfe_u32 s0, s23, 0xb0014
626; SI-NEXT:    s_add_i32 s12, s0, s30
627; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s12
628; SI-NEXT:    s_and_b64 s[8:9], s[22:23], s[0:1]
629; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s12
630; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
631; SI-NEXT:    v_mov_b32_e32 v14, s10
632; SI-NEXT:    v_mov_b32_e32 v13, s11
633; SI-NEXT:    v_cndmask_b32_e32 v14, 0, v14, vcc
634; SI-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
635; SI-NEXT:    v_mov_b32_e32 v15, s23
636; SI-NEXT:    v_add_i32_e32 v14, vcc, s22, v14
637; SI-NEXT:    v_addc_u32_e32 v13, vcc, v15, v13, vcc
638; SI-NEXT:    v_not_b32_e32 v15, s0
639; SI-NEXT:    v_and_b32_e32 v14, v14, v15
640; SI-NEXT:    v_not_b32_e32 v15, s1
641; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
642; SI-NEXT:    v_and_b32_e32 v13, v13, v15
643; SI-NEXT:    v_cndmask_b32_e32 v15, 0, v12, vcc
644; SI-NEXT:    v_mov_b32_e32 v16, s23
645; SI-NEXT:    v_bfi_b32 v15, s28, v15, v16
646; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
647; SI-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc
648; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
649; SI-NEXT:    v_cndmask_b32_e64 v15, v13, v16, s[0:1]
650; SI-NEXT:    v_cndmask_b32_e64 v13, v14, 0, vcc
651; SI-NEXT:    v_mov_b32_e32 v14, s22
652; SI-NEXT:    v_cndmask_b32_e64 v14, v13, v14, s[0:1]
653; SI-NEXT:    s_bfe_u32 s0, s21, 0xb0014
654; SI-NEXT:    s_add_i32 s10, s0, s30
655; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s10
656; SI-NEXT:    s_and_b64 s[2:3], s[20:21], s[0:1]
657; SI-NEXT:    s_lshr_b64 s[8:9], s[24:25], s10
658; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[2:3], 0
659; SI-NEXT:    v_mov_b32_e32 v16, s8
660; SI-NEXT:    v_mov_b32_e32 v13, s9
661; SI-NEXT:    v_cndmask_b32_e32 v16, 0, v16, vcc
662; SI-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
663; SI-NEXT:    v_mov_b32_e32 v17, s21
664; SI-NEXT:    v_add_i32_e32 v16, vcc, s20, v16
665; SI-NEXT:    v_addc_u32_e32 v13, vcc, v17, v13, vcc
666; SI-NEXT:    v_not_b32_e32 v17, s0
667; SI-NEXT:    v_and_b32_e32 v16, v16, v17
668; SI-NEXT:    v_not_b32_e32 v17, s1
669; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s10, -1
670; SI-NEXT:    v_and_b32_e32 v13, v13, v17
671; SI-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
672; SI-NEXT:    v_mov_b32_e32 v17, s21
673; SI-NEXT:    v_bfi_b32 v12, s28, v12, v17
674; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s10, 0
675; SI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
676; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s10, 51
677; SI-NEXT:    v_cndmask_b32_e64 v13, v12, v17, s[0:1]
678; SI-NEXT:    v_cndmask_b32_e64 v12, v16, 0, vcc
679; SI-NEXT:    v_mov_b32_e32 v16, s20
680; SI-NEXT:    s_mov_b32 s7, 0xf000
681; SI-NEXT:    v_cndmask_b32_e64 v12, v12, v16, s[0:1]
682; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:48
683; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32
684; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
685; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
686; SI-NEXT:    s_endpgm
687;
688; CI-LABEL: round_v8f64:
689; CI:       ; %bb.0:
690; CI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
691; CI-NEXT:    s_load_dwordx16 s[8:23], s[0:1], 0x19
692; CI-NEXT:    s_brev_b32 s2, -2
693; CI-NEXT:    v_mov_b32_e32 v16, 0x3ff00000
694; CI-NEXT:    s_mov_b32 s7, 0xf000
695; CI-NEXT:    s_mov_b32 s6, -1
696; CI-NEXT:    s_waitcnt lgkmcnt(0)
697; CI-NEXT:    v_trunc_f64_e32 v[0:1], s[10:11]
698; CI-NEXT:    v_mov_b32_e32 v4, s11
699; CI-NEXT:    v_add_f64 v[2:3], s[10:11], -v[0:1]
700; CI-NEXT:    v_bfi_b32 v4, s2, v16, v4
701; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
702; CI-NEXT:    v_mov_b32_e32 v2, 0
703; CI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
704; CI-NEXT:    v_trunc_f64_e32 v[4:5], s[8:9]
705; CI-NEXT:    v_add_f64 v[2:3], v[0:1], v[2:3]
706; CI-NEXT:    v_add_f64 v[0:1], s[8:9], -v[4:5]
707; CI-NEXT:    v_mov_b32_e32 v6, s9
708; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
709; CI-NEXT:    v_bfi_b32 v6, s2, v16, v6
710; CI-NEXT:    v_cndmask_b32_e32 v1, 0, v6, vcc
711; CI-NEXT:    v_trunc_f64_e32 v[6:7], s[14:15]
712; CI-NEXT:    v_mov_b32_e32 v0, 0
713; CI-NEXT:    v_add_f64 v[0:1], v[4:5], v[0:1]
714; CI-NEXT:    v_add_f64 v[4:5], s[14:15], -v[6:7]
715; CI-NEXT:    v_mov_b32_e32 v8, s15
716; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
717; CI-NEXT:    v_bfi_b32 v8, s2, v16, v8
718; CI-NEXT:    v_cndmask_b32_e32 v5, 0, v8, vcc
719; CI-NEXT:    v_trunc_f64_e32 v[8:9], s[12:13]
720; CI-NEXT:    v_mov_b32_e32 v4, 0
721; CI-NEXT:    v_add_f64 v[6:7], v[6:7], v[4:5]
722; CI-NEXT:    v_add_f64 v[4:5], s[12:13], -v[8:9]
723; CI-NEXT:    v_mov_b32_e32 v10, s13
724; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
725; CI-NEXT:    v_bfi_b32 v10, s2, v16, v10
726; CI-NEXT:    v_cndmask_b32_e32 v5, 0, v10, vcc
727; CI-NEXT:    v_mov_b32_e32 v4, 0
728; CI-NEXT:    v_add_f64 v[4:5], v[8:9], v[4:5]
729; CI-NEXT:    v_mov_b32_e32 v8, s19
730; CI-NEXT:    v_bfi_b32 v18, s2, v16, v8
731; CI-NEXT:    v_trunc_f64_e32 v[8:9], s[20:21]
732; CI-NEXT:    v_trunc_f64_e32 v[10:11], s[22:23]
733; CI-NEXT:    v_add_f64 v[14:15], s[20:21], -v[8:9]
734; CI-NEXT:    v_mov_b32_e32 v19, s23
735; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
736; CI-NEXT:    v_add_f64 v[14:15], s[22:23], -v[10:11]
737; CI-NEXT:    v_mov_b32_e32 v17, s21
738; CI-NEXT:    v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
739; CI-NEXT:    v_bfi_b32 v19, s2, v16, v19
740; CI-NEXT:    v_trunc_f64_e32 v[12:13], s[16:17]
741; CI-NEXT:    v_bfi_b32 v17, s2, v16, v17
742; CI-NEXT:    v_cndmask_b32_e64 v15, 0, v19, s[0:1]
743; CI-NEXT:    v_mov_b32_e32 v14, 0
744; CI-NEXT:    v_add_f64 v[10:11], v[10:11], v[14:15]
745; CI-NEXT:    v_cndmask_b32_e32 v15, 0, v17, vcc
746; CI-NEXT:    v_mov_b32_e32 v14, 0
747; CI-NEXT:    v_mov_b32_e32 v17, s17
748; CI-NEXT:    v_add_f64 v[8:9], v[8:9], v[14:15]
749; CI-NEXT:    v_add_f64 v[14:15], s[16:17], -v[12:13]
750; CI-NEXT:    v_bfi_b32 v19, s2, v16, v17
751; CI-NEXT:    v_trunc_f64_e32 v[16:17], s[18:19]
752; CI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
753; CI-NEXT:    v_add_f64 v[14:15], s[18:19], -v[16:17]
754; CI-NEXT:    v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
755; CI-NEXT:    v_mov_b32_e32 v14, 0
756; CI-NEXT:    v_cndmask_b32_e64 v15, 0, v18, s[0:1]
757; CI-NEXT:    v_add_f64 v[14:15], v[16:17], v[14:15]
758; CI-NEXT:    v_cndmask_b32_e32 v17, 0, v19, vcc
759; CI-NEXT:    v_mov_b32_e32 v16, 0
760; CI-NEXT:    v_add_f64 v[12:13], v[12:13], v[16:17]
761; CI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48
762; CI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32
763; CI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
764; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
765; CI-NEXT:    s_endpgm
766  %result = call <8 x double> @llvm.round.v8f64(<8 x double> %in) #1
767  store <8 x double> %result, <8 x double> addrspace(1)* %out
768  ret void
769}
770
771declare i32 @llvm.amdgcn.workitem.id.x() #1
772
773declare double @llvm.round.f64(double) #1
774declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
775declare <4 x double> @llvm.round.v4f64(<4 x double>) #1
776declare <8 x double> @llvm.round.v8f64(<8 x double>) #1
777
778attributes #0 = { nounwind }
779attributes #1 = { nounwind readnone }
780