1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CIGFX9 %s
2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CIGFX9 %s
3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
4; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
5
6declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #0
7
8; CHECK-LABEL: {{^}}test_writelane_sreg:
9; CIGFX9: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, m0
10; GFX10: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
11define amdgpu_kernel void @test_writelane_sreg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
12  %oldval = load i32, i32 addrspace(1)* %out
13  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
14  store i32 %writelane, i32 addrspace(1)* %out, align 4
15  ret void
16}
17
18; CHECK-LABEL: {{^}}test_writelane_imm_sreg:
19; CHECK: v_writelane_b32 v{{[0-9]+}}, 32, s{{[0-9]+}}
20define amdgpu_kernel void @test_writelane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
21  %oldval = load i32, i32 addrspace(1)* %out
22  %writelane = call i32 @llvm.amdgcn.writelane(i32 32, i32 %src1, i32 %oldval)
23  store i32 %writelane, i32 addrspace(1)* %out, align 4
24  ret void
25}
26
27; CHECK-LABEL: {{^}}test_writelane_vreg_lane:
28; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
29; CHECK: v_writelane_b32 v{{[0-9]+}}, 12, [[LANE]]
30define amdgpu_kernel void @test_writelane_vreg_lane(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
31  %tid = call i32 @llvm.amdgcn.workitem.id.x()
32  %gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid
33  %args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
34  %oldval = load i32, i32 addrspace(1)* %out
35  %lane = extractelement <2 x i32> %args, i32 1
36  %writelane = call i32 @llvm.amdgcn.writelane(i32 12, i32 %lane, i32 %oldval)
37  store i32 %writelane, i32 addrspace(1)* %out, align 4
38  ret void
39}
40
41; CHECK-LABEL: {{^}}test_writelane_m0_sreg:
42; CHECK: s_mov_b32 m0, -1
43; CIGFX9: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
44; CIGFX9: v_writelane_b32 v{{[0-9]+}}, [[COPY_M0]], m0
45; GFX10: v_writelane_b32 v{{[0-9]+}}, m0, s{{[0-9]+}}
46define amdgpu_kernel void @test_writelane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
47  %oldval = load i32, i32 addrspace(1)* %out
48  %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
49  %writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %src1, i32 %oldval)
50  store i32 %writelane, i32 addrspace(1)* %out, align 4
51  ret void
52}
53
54; CHECK-LABEL: {{^}}test_writelane_imm:
55; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 32
56define amdgpu_kernel void @test_writelane_imm(i32 addrspace(1)* %out, i32 %src0) #1 {
57  %oldval = load i32, i32 addrspace(1)* %out
58  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 32, i32 %oldval) #0
59  store i32 %writelane, i32 addrspace(1)* %out, align 4
60  ret void
61}
62
63; CHECK-LABEL: {{^}}test_writelane_sreg_oldval:
64; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], s{{[0-9]+}}
65; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
66; GFX10: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
67define amdgpu_kernel void @test_writelane_sreg_oldval(i32 inreg %oldval, i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
68  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
69  store i32 %writelane, i32 addrspace(1)* %out, align 4
70  ret void
71}
72
73; CHECK-LABEL: {{^}}test_writelane_imm_oldval:
74; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], 42
75; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
76; GFX10: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
77define amdgpu_kernel void @test_writelane_imm_oldval(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
78  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 42)
79  store i32 %writelane, i32 addrspace(1)* %out, align 4
80  ret void
81}
82
83declare i32 @llvm.amdgcn.workitem.id.x() #2
84
85attributes #0 = { nounwind readnone convergent }
86attributes #1 = { nounwind }
87attributes #2 = { nounwind readnone }
88