1; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX906
2; RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX940
3; RUN: llc -march=amdgcn -mcpu=gfx940 -global-isel -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX940
4; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
5; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
6
7declare i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp)
8declare i32 @llvm.amdgcn.workitem.id.x()
9
10; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_clamp:
11; GFX9:   v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
12; GFX10:  v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
13define amdgpu_kernel void @test_llvm_amdgcn_udot2_clamp(
14    i32 addrspace(1)* %r,
15    <2 x i16> addrspace(1)* %a,
16    <2 x i16> addrspace(1)* %b,
17    i32 addrspace(1)* %c) {
18entry:
19  %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
20  %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
21  %c.val = load i32, i32 addrspace(1)* %c
22  %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1)
23  store i32 %r.val, i32 addrspace(1)* %r
24  ret void
25}
26
27; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_no_clamp:
28; GFX9:   v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
29; GFX10:  v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
30define amdgpu_kernel void @test_llvm_amdgcn_udot2_no_clamp(
31    i32 addrspace(1)* %r,
32    <2 x i16> addrspace(1)* %a,
33    <2 x i16> addrspace(1)* %b,
34    i32 addrspace(1)* %c) {
35entry:
36  %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
37  %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
38  %c.val = load i32, i32 addrspace(1)* %c
39  %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0)
40  store i32 %r.val, i32 addrspace(1)* %r
41  ret void
42}
43
44; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_op_sel:
45; GFX906: v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}} op_sel:[0,1,0] op_sel_hi:[0,0,1]{{$}}
46; GFX940: v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}}{{$}}
47; GFX10:  v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}} op_sel:[0,1,0] op_sel_hi:[0,0,1]{{$}}
48define amdgpu_kernel void @test_llvm_amdgcn_udot2_op_sel(
49    i32 addrspace(1)* %r,
50    <2 x i16> addrspace(1)* %b,
51    i32 %c) {
52entry:
53  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
54  %b.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %b, i32 %id
55  %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b.gep
56  %b.elt0 = extractelement <2 x i16> %b.val, i32 0
57  %b.elt1 = extractelement <2 x i16> %b.val, i32 1
58  %b0 = insertelement <2 x i16> undef, i16 %b.elt1, i32 0
59  %b1 = insertelement <2 x i16> %b0, i16 %b.elt0, i32 1
60  %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> <i16 1, i16 1>, <2 x i16> %b1, i32 %c, i1 0)
61  store i32 %r.val, i32 addrspace(1)* %r
62  ret void
63}
64